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author | Tristan Gingold <tgingold@free.fr> | 2020-03-21 14:05:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-21 14:05:01 +0100 |
commit | 234741f30661bbf2806fda277b6f16dbfb1a8c1c (patch) | |
tree | 6d064fc746d0679716829dd339098b512748b5ba | |
parent | 2615e17cd9cbd19e88b3093d30b0011435bd3eb2 (diff) | |
download | ghdl-234741f30661bbf2806fda277b6f16dbfb1a8c1c.tar.gz ghdl-234741f30661bbf2806fda277b6f16dbfb1a8c1c.tar.bz2 ghdl-234741f30661bbf2806fda277b6f16dbfb1a8c1c.zip |
testsuite/synth: add testcase for #1167
-rw-r--r-- | testsuite/synth/issue1167/bug.vhdl | 18 | ||||
-rwxr-xr-x | testsuite/synth/issue1167/testsuite.sh | 9 |
2 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/issue1167/bug.vhdl b/testsuite/synth/issue1167/bug.vhdl new file mode 100644 index 000000000..76ef78a01 --- /dev/null +++ b/testsuite/synth/issue1167/bug.vhdl @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + generic( + LEN : positive := 32 + ); + port( + input : in unsigned(LEN-1 downto 0); + output : out unsigned(LEN-1 downto 0) + ); +end bug; + +architecture behav of bug is +begin + output <= input and not to_unsigned(4096-1, input'length); +end architecture; diff --git a/testsuite/synth/issue1167/testsuite.sh b/testsuite/synth/issue1167/testsuite.sh new file mode 100755 index 000000000..2be3b2f1a --- /dev/null +++ b/testsuite/synth/issue1167/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_analyze bug + +clean + +echo "Test successful" |