pyHDL: CLI Update for DOM (#1808)

46 files changed, 1868 insertions, 750 deletions

diff --git a/pyGHDL/__init__.py b/pyGHDL/__init__.py
index 0324bd15d..eb400e0f1 100644
--- a/pyGHDL/__init__.py
+++ b/pyGHDL/__init__.py
@@ -52,4 +52,6 @@ from pydecor import export
 
 @export
 class GHDLBaseException(Exception):
-    pass
+    @property
+    def message(self) -> str:
+        return str(self)
diff --git a/pyGHDL/cli/DOM.py b/pyGHDL/cli/DOM.py
deleted file mode 100755
index 622a70d16..000000000
--- a/pyGHDL/cli/DOM.py
+++ /dev/null
@@ -1,121 +0,0 @@
-#!/usr/bin/env python3
-
-from sys import argv
-from sys import exit as sysexit
-
-from pathlib import Path
-from textwrap import dedent
-
-from pydecor import export
-
-from pyGHDL import GHDLBaseException
-from pyGHDL.libghdl import LibGHDLException
-from pyGHDL.dom import DOMException
-from pyGHDL.dom.NonStandard import Design, Document
-from pyGHDL.dom.formatting.prettyprint import PrettyPrint, PrettyPrintException
-
-__all__ = []
-__api__ = __all__
-
-
-@export
-class Application:
-    _design: Design
-
-    def __init__(self):
-        self._design = Design()
-
-    def addFile(self, filename: Path, library: str):
-        lib = self._design.GetLibrary(library)
-
-        document = Document(filename)
-        self._design.AddDocument(document, lib)
-
-    def prettyPrint(self):
-        PP = PrettyPrint()
-
-        buffer = []
-
-        buffer.append("Design:")
-        for line in PP.formatDesign(self._design, 1):
-            buffer.append(line)
-
-        print("\n".join(buffer))
-
-        document: Document = self._design.Documents[0]
-        print()
-        print(
-            "libghdl processing time: {: 5.3f} us".format(
-                document.LibGHDLProcessingTime * 10 ** 6
-            )
-        )
-        print(
-            "DOM translation time:    {:5.3f} us".format(
-                document.DOMTranslationTime * 10 ** 6
-            )
-        )
-
-
-def handleException(ex):
-    if isinstance(ex, PrettyPrintException):
-        print("PP:", ex)
-        return 0
-    elif isinstance(ex, DOMException):
-        print("DOM:", ex)
-        ex2 = ex.__cause__
-        if ex2 is not None:
-            for message in ex2.InternalErrors:
-                print("libghdl: {message}".format(message=message))
-            return 0
-        return 4
-    elif isinstance(ex, LibGHDLException):
-        print("LIB:", ex)
-        for message in ex.InternalErrors:
-            print("  {message}".format(message=message))
-        return 3
-    elif isinstance(ex, GHDLBaseException):
-        print("GHDL:", ex)
-        return 2
-    else:
-        print(
-            "Fatal: An unhandled exception has reached to the top-most exception handler."
-        )
-        return 1
-
-
-def main(items=argv[1:]):
-    _exitcode = 0
-
-    if len(items) < 1:
-        print("Please, provide the files to be analyzed as CLI arguments.")
-        print("Using <testsuite/pyunit/SimpleEntity.vhdl> for demo purposes.\n")
-        items = ["testsuite/pyunit/Current.vhdl"]
-
-    for item in items:
-        try:
-            app = Application()
-            app.addFile(Path(item), "default_lib")
-            app.prettyPrint()
-        except GHDLBaseException as ex:
-            _exitcode = handleException(ex)
-        except Exception as ex:
-            print(
-                dedent(
-                    """\
-                    Fatal: An unhandled exception has reached to the top-most exception handler.
-                    Exception: {name}
-                    """.format(
-                        name=ex.__class__.__name__
-                    )
-                )
-            )
-            if isinstance(ex, ValueError):
-                print("  Message: {msg}".format(msg=str(ex)))
-            if ex.__cause__ is not None:
-                print("Cause:     {msg}".format(msg=str(ex.__cause__)))
-
-    return _exitcode
-
-
-if __name__ == "__main__":
-    sysexit(main())
diff --git a/pyGHDL/cli/dom.py b/pyGHDL/cli/dom.py
new file mode 100755
index 000000000..2d0e85ea9
--- /dev/null
+++ b/pyGHDL/cli/dom.py
@@ -0,0 +1,374 @@
+#!/usr/bin/env python3
+# =============================================================================
+#               ____ _   _ ____  _          _
+#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
+# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
+# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
+# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
+# |_|    |___/
+# =============================================================================
+# Authors:
+#   Patrick Lehmann
+#   Unai Martinez-Corral
+#
+# Package module:   DOM: Interface items (e.g. generic or port)
+#
+# License:
+# ============================================================================
+#  Copyright (C) 2019-2021 Tristan Gingold
+#
+#  This program is free software: you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation, either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program.  If not, see <gnu.org/licenses>.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ============================================================================
+from argparse import RawDescriptionHelpFormatter
+from pathlib import Path
+from platform import system as platform_system
+from textwrap import wrap, dedent
+
+from pyGHDL.dom import DOMException
+
+from pyGHDL.libghdl import LibGHDLException
+from pydecor import export
+from pyMetaClasses import Singleton
+from pyAttributes import Attribute
+from pyAttributes.ArgParseAttributes import (
+    ArgParseMixin,
+    CommonSwitchArgumentAttribute,
+    DefaultAttribute,
+    CommandAttribute,
+    ArgumentAttribute,
+    SwitchArgumentAttribute,
+)
+from pyTerminalUI import LineTerminal, Severity
+
+from pyGHDL import GHDLBaseException
+from pyGHDL.dom.NonStandard import Design, Document
+from pyGHDL.dom.formatting.prettyprint import PrettyPrint, PrettyPrintException
+
+__author__ = "Tristan Gingold"
+__copyright__ = "Copyright (C) 2019-2021 Tristan Gingold"
+__maintainer__ = "Tristan Gingold"
+__email__ = ""
+__version__ = "0.0.0"
+__status__ = "Alpha"
+__license__ = ""
+__all__ = []
+__api__ = __all__
+
+
+class SourceAttribute(Attribute):
+    def __call__(self, func):
+        self._AppendAttribute(
+            func,
+            ArgumentAttribute(
+                "-f",
+                "--file",
+                action="append",
+                metavar="file",
+                dest="Files",
+                type=Path,
+                help="The filename to parse (can be used multiple times).",
+            ),
+        )
+        self._AppendAttribute(
+            func,
+            ArgumentAttribute(
+                "-F",
+                "--files",
+                metavar="files",
+                dest="Files",
+                type=Path,
+                nargs="+",
+                help="List of filenames to parse.",
+            ),
+        )
+        self._AppendAttribute(
+            func,
+            ArgumentAttribute(
+                "-D",
+                "--directory",
+                metavar="dir",
+                dest="Directory",
+                type=Path,
+                help="The directory to parse.",
+            ),
+        )
+        return func
+
+
+@export
+class Application(LineTerminal, ArgParseMixin):
+    HeadLine = "pyGHDL.dom - Test Application"
+
+    # load platform information (Windows, Linux, Darwin, ...)
+    __PLATFORM = platform_system()
+
+    _design: Design
+
+    def __init__(self, debug=False, verbose=False, quiet=False, sphinx=False):
+        super().__init__(verbose, debug, quiet)
+
+        # Initialize the Terminal class
+        # --------------------------------------------------------------------------
+        Singleton.Register(LineTerminal, self)
+
+        # Initialize DOM with an empty design
+        # --------------------------------------------------------------------------
+        self._design = Design()
+
+        # Call the constructor of the ArgParseMixin
+        # --------------------------------------------------------------------------
+        textWidth = min(max(self.Width, 80), 160)
+        description = dedent(
+            """\
+            Application to test pyGHDL's DOM API.
+            """
+        )
+        epilog = "\n".join(
+            wrap(
+                dedent(
+                    """\
+                    pyGHDL is a Python binding for libghdl.
+                    """
+                ),
+                textWidth,
+                replace_whitespace=False,
+            )
+        )
+
+        class HelpFormatter(RawDescriptionHelpFormatter):
+            def __init__(self, *args, **kwargs):
+                kwargs["max_help_position"] = 30
+                kwargs["width"] = textWidth
+                super().__init__(*args, **kwargs)
+
+        ArgParseMixin.__init__(
+            self,
+            description=description,
+            epilog=epilog,
+            formatter_class=HelpFormatter,
+            add_help=False,
+        )
+
+        # If executed in Sphinx to auto-document CLI arguments, exit now
+        # --------------------------------------------------------------------------
+        if sphinx:
+            return
+
+        # Change error and warning reporting
+        # --------------------------------------------------------------------------
+        self._LOG_MESSAGE_FORMAT__[
+            Severity.Fatal
+        ] = "{DARK_RED}[FATAL] {message}{NOCOLOR}"
+        self._LOG_MESSAGE_FORMAT__[Severity.Error] = "{RED}[ERROR] {message}{NOCOLOR}"
+        self._LOG_MESSAGE_FORMAT__[
+            Severity.Warning
+        ] = "{YELLOW}[WARNING] {message}{NOCOLOR}"
+        self._LOG_MESSAGE_FORMAT__[Severity.Normal] = "{GRAY}{message}{NOCOLOR}"
+
+    # class properties
+    # ============================================================================
+    @property
+    def Platform(self):
+        return self.__PLATFORM
+
+    def PrintHeadline(self):
+        self.WriteNormal(
+            dedent(
+                """\
+                {HEADLINE}{line}
+                {headline: ^80s}
+                {line}"""
+            ).format(line="=" * 80, headline=self.HeadLine, **LineTerminal.Foreground)
+        )
+
+    # ============================================================================
+    # Common commands
+    # ============================================================================
+    # common arguments valid for all commands
+    # ----------------------------------------------------------------------------
+    @CommonSwitchArgumentAttribute(
+        "-d", "--debug", dest="debug", help="Enable debug mode."
+    )
+    @CommonSwitchArgumentAttribute(
+        "-v", "--verbose", dest="verbose", help="Print out detailed messages."
+    )
+    @CommonSwitchArgumentAttribute(
+        "-q", "--quiet", dest="quiet", help="Reduce messages to a minimum."
+    )
+    def Run(self):
+        ArgParseMixin.Run(self)
+
+    @DefaultAttribute()
+    def HandleDefault(self, _):
+        self.PrintHeadline()
+        self.MainParser.print_help()
+
+        self.WriteNormal("")
+        self.exit()
+
+    # ----------------------------------------------------------------------------
+    # create the sub-parser for the "help" command
+    # ----------------------------------------------------------------------------
+    @CommandAttribute("help", help="Display help page(s) for the given command name.")
+    @ArgumentAttribute(
+        metavar="Command",
+        dest="Command",
+        type=str,
+        nargs="?",
+        help="Print help page(s) for a command.",
+    )
+    def HandleHelp(self, args):
+        self.PrintHeadline()
+
+        if args.Command is None:
+            self.MainParser.print_help()
+        elif args.Command == "help":
+            self.WriteError("This is a recursion ...")
+        else:
+            try:
+                self.SubParsers[args.Command].print_help()
+            except KeyError:
+                self.WriteError("Command {0} is unknown.".format(args.Command))
+
+        self.WriteNormal("")
+        self.exit()
+
+    # ----------------------------------------------------------------------------
+    # create the sub-parser for the "version" command
+    # ----------------------------------------------------------------------------
+    @CommandAttribute("version", help="Display tool and version information.")
+    def HandleInfo(self, args):
+        self.PrintHeadline()
+
+        copyrights = __copyright__.split("\n", 1)
+        self.WriteNormal("Copyright:  {0}".format(copyrights[0]))
+        for copyright in copyrights[1:]:
+            self.WriteNormal("            {0}".format(copyright))
+        self.WriteNormal("License:    {0}".format(__license__))
+        authors = __author__.split(", ")
+        self.WriteNormal("Authors:    {0}".format(authors[0]))
+        for author in authors[1:]:
+            self.WriteNormal("            {0}".format(author))
+        self.WriteNormal("Version:    {0}".format(__version__))
+        self.exit()
+
+    # ----------------------------------------------------------------------------
+    # Create the sub-parser for the "pretty" command
+    # ----------------------------------------------------------------------------
+    @CommandAttribute(
+        "pretty",
+        help="Pretty-print the DOM to console.",
+        description="Translate a source file into a DOM and pretty-print the DOM.",
+    )
+    @SourceAttribute()
+    def HandlePretty(self, args):
+        self.PrintHeadline()
+
+        if args.Files is not None:
+            for file in args.Files:
+                if not file.exists():
+                    self.WriteError("File '{0!s}' does not exist.".format(file))
+                    continue
+
+                self.WriteNormal("Parsing file '{!s}'".format(file))
+                document = self.addFile(file, "pretty")
+                self.WriteInfo(
+                    dedent(
+                        """\
+                          libghdl processing time: {: 5.3f} us
+                          DOM translation time:    {:5.3f} us
+                        """
+                    ).format(
+                        document.LibGHDLProcessingTime * 10 ** 6,
+                        document.DOMTranslationTime * 10 ** 6,
+                    )
+                )
+
+        PP = PrettyPrint()
+
+        buffer = []
+        buffer.append("Design:")
+        for line in PP.formatDesign(self._design, 1):
+            buffer.append(line)
+
+        print("\n".join(buffer))
+
+        self.exit()
+
+    def addFile(self, filename: Path, library: str) -> Document:
+        lib = self._design.GetLibrary(library)
+
+        document = Document(filename)
+        self._design.AddDocument(document, lib)
+        return document
+
+
+# main program
+def main():  # mccabe:disable=MC0001
+    """This is the entry point for pyghdl.cli.dom written as a function.
+
+    1. It extracts common flags from the script's arguments list, before :py:class:`~argparse.ArgumentParser` is fully loaded.
+    2. It creates an instance of DOM test application and hands over to a class based execution.
+       All is wrapped in a big ``try..except`` block to catch every unhandled exception.
+    3. Shutdown the script and return its exit code.
+    """
+    from sys import argv as sys_argv
+
+    debug = "-d" in sys_argv
+    verbose = "-v" in sys_argv
+    quiet = "-q" in sys_argv
+
+    try:
+        # handover to a class instance
+        app = Application(debug, verbose, quiet)
+        app.Run()
+        app.exit()
+    except PrettyPrintException as ex:
+        print("PP: {!s}".format(ex))
+        LineTerminal.exit()
+
+    except DOMException as ex:
+        print("DOM: {!s}".format(ex))
+        ex2: LibGHDLException = ex.__cause__
+        if ex2 is not None:
+            for message in ex2.InternalErrors:
+                print("libghdl: {message}".format(message=message))
+            LineTerminal.exit(0)
+
+        LineTerminal.exit(6)
+
+    except LibGHDLException as ex:
+        print("LIB: {!s}".format(ex))
+        for message in ex.InternalErrors:
+            print("  {message}".format(message=message))
+        LineTerminal.exit(5)
+
+    except GHDLBaseException as ex:
+        LineTerminal.printExceptionBase(ex)
+
+    except NotImplementedError as ex:
+        LineTerminal.printNotImplementedError(ex)
+
+    # except ImportError as ex:
+    #     printImportError(ex)
+    except Exception as ex:
+        LineTerminal.printException(ex)
+
+
+# entry point
+if __name__ == "__main__":
+    LineTerminal.versionCheck((3, 6, 0))
+    main()
diff --git a/pyGHDL/cli/requirements.txt b/pyGHDL/cli/requirements.txt
new file mode 100644
index 000000000..4ea0fb1fd
--- /dev/null
+++ b/pyGHDL/cli/requirements.txt
@@ -0,0 +1,5 @@
+-r ../dom/requirements.txt
+
+pyAttributes==2.1.0
+pyMetaClasses==1.2.1
+pyTerminalUI==1.3.4
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 32dc1cacf..87bc44360 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -48,12 +48,11 @@ from pyVHDLModel.VHDLModel import (
     NamedAggregateElement as VHDLModel_NamedAggregateElement,
     OthersAggregateElement as VHDLModel_OthersAggregateElement,
     Expression,
+    Symbol,
 )
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
-
 
 __all__ = []
 
@@ -61,48 +60,33 @@ __all__ = []
 @export
 class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
     def __init__(self, node: Iir, expression: Expression):
-        super().__init__()
+        super().__init__(expression)
         DOMMixin.__init__(self, node)
 
-        self._expression = expression
-
 
 @export
 class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
     def __init__(self, node: Iir, index: Expression, expression: Expression):
-        super().__init__()
+        super().__init__(index, expression)
         DOMMixin.__init__(self, node)
 
-        self._index = index
-        self._expression = expression
-
 
 @export
 class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, r: Range, expression: Expression):
-        super().__init__()
+    def __init__(self, node: Iir, rng: Range, expression: Expression):
+        super().__init__(rng, expression)
         DOMMixin.__init__(self, node)
 
-        self._range = r
-        self._expression = expression
-
 
 @export
 class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
-    def __init__(
-        self, node: Iir, name: EnumerationLiteralSymbol, expression: Expression
-    ):
-        super().__init__()
+    def __init__(self, node: Iir, name: Symbol, expression: Expression):
+        super().__init__(name, expression)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._expression = expression
-
 
 @export
 class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
     def __init__(self, node: Iir, expression: Expression):
-        super().__init__()
+        super().__init__(expression)
         DOMMixin.__init__(self, node)
-
-        self._expression = expression
diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py
index 8c7b08190..270f8feb3 100644
--- a/pyGHDL/dom/Attribute.py
+++ b/pyGHDL/dom/Attribute.py
@@ -30,42 +30,80 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from typing import List
+
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
     Attribute as VHDLModel_Attribute,
     AttributeSpecification as VHDLModel_AttributeSpecification,
     Name,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
+    EntityClass,
 )
+from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
-from pyGHDL.dom import DOMMixin
+from pyGHDL.libghdl.vhdl.tokens import Tok
+from pyGHDL.dom import DOMMixin, Position, DOMException, Expression
 from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode
-from pyGHDL.dom._Translate import GetNameFromNode
-from pyGHDL.dom.Symbol import SimpleSubTypeSymbol
+from pyGHDL.dom._Translate import GetNameFromNode, GetExpressionFromNode
+from pyGHDL.dom.Names import SimpleName
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 
 
 @export
 class Attribute(VHDLModel_Attribute, DOMMixin):
-    def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol):
-        super().__init__(name, subType)
+    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol):
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, attributeNode: Iir) -> "Attribute":
         name = GetNameOfNode(attributeNode)
-        subTypeMark = nodes.Get_Type_Mark(attributeNode)
-        subTypeName = GetNameOfNode(subTypeMark)
+        subtypeMark = nodes.Get_Type_Mark(attributeNode)
+        subtypeName = GetNameOfNode(subtypeMark)
+
+        subtype = SimpleSubtypeSymbol(subtypeMark, subtypeName)
+        return cls(attributeNode, name, subtype)
 
-        subType = SimpleSubTypeSymbol(subTypeMark, subTypeName)
-        return cls(attributeNode, name, subType)
+
+_TOKEN_TRANSLATION = {
+    Tok.Entity: EntityClass.Entity,
+    Tok.Architecture: EntityClass.Architecture,
+    Tok.Configuration: EntityClass.Configuration,
+    Tok.Procedure: EntityClass.Procedure,
+    Tok.Function: EntityClass.Function,
+    Tok.Package: EntityClass.Package,
+    Tok.Type: EntityClass.Type,
+    Tok.Subtype: EntityClass.Subtype,
+    Tok.Constant: EntityClass.Constant,
+    Tok.Signal: EntityClass.Signal,
+    Tok.Variable: EntityClass.Variable,
+    Tok.Component: EntityClass.Component,
+    Tok.Label: EntityClass.Label,
+    Tok.Literal: EntityClass.Literal,
+    Tok.Units: EntityClass.Units,
+    Tok.Group: EntityClass.Group,
+    Tok.File: EntityClass.File,
+    Tok.Property: EntityClass.Property,
+    Tok.Sequence: EntityClass.Sequence,
+    #    Tok.View: EntityClass.View,
+    Tok.Others: EntityClass.Others,
+}
 
 
 @export
 class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin):
-    def __init__(self, node: Iir, attribute: Name):
-        super().__init__(attribute)
+    def __init__(
+        self,
+        node: Iir,
+        identifiers: List[Name],
+        attribute: Name,
+        entityClass: EntityClass,
+        expression: Expression,
+    ):
+        super().__init__(identifiers, attribute, entityClass, expression)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -73,11 +111,41 @@ class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin):
         attributeDesignator = nodes.Get_Attribute_Designator(attributeNode)
         attributeName = GetNameFromNode(attributeDesignator)
 
-        # FIXME: needs an implementation
+        names = []
         entityNameList = nodes.Get_Entity_Name_List(attributeNode)
-        enlk = GetIirKindOfNode(entityNameList)
+        for name in utils.flist_iter(entityNameList):
+            nameKind = GetIirKindOfNode(name)
+            if nameKind == nodes.Iir_Kind.Simple_Name:
+                names.append(SimpleName(name, GetNameOfNode(name)))
+            elif nameKind == nodes.Iir_Kind.Signature:
+                print("[NOT IMPLEMENTED] Signature name in attribute specifications.")
+            else:
+                position = Position.parse(name)
+                raise DOMException(
+                    "Unknown name kind '{kind}' in attribute specification '{attr}' at {file}:{line}:{column}.".format(
+                        kind=nameKind.name,
+                        attr=attributeNode,
+                        file=position.Filename,
+                        line=position.Line,
+                        column=position.Column,
+                    )
+                )
+
+        entityClassToken = nodes.Get_Entity_Class(attributeNode)
+        try:
+            entityClass = _TOKEN_TRANSLATION[entityClassToken]
+        except KeyError:
+            position = Position.parse(attributeNode)
+            raise DOMException(
+                "Unknown token '{token}' in attribute specification for entity class '{entityClass}' at {file}:{line}:{column}.".format(
+                    token=entityClassToken.name,
+                    entityClass=attributeNode,
+                    file=position.Filename,
+                    line=position.Line,
+                    column=position.Column,
+                )
+            )
 
-        entityClass = nodes.Get_Entity_Class(attributeNode)
-        eck = GetIirKindOfNode(entityClass)
+        expression = GetExpressionFromNode(nodes.Get_Expression(attributeNode))
 
-        return cls(attributeNode, attributeName)
+        return cls(attributeNode, names, attributeName, entityClass, expression)
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index a8249d38d..d5bf161fd 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -41,8 +41,6 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from typing import List
 
-from pyGHDL.dom import DOMMixin
-from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
@@ -59,9 +57,12 @@ from pyVHDLModel.VHDLModel import (
     PortInterfaceItem,
     EntityOrSymbol,
     Name,
+    ConcurrentStatement,
 )
 
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
+from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode
 from pyGHDL.dom._Translate import (
     GetGenericsFromChainedNodes,
@@ -95,13 +96,13 @@ class Entity(VHDLModel_Entity, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         genericItems: List[GenericInterfaceItem] = None,
         portItems: List[PortInterfaceItem] = None,
         declaredItems: List = None,
         bodyItems: List["ConcurrentStatement"] = None,
     ):
-        super().__init__(name, genericItems, portItems, declaredItems, bodyItems)
+        super().__init__(identifier, genericItems, portItems, declaredItems, bodyItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -122,12 +123,12 @@ class Architecture(VHDLModel_Architecture, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         entity: EntityOrSymbol,
         declaredItems: List = None,
         bodyItems: List["ConcurrentStatement"] = None,
     ):
-        super().__init__(name, entity, declaredItems, bodyItems)
+        super().__init__(identifier, entity, declaredItems, bodyItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -152,11 +153,11 @@ class Component(VHDLModel_Component, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         genericItems: List[GenericInterfaceItem] = None,
         portItems: List[PortInterfaceItem] = None,
     ):
-        super().__init__(name, genericItems, portItems)
+        super().__init__(identifier, genericItems, portItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -173,11 +174,11 @@ class Package(VHDLModel_Package, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         genericItems: List[GenericInterfaceItem] = None,
         declaredItems: List = None,
     ):
-        super().__init__(name, genericItems, declaredItems)
+        super().__init__(identifier, genericItems, declaredItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -204,10 +205,10 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         declaredItems: List = None,
     ):
-        super().__init__(name, declaredItems)
+        super().__init__(identifier, declaredItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -225,11 +226,11 @@ class PackageInstantiation(VHDLModel_PackageInstantiation, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         uninstantiatedPackageName: Name,
         #        genericItems: List[GenericInterfaceItem] = None,
     ):
-        super().__init__(name, uninstantiatedPackageName)
+        super().__init__(identifier, uninstantiatedPackageName)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -248,9 +249,9 @@ class Context(VHDLModel_Context, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
     ):
-        super().__init__(name)
+        super().__init__(identifier)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -267,9 +268,9 @@ class Configuration(VHDLModel_Configuration, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
     ):
-        super().__init__(name)
+        super().__init__(identifier)
         DOMMixin.__init__(self, node)
 
     @classmethod
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index b3256d551..972b86ced 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -30,12 +30,14 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
-from typing import List
+from typing import List, Union
 
 from pydecor import export
 
 from pyGHDL.dom import DOMMixin, DOMException
 from pyVHDLModel.VHDLModel import (
+    UnaryExpression as VHDLModel_UnaryExpression,
+    BinaryExpression as VHDLModel_BinaryExpression,
     InverseExpression as VHDLModel_InverseExpression,
     IdentityExpression as VHDLModel_IdentityExpression,
     NegationExpression as VHDLModel_NegationExpression,
@@ -67,23 +69,32 @@ from pyVHDLModel.VHDLModel import (
     LessEqualExpression as VHDLModel_LessEqualExpression,
     GreaterThanExpression as VHDLModel_GreaterThanExpression,
     GreaterEqualExpression as VHDLModel_GreaterEqualExpression,
+    MatchingEqualExpression as VHDLModel_MatchingEqualExpression,
+    MatchingUnequalExpression as VHDLModel_MatchingUnequalExpression,
+    MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
+    MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
+    MatchingGreaterThanExpression as VHDLModel_MatchingGreaterThanExpression,
+    MatchingGreaterEqualExpression as VHDLModel_MatchingGreaterEqualExpression,
     ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression,
     ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression,
     ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression,
     ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression,
     RotateRightExpression as VHDLModel_RotateRightExpression,
     RotateLeftExpression as VHDLModel_RotateLeftExpression,
+    SubtypeAllocation as VHDLModel_SubtypeAllocation,
+    QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation,
     Aggregate as VHDLModel_Aggregate,
     Expression,
     AggregateElement,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
+    Symbol,
 )
 
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom._Utils import GetIirKindOfNode
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 from pyGHDL.dom.Aggregates import (
     OthersAggregateElement,
     SimpleAggregateElement,
@@ -96,18 +107,18 @@ from pyGHDL.dom.Aggregates import (
 __all__ = []
 
 
-class _ParseUnaryExpression:
+class _ParseUnaryExpressionMixin:
     @classmethod
-    def parse(cls, node: Iir):
+    def parse(cls, node: Iir) -> VHDLModel_UnaryExpression:
         from pyGHDL.dom._Translate import GetExpressionFromNode
 
         operand = GetExpressionFromNode(nodes.Get_Operand(node))
         return cls(node, operand)
 
 
-class _ParseBinaryExpression:
+class _ParseBinaryExpressionMixin:
     @classmethod
-    def parse(cls, node: Iir):
+    def parse(cls, node: Iir) -> VHDLModel_BinaryExpression:
         from pyGHDL.dom._Translate import GetExpressionFromNode
 
         left = GetExpressionFromNode(nodes.Get_Left(node))
@@ -116,53 +127,51 @@ class _ParseBinaryExpression:
 
 
 @export
-class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpression):
+class InverseExpression(
+    VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 @export
-class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpression):
+class IdentityExpression(
+    VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 @export
-class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpression):
+class NegationExpression(
+    VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 @export
-class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpression):
+class AbsoluteExpression(
+    VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 @export
 class ParenthesisExpression(
-    VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpression
+    VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
     @classmethod
-    def parse(cls, node: Iir):
+    def parse(cls, node: Iir) -> "ParenthesisExpression":
         from pyGHDL.dom._Translate import GetExpressionFromNode
 
         operand = GetExpressionFromNode(nodes.Get_Expression(node))
@@ -172,11 +181,9 @@ class ParenthesisExpression(
 @export
 class TypeConversion(VHDLModel_TypeConversion, DOMMixin):
     def __init__(self, node: Iir, operand: Expression):
-        super().__init__()
+        super().__init__(operand)
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 @export
 class FunctionCall(VHDLModel_FunctionCall, DOMMixin):
@@ -184,12 +191,12 @@ class FunctionCall(VHDLModel_FunctionCall, DOMMixin):
         super().__init__()
         DOMMixin.__init__(self, node)
 
-        self._operand = operand
-
 
 class RangeExpression(VHDLModel_RangeExpression, DOMMixin):
     @classmethod
-    def parse(cls, node: Iir) -> "VHDLModel_RangeExpression":
+    def parse(
+        cls, node: Iir
+    ) -> Union["AscendingRangeExpression", "DescendingRangeExpression"]:
         from pyGHDL.dom._Translate import GetExpressionFromNode
 
         direction = nodes.Get_Direction(node)
@@ -205,347 +212,350 @@ class RangeExpression(VHDLModel_RangeExpression, DOMMixin):
 @export
 class AscendingRangeExpression(VHDLModel_AscendingRangeExpression, DOMMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class AdditionExpression(
-    VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class SubtractionExpression(
-    VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class ConcatenationExpression(
-    VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class MultiplyExpression(
-    VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class DivisionExpression(
-    VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class RemainderExpression(
-    VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpression):
+class ModuloExpression(
+    VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class ExponentiationExpression(
-    VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpression):
+class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpression):
+class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpression):
+class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpression):
+class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpression):
+class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpression):
+class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
-class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpression):
+class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressionMixin):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class UnequalExpression(
+    VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
-class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpression):
+class LessThanExpression(
+    VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class LessEqualExpression(
+    VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
-class LessThanExpression(
-    VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpression
+class GreaterThanExpression(
+    VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class GreaterEqualExpression(
+    VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
-class LessEqualExpression(
-    VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpression
+class MatchingEqualExpression(
+    VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class MatchingUnequalExpression(
+    VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
-class GreaterThanExpression(
-    VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpression
+class MatchingLessThanExpression(
+    VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class MatchingLessEqualExpression(
+    VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
-class GreaterEqualExpression(
-    VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpression
+class MatchingGreaterThanExpression(
+    VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
+
+@export
+class MatchingGreaterEqualExpression(
+    VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+    def __init__(self, node: Iir, left: Expression, right: Expression):
+        super().__init__(left, right)
+        DOMMixin.__init__(self, node)
 
 
 @export
 class ShiftRightLogicExpression(
-    VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class ShiftLeftLogicExpression(
-    VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class ShiftRightArithmeticExpression(
-    VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class ShiftLeftArithmeticExpression(
-    VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class RotateRightExpression(
-    VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class RotateLeftExpression(
-    VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpression
+    VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
     def __init__(self, node: Iir, left: Expression, right: Expression):
-        super().__init__()
+        super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
-        self._leftOperand = left
-        self._rightOperand = right
-
 
 @export
 class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin):
-    def __init__(self, node: Iir, subType: SubTypeOrSymbol, operand: Expression):
-        super().__init__()
+    def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: Expression):
+        super().__init__(subtype, operand)
         DOMMixin.__init__(self, node)
 
-        self._subtype = subType
-        self._operand = operand
-
     @classmethod
-    def parse(cls, node: Iir):
+    def parse(cls, node: Iir) -> "QualifiedExpression":
         from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode
 
         typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node))
-        subType = SimpleSubTypeSymbol(typeMarkName)
+        subtype = SimpleSubtypeSymbol(node, typeMarkName)
         operand = GetExpressionFromNode(nodes.Get_Expression(node))
-        return cls(subType, operand)
+        return cls(node, subtype, operand)
+
+
+@export
+class SubtypeAllocation(VHDLModel_SubtypeAllocation, DOMMixin):
+    def __init__(self, node: Iir, subtype: Symbol):
+        super().__init__(subtype)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, node: Iir) -> "QualifiedExpressionAllocation":
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
+
+        subtype = GetSubtypeIndicationFromNode(node, "allocation", "?")
+
+        return cls(node, subtype)
+
+
+@export
+class QualifiedExpressionAllocation(VHDLModel_QualifiedExpressionAllocation, DOMMixin):
+    def __init__(self, node: Iir, qualifiedExpression: QualifiedExpression):
+        super().__init__(qualifiedExpression)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, node: Iir) -> "QualifiedExpressionAllocation":
+        from pyGHDL.dom._Translate import GetExpressionFromNode
+
+        expression = GetExpressionFromNode(nodes.Get_Expression(node))
+
+        return cls(node, expression)
 
 
 @export
 class Aggregate(VHDLModel_Aggregate, DOMMixin):
     def __init__(self, node: Iir, elements: List[AggregateElement]):
-        super().__init__()
+        super().__init__(elements)
         DOMMixin.__init__(self, node)
 
-        self._elements = elements
-
     @classmethod
-    def parse(cls, node: Iir):
-        from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode
+    def parse(cls, node: Iir) -> "Aggregate":
+        from pyGHDL.dom._Translate import (
+            GetExpressionFromNode,
+            GetRangeFromNode,
+            GetNameFromNode,
+        )
 
         choices = []
 
@@ -563,8 +573,9 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin):
                 r = GetRangeFromNode(nodes.Get_Choice_Range(item))
                 choices.append(RangedAggregateElement(item, r, value))
             elif kind == nodes.Iir_Kind.Choice_By_Name:
-                name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item))
-                choices.append(NamedAggregateElement(item, name, value))
+                name = GetNameFromNode(nodes.Get_Choice_Name(item))
+                symbol = Symbol(item, name)
+                choices.append(NamedAggregateElement(item, symbol, value))
             elif kind == nodes.Iir_Kind.Choice_By_Others:
                 choices.append(OthersAggregateElement(item, value))
             else:
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index df62c8256..4ebea735a 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -34,13 +34,17 @@ from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
     GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem,
+    GenericTypeInterfaceItem as VHDLModel_GenericTypeInterfaceItem,
+    GenericPackageInterfaceItem as VHDLModel_GenericPackageInterfaceItem,
+    GenericProcedureInterfaceItem as VHDLModel_GenericProcedureInterfaceItem,
+    GenericFunctionInterfaceItem as VHDLModel_GenericFunctionInterfaceItem,
     PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem,
     ParameterConstantInterfaceItem as VHDLModel_ParameterConstantInterfaceItem,
     ParameterVariableInterfaceItem as VHDLModel_ParameterVariableInterfaceItem,
     ParameterSignalInterfaceItem as VHDLModel_ParameterSignalInterfaceItem,
     ParameterFileInterfaceItem as VHDLModel_ParameterFileInterfaceItem,
     Mode,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
     Expression,
 )
 
@@ -48,7 +52,7 @@ from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode, GetModeOfNode
-from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode, GetExpressionFromNode
+from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode
 
 
 __all__ = []
@@ -59,51 +63,111 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         mode: Mode,
-        subType: SubTypeOrSymbol,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression,
     ):
-        super().__init__(name=name, mode=mode)
+        super().__init__(identifier, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, genericNode: Iir) -> "GenericConstantInterfaceItem":
         name = GetNameOfNode(genericNode)
         mode = GetModeOfNode(genericNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(genericNode, "generic", name)
         default = nodes.Get_Default_Value(genericNode)
         value = GetExpressionFromNode(default) if default else None
 
-        return cls(genericNode, name, mode, subTypeIndication, value)
+        return cls(genericNode, name, mode, subtypeIndication, value)
 
 
 @export
-class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin):
+class GenericTypeInterfaceItem(VHDLModel_GenericTypeInterfaceItem, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, genericNode: Iir) -> "GenericTypeInterfaceItem":
+        name = GetNameOfNode(genericNode)
+
+        return cls(genericNode, name)
+
+
+@export
+class GenericPackageInterfaceItem(VHDLModel_GenericPackageInterfaceItem, DOMMixin):
     def __init__(
         self,
         node: Iir,
         name: str,
+    ):
+        super().__init__(name)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, genericNode: Iir) -> "GenericPackageInterfaceItem":
+        name = GetNameOfNode(genericNode)
+
+        return cls(genericNode, name)
+
+
+@export
+class GenericProcedureInterfaceItem(VHDLModel_GenericProcedureInterfaceItem, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, genericNode: Iir) -> "GenericProcedureInterfaceItem":
+        name = GetNameOfNode(genericNode)
+
+        return cls(genericNode, name)
+
+
+@export
+class GenericFunctionInterfaceItem(VHDLModel_GenericFunctionInterfaceItem, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, genericNode: Iir) -> "GenericFunctionInterfaceItem":
+        name = GetNameOfNode(genericNode)
+
+        return cls(genericNode, name)
+
+
+@export
+class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
         mode: Mode,
-        subType: SubTypeOrSymbol,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression = None,
     ):
-        super().__init__(name=name, mode=mode)
+        super().__init__(identifier, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, portNode: Iir) -> "PortSignalInterfaceItem":
         name = GetNameOfNode(portNode)
         mode = GetModeOfNode(portNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(portNode, "port", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(portNode, "port", name)
 
         defaultValue = nodes.Get_Default_Value(portNode)
         value = (
@@ -112,7 +176,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin):
             else None
         )
 
-        return cls(portNode, name, mode, subTypeIndication, value)
+        return cls(portNode, name, mode, subtypeIndication, value)
 
 
 @export
@@ -122,23 +186,19 @@ class ParameterConstantInterfaceItem(
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         mode: Mode,
-        subType: SubTypeOrSymbol,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression = None,
     ):
-        super().__init__(name, mode)
+        super().__init__(identifier, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, parameterNode: Iir) -> "ParameterConstantInterfaceItem":
         name = GetNameOfNode(parameterNode)
         mode = GetModeOfNode(parameterNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(
+        subtypeIndication = GetSubtypeIndicationFromNode(
             parameterNode, "parameter", name
         )
 
@@ -149,7 +209,7 @@ class ParameterConstantInterfaceItem(
             else None
         )
 
-        return cls(parameterNode, name, mode, subTypeIndication, value)
+        return cls(parameterNode, name, mode, subtypeIndication, value)
 
 
 @export
@@ -159,23 +219,19 @@ class ParameterVariableInterfaceItem(
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         mode: Mode,
-        subType: SubTypeOrSymbol,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression = None,
     ):
-        super().__init__(name, mode)
+        super().__init__(identifier, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, parameterNode: Iir) -> "ParameterVariableInterfaceItem":
         name = GetNameOfNode(parameterNode)
         mode = GetModeOfNode(parameterNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(
+        subtypeIndication = GetSubtypeIndicationFromNode(
             parameterNode, "parameter", name
         )
 
@@ -186,7 +242,7 @@ class ParameterVariableInterfaceItem(
             else None
         )
 
-        return cls(parameterNode, name, mode, subTypeIndication, value)
+        return cls(parameterNode, name, mode, subtypeIndication, value)
 
 
 @export
@@ -194,23 +250,19 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi
     def __init__(
         self,
         node: Iir,
-        name: str,
+        identifier: str,
         mode: Mode,
-        subType: SubTypeOrSymbol,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression = None,
     ):
-        super().__init__(name, mode)
+        super().__init__(identifier, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, parameterNode: Iir) -> "ParameterSignalInterfaceItem":
         name = GetNameOfNode(parameterNode)
         mode = GetModeOfNode(parameterNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(
+        subtypeIndication = GetSubtypeIndicationFromNode(
             parameterNode, "parameter", name
         )
 
@@ -221,7 +273,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi
             else None
         )
 
-        return cls(parameterNode, name, mode, subTypeIndication, value)
+        return cls(parameterNode, name, mode, subtypeIndication, value)
 
 
 @export
@@ -229,22 +281,17 @@ class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin)
     def __init__(
         self,
         node: Iir,
-        name: str,
-        mode: Mode,
-        subType: SubTypeOrSymbol,
+        identifier: str,
+        subtype: SubtypeOrSymbol,
     ):
-        super().__init__(name, mode)
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
-        # TODO: move to model
-        self._subType = subType
-
     @classmethod
     def parse(cls, parameterNode: Iir) -> "ParameterFileInterfaceItem":
         name = GetNameOfNode(parameterNode)
-        mode = GetModeOfNode(parameterNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(
+        subtypeIndication = GetSubtypeIndicationFromNode(
             parameterNode, "parameter", name
         )
 
-        return cls(parameterNode, name, mode, subTypeIndication)
+        return cls(parameterNode, name, subtypeIndication)
diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py
index fa53acae6..e09294d40 100644
--- a/pyGHDL/dom/Names.py
+++ b/pyGHDL/dom/Names.py
@@ -52,8 +52,8 @@ __all__ = []
 
 @export
 class SimpleName(VHDLModel_SimpleName, DOMMixin):
-    def __init__(self, node: Iir, name: str):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str):
+        super().__init__(identifier)
         DOMMixin.__init__(self, node)
 
 
@@ -66,29 +66,29 @@ class ParenthesisName(VHDLModel_ParenthesisName, DOMMixin):
 
 @export
 class IndexedName(VHDLModel_IndexedName, DOMMixin):
-    def __init__(self, node: Iir, name: str):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str):
+        super().__init__(identifier)
         DOMMixin.__init__(self, node)
 
 
 @export
 class SlicedName(VHDLModel_SlicedName, DOMMixin):
-    def __init__(self, node: Iir, name: str):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str):
+        super().__init__(identifier)
         DOMMixin.__init__(self, node)
 
 
 @export
 class SelectedName(VHDLModel_SelectedName, DOMMixin):
-    def __init__(self, node: Iir, name: str, prefix: Name):
-        super().__init__(name, prefix)
+    def __init__(self, node: Iir, identifier: str, prefix: Name):
+        super().__init__(identifier, prefix)
         DOMMixin.__init__(self, node)
 
 
 @export
 class AttributeName(VHDLModel_AttributeName, DOMMixin):
-    def __init__(self, node: Iir, name: str, prefix: Name):
-        super().__init__(name, prefix)
+    def __init__(self, node: Iir, identifier: str, prefix: Name):
+        super().__init__(identifier, prefix)
         DOMMixin.__init__(self, node)
 
 
diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py
index 1524b549f..bf48db900 100644
--- a/pyGHDL/dom/NonStandard.py
+++ b/pyGHDL/dom/NonStandard.py
@@ -42,6 +42,7 @@ from typing import Any
 
 from pydecor import export
 
+from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
 from pyVHDLModel.VHDLModel import (
     Design as VHDLModel_Design,
     Library as VHDLModel_Library,
@@ -198,6 +199,18 @@ class Document(VHDLModel_Document):
                 configuration = Configuration.parse(libraryUnit)
                 self.Configurations.append(configuration)
 
+            elif nodeKind == nodes.Iir_Kind.Vunit_Declaration:
+                vunit = VerificationUnit.parse(libraryUnit)
+                self.VerificationUnits.append(vunit)
+
+            elif nodeKind == nodes.Iir_Kind.Vprop_Declaration:
+                vprop = VerificationProperty.parse(libraryUnit)
+                self.VerificationProperties.append(vprop)
+
+            elif nodeKind == nodes.Iir_Kind.Vmode_Declaration:
+                vmod = VerificationMode.parse(libraryUnit)
+                self.VerificationModes.append(vmod)
+
             else:
                 raise DOMException(
                     "Unknown design unit kind '{kindName}'({kind}).".format(
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index 3085f9f81..d25acb587 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -43,7 +43,7 @@ from pyVHDLModel.VHDLModel import (
     Signal as VHDLModel_Signal,
     File as VHDLModel_File,
     Expression,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
 )
 
 from pyGHDL.libghdl.vhdl import nodes
@@ -58,54 +58,47 @@ class Constant(VHDLModel_Constant, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
-        subType: SubTypeOrSymbol,
+        identifier: str,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression,
     ):
-        super().__init__(name)
+        super().__init__(identifier, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, constantNode: Iir) -> Union["Constant", "DeferredConstant"]:
         from pyGHDL.dom._Translate import (
-            GetSubTypeIndicationFromNode,
+            GetSubtypeIndicationFromNode,
             GetExpressionFromNode,
         )
 
         name = GetNameOfNode(constantNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(constantNode, "constant", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(constantNode, "constant", name)
         defaultValue = nodes.Get_Default_Value(constantNode)
         if defaultValue != nodes.Null_Iir:
             defaultExpression = GetExpressionFromNode(defaultValue)
 
-            return cls(constantNode, name, subTypeIndication, defaultExpression)
+            return cls(constantNode, name, subtypeIndication, defaultExpression)
         else:
-            return DeferredConstant(constantNode, name, subTypeIndication)
+            return DeferredConstant(constantNode, name, subtypeIndication)
 
 
 @export
 class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin):
-    def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol):
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-
     @classmethod
     def parse(cls, constantNode: Iir) -> "DeferredConstant":
-        from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
 
         name = GetNameOfNode(constantNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(
+        subtypeIndication = GetSubtypeIndicationFromNode(
             constantNode, "deferred constant", name
         )
 
-        return cls(constantNode, name, subTypeIndication)
+        return cls(constantNode, name, subtypeIndication)
 
 
 @export
@@ -113,51 +106,44 @@ class Variable(VHDLModel_Variable, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
-        subType: SubTypeOrSymbol,
+        identifier: str,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression,
     ):
-        super().__init__(name)
+        super().__init__(identifier, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, variableNode: Iir) -> "Variable":
         from pyGHDL.dom._Translate import (
-            GetSubTypeIndicationFromNode,
+            GetSubtypeIndicationFromNode,
             GetExpressionFromNode,
         )
 
         name = GetNameOfNode(variableNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(variableNode, "variable", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(variableNode, "variable", name)
         defaultValue = nodes.Get_Default_Value(variableNode)
         defaultExpression = None
         if defaultValue != nodes.Null_Iir:
             defaultExpression = GetExpressionFromNode(defaultValue)
 
-        return cls(variableNode, name, subTypeIndication, defaultExpression)
+        return cls(variableNode, name, subtypeIndication, defaultExpression)
 
 
 @export
 class SharedVariable(VHDLModel_SharedVariable, DOMMixin):
-    def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol):
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-
     @classmethod
     def parse(cls, variableNode: Iir) -> "SharedVariable":
-        from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
 
         name = GetNameOfNode(variableNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(variableNode, "variable", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(variableNode, "variable", name)
 
-        return cls(variableNode, name, subTypeIndication)
+        return cls(variableNode, name, subtypeIndication)
 
 
 @export
@@ -165,48 +151,41 @@ class Signal(VHDLModel_Signal, DOMMixin):
     def __init__(
         self,
         node: Iir,
-        name: str,
-        subType: SubTypeOrSymbol,
+        identifier: str,
+        subtype: SubtypeOrSymbol,
         defaultExpression: Expression,
     ):
-        super().__init__(name)
+        super().__init__(identifier, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-        self._defaultExpression = defaultExpression
-
     @classmethod
     def parse(cls, signalNode: Iir) -> "Signal":
         from pyGHDL.dom._Translate import (
-            GetSubTypeIndicationFromNode,
+            GetSubtypeIndicationFromNode,
             GetExpressionFromNode,
         )
 
         name = GetNameOfNode(signalNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(signalNode, "signal", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(signalNode, "signal", name)
         default = nodes.Get_Default_Value(signalNode)
         defaultExpression = GetExpressionFromNode(default) if default else None
 
-        return cls(signalNode, name, subTypeIndication, defaultExpression)
+        return cls(signalNode, name, subtypeIndication, defaultExpression)
 
 
 @export
 class File(VHDLModel_File, DOMMixin):
-    def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol):
-        super().__init__(name)
+    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol):
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._subType = subType
-
     @classmethod
     def parse(cls, fileNode: Iir) -> "File":
-        from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
 
         name = GetNameOfNode(fileNode)
-        subTypeIndication = GetSubTypeIndicationFromNode(fileNode, "file", name)
+        subtypeIndication = GetSubtypeIndicationFromNode(fileNode, "file", name)
 
         # FIXME: handle file open stuff
 
-        return cls(fileNode, name, subTypeIndication)
+        return cls(fileNode, name, subtypeIndication)
diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
new file mode 100644
index 000000000..6c4ba76b3
--- /dev/null
+++ b/pyGHDL/dom/PSL.py
@@ -0,0 +1,133 @@
+# =============================================================================
+#               ____ _   _ ____  _          _
+#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
+# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
+# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
+# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
+# |_|    |___/
+# =============================================================================
+# Authors:
+#   Patrick Lehmann
+#
+# Package module:   DOM: VHDL design units (e.g. context or package).
+#
+# License:
+# ============================================================================
+#  Copyright (C) 2019-2021 Tristan Gingold
+#
+#  This program is free software: you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation, either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program.  If not, see <gnu.org/licenses>.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ============================================================================
+
+"""
+This module contains all DOM classes for VHDL's design units (:class:`context <Entity>`,
+:class:`architecture <Architecture>`, :class:`package <Package>`,
+:class:`package body <PackageBody>`, :class:`context <Context>` and
+:class:`configuration <Configuration>`.
+
+
+"""
+from pyGHDL.libghdl.vhdl import nodes
+from pydecor import export
+
+from pyVHDLModel.PSLModel import (
+    VerificationUnit as VHDLModel_VerificationUnit,
+    VerificationProperty as VHDLModel_VerificationProperty,
+    VerificationMode as VHDLModel_VerificationMode,
+    DefaultClock as VHDLModel_DefaultClock,
+)
+
+from pyGHDL.libghdl._types import Iir
+from pyGHDL.dom import DOMMixin
+from pyGHDL.dom._Utils import GetNameOfNode
+
+
+__all__ = []
+
+
+@export
+class VerificationUnit(VHDLModel_VerificationUnit, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vunitNode: Iir):
+        name = GetNameOfNode(vunitNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vunitNode, name)
+
+
+@export
+class VerificationProperty(VHDLModel_VerificationProperty, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vpropNode: Iir):
+        name = GetNameOfNode(vpropNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vpropNode, name)
+
+
+@export
+class VerificationMode(VHDLModel_VerificationMode, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vmodeNode: Iir):
+        name = GetNameOfNode(vmodeNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vmodeNode, name)
+
+
+@export
+class DefaultClock(VHDLModel_DefaultClock, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, defaultClockNode: Iir):
+        name = GetNameOfNode(defaultClockNode)
+
+        # FIXME: needs an implementation
+
+        return cls(defaultClockNode, name)
diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py
index d091be1c6..ce8dfbc40 100644
--- a/pyGHDL/dom/Range.py
+++ b/pyGHDL/dom/Range.py
@@ -44,9 +44,4 @@ __all__ = []
 
 @export
 class Range(VHDLModel_Range):
-    def __init__(self, left: Expression, right: Expression, direction: Direction):
-        super().__init__()
-
-        self._leftBound = left
-        self._rightBound = right
-        self._direction = direction
+    pass
diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py
index 42e3c7d79..e8e5ebbb4 100644
--- a/pyGHDL/dom/Subprogram.py
+++ b/pyGHDL/dom/Subprogram.py
@@ -37,7 +37,7 @@ from pydecor import export
 from pyVHDLModel.VHDLModel import (
     Function as VHDLModel_Function,
     Procedure as VHDLModel_Procedure,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
     GenericInterfaceItem,
     ParameterInterfaceItem,
 )
@@ -45,7 +45,7 @@ from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode
-from pyGHDL.dom.Symbol import SimpleSubTypeSymbol
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 
 
 @export
@@ -54,7 +54,7 @@ class Function(VHDLModel_Function, DOMMixin):
         self,
         node: Iir,
         functionName: str,
-        returnType: SubTypeOrSymbol,
+        returnType: SubtypeOrSymbol,
         genericItems: List[GenericInterfaceItem] = None,
         parameterItems: List[ParameterInterfaceItem] = None,
     ):
@@ -84,7 +84,7 @@ class Function(VHDLModel_Function, DOMMixin):
 
         returnType = nodes.Get_Return_Type_Mark(functionNode)
         returnTypeName = GetNameOfNode(returnType)
-        returnTypeSymbol = SimpleSubTypeSymbol(returnType, returnTypeName)
+        returnTypeSymbol = SimpleSubtypeSymbol(returnType, returnTypeName)
 
         return cls(functionNode, functionName, returnTypeSymbol, generics, parameters)
 
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index 85d1c637b..3597f2572 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -36,10 +36,9 @@ from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
     EntitySymbol as VHDLModel_EntitySymbol,
-    SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol,
-    ConstrainedScalarSubTypeSymbol as VHDLModel_ConstrainedScalarSubTypeSymbol,
-    ConstrainedCompositeSubTypeSymbol as VHDLModel_ConstrainedCompositeSubTypeSymbol,
-    EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol,
+    SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol,
+    ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol,
+    ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol,
     SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol,
     IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol,
     Constraint,
@@ -47,7 +46,6 @@ from pyVHDLModel.VHDLModel import (
 )
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
-from pyGHDL.dom._Utils import GetNameOfNode
 from pyGHDL.dom.Range import Range
 
 
@@ -56,34 +54,27 @@ __all__ = []
 
 @export
 class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin):
-    def __init__(self, node: Iir, entityName: str):
+    def __init__(self, node: Iir, entityName: Name):
         super().__init__(entityName)
         DOMMixin.__init__(self, node)
 
 
 @export
-class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol, DOMMixin):
-    def __init__(self, node: Iir, literalName: str):
-        super().__init__(symbolName=literalName)
-        DOMMixin.__init__(self, node)
-
-
-@export
-class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin):
-    def __init__(self, node: Iir, subTypeName: Name):
-        if isinstance(subTypeName, (List, Iterator)):
-            subTypeName = ".".join(subTypeName)
+class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin):
+    def __init__(self, node: Iir, subtypeName: Name):
+        if isinstance(subtypeName, (List, Iterator)):
+            subtypeName = ".".join(subtypeName)
 
-        super().__init__(subTypeName=subTypeName)
+        super().__init__(subtypeName=subtypeName)
         DOMMixin.__init__(self, node)
 
 
 @export
-class ConstrainedScalarSubTypeSymbol(
-    VHDLModel_ConstrainedScalarSubTypeSymbol, DOMMixin
+class ConstrainedScalarSubtypeSymbol(
+    VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin
 ):
-    def __init__(self, node: Iir, subTypeName: str, range: Range = None):
-        super().__init__(subTypeName=subTypeName, range=range)
+    def __init__(self, node: Iir, subtypeName: Name, rng: Range = None):
+        super().__init__(subtypeName, rng)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -92,13 +83,13 @@ class ConstrainedScalarSubTypeSymbol(
 
 
 @export
-class ConstrainedCompositeSubTypeSymbol(
-    VHDLModel_ConstrainedCompositeSubTypeSymbol, DOMMixin
+class ConstrainedCompositeSubtypeSymbol(
+    VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin
 ):
     def __init__(
-        self, node: Iir, subTypeName: str, constraints: List[Constraint] = None
+        self, node: Iir, subtypeName: Name, constraints: List[Constraint] = None
     ):
-        super().__init__(subTypeName=subTypeName, constraints=constraints)
+        super().__init__(subtypeName, constraints)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -112,7 +103,9 @@ class SimpleObjectOrFunctionCallSymbol(
 ):
     @classmethod
     def parse(cls, node: Iir):
-        name = GetNameOfNode(node)
+        from pyGHDL.dom._Translate import GetNameFromNode
+
+        name = GetNameFromNode(node)
         return cls(name)
 
 
@@ -120,13 +113,13 @@ class SimpleObjectOrFunctionCallSymbol(
 class IndexedObjectOrFunctionCallSymbol(
     VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin
 ):
-    def __init__(self, node: Iir, name: str):
-        super().__init__(objectName=name)
+    def __init__(self, node: Iir, name: Name):
+        super().__init__(name)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, node: Iir):
-        from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameFromNode
+        from pyGHDL.dom._Translate import GetNameFromNode
 
         name = GetNameFromNode(node)
 
diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py
index db51f1c49..efe32afc2 100644
--- a/pyGHDL/dom/Type.py
+++ b/pyGHDL/dom/Type.py
@@ -35,6 +35,7 @@ from typing import List, Union, Iterator, Tuple
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
+    AnonymousType as VHDLModel_AnonymousType,
     PhysicalType as VHDLModel_PhysicalType,
     IntegerType as VHDLModel_IntegerType,
     EnumeratedType as VHDLModel_EnumeratedType,
@@ -45,24 +46,38 @@ from pyVHDLModel.VHDLModel import (
     FileType as VHDLModel_FileType,
     ProtectedType as VHDLModel_ProtectedType,
     ProtectedTypeBody as VHDLModel_ProtectedTypeBody,
-    SubType as VHDLModel_SubType,
-    SubTypeOrSymbol,
+    Subtype as VHDLModel_Subtype,
+    SubtypeOrSymbol,
+    Name,
 )
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin, DOMException
 from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode
-from pyGHDL.dom.Symbol import SimpleSubTypeSymbol
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 from pyGHDL.dom.Literal import EnumerationLiteral, PhysicalIntegerLiteral
 from pyGHDL.dom.Range import Range
 from pyGHDL.dom.Subprogram import Function, Procedure
 
 
 @export
+class IncompleteType(VHDLModel_AnonymousType, DOMMixin):
+    def __init__(self, node: Iir, identifier: str):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, node: Iir) -> "IncompleteType":
+        name = GetNameOfNode(node)
+
+        return cls(node, name)
+
+
+@export
 class EnumeratedType(VHDLModel_EnumeratedType, DOMMixin):
-    def __init__(self, node: Iir, name: str, literals: List[EnumerationLiteral]):
-        super().__init__(name, literals)
+    def __init__(self, node: Iir, identifier: str, literals: List[EnumerationLiteral]):
+        super().__init__(identifier, literals)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -78,13 +93,10 @@ class EnumeratedType(VHDLModel_EnumeratedType, DOMMixin):
 
 @export
 class IntegerType(VHDLModel_IntegerType, DOMMixin):
-    def __init__(self, node: Iir, typeName: str, range: Range):
-        super().__init__(typeName)
+    def __init__(self, node: Iir, typeName: str, rng: Union[Range, "Name"]):
+        super().__init__(typeName, rng)
         DOMMixin.__init__(self, node)
 
-        self._leftBound = range.LeftBound
-        self._rightBound = range.RightBound
-
 
 @export
 class PhysicalType(VHDLModel_PhysicalType, DOMMixin):
@@ -92,14 +104,19 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin):
         self,
         node: Iir,
         typeName: str,
+        rng: Union[Range, Name],
         primaryUnit: str,
         units: List[Tuple[str, PhysicalIntegerLiteral]],
     ):
-        super().__init__(typeName, primaryUnit, units)
+        super().__init__(typeName, rng, primaryUnit, units)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "PhysicalType":
+        from pyGHDL.dom._Translate import GetRangeFromNode
+
+        rng = GetRangeFromNode(nodes.Get_Range_Constraint(typeDefinitionNode))
+
         primaryUnit = nodes.Get_Primary_Unit(typeDefinitionNode)
         primaryUnitName = GetNameOfNode(primaryUnit)
 
@@ -115,22 +132,22 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin):
 
             units.append((secondaryUnitName, physicalLiteral))
 
-        return cls(typeDefinitionNode, typeName, primaryUnitName, units)
+        return cls(typeDefinitionNode, typeName, rng, primaryUnitName, units)
 
 
 @export
 class ArrayType(VHDLModel_ArrayType, DOMMixin):
     def __init__(
-        self, node: Iir, name: str, indices: List, elementSubType: SubTypeOrSymbol
+        self, node: Iir, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol
     ):
-        super().__init__(name, indices, elementSubType)
+        super().__init__(identifier, indices, elementSubtype)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "ArrayType":
         from pyGHDL.dom._Translate import (
             GetSimpleTypeFromNode,
-            GetSubTypeIndicationFromIndicationNode,
+            GetSubtypeIndicationFromIndicationNode,
         )
 
         indices = []
@@ -138,8 +155,8 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin):
         for index in utils.flist_iter(indexDefinitions):
             indexKind = GetIirKindOfNode(index)
             if indexKind == nodes.Iir_Kind.Simple_Name:
-                indexSubType = GetSimpleTypeFromNode(index)
-                indices.append(indexSubType)
+                indexSubtype = GetSimpleTypeFromNode(index)
+                indices.append(indexSubtype)
             else:
                 raise DOMException(
                     "Unknown kind '{kind}' for an index in the array definition of `{typeName}`.".format(
@@ -147,28 +164,28 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin):
                     )
                 )
 
-        elementSubTypeIndication = nodes.Get_Element_Subtype_Indication(
+        elementSubtypeIndication = nodes.Get_Element_Subtype_Indication(
             typeDefinitionNode
         )
-        elementSubType = GetSubTypeIndicationFromIndicationNode(
-            elementSubTypeIndication, "array declaration", typeName
+        elementSubtype = GetSubtypeIndicationFromIndicationNode(
+            elementSubtypeIndication, "array declaration", typeName
         )
 
-        return cls(typeDefinitionNode, typeName, indices, elementSubType)
+        return cls(typeDefinitionNode, typeName, indices, elementSubtype)
 
 
 @export
 class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin):
-    def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol):
-        super().__init__(name, subType)
+    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol):
+        super().__init__(identifier, subtype)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, elementDeclarationNode: Iir) -> "RecordTypeElement":
-        from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
 
         elementName = GetNameOfNode(elementDeclarationNode)
-        elementType = GetSubTypeIndicationFromNode(
+        elementType = GetSubtypeIndicationFromNode(
             elementDeclarationNode, "record element", elementName
         )
 
@@ -177,8 +194,10 @@ class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin):
 
 @export
 class RecordType(VHDLModel_RecordType, DOMMixin):
-    def __init__(self, node: Iir, name: str, elements: List[RecordTypeElement] = None):
-        super().__init__(name, elements)
+    def __init__(
+        self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None
+    ):
+        super().__init__(identifier, elements)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -194,8 +213,10 @@ class RecordType(VHDLModel_RecordType, DOMMixin):
 
 @export
 class ProtectedType(VHDLModel_ProtectedType, DOMMixin):
-    def __init__(self, node: Iir, name: str, methods: Union[List, Iterator] = None):
-        super().__init__(name, methods)
+    def __init__(
+        self, node: Iir, identifier: str, methods: Union[List, Iterator] = None
+    ):
+        super().__init__(identifier, methods)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -215,9 +236,9 @@ class ProtectedType(VHDLModel_ProtectedType, DOMMixin):
 @export
 class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin):
     def __init__(
-        self, node: Iir, name: str, declaredItems: Union[List, Iterator] = None
+        self, node: Iir, identifier: str, declaredItems: Union[List, Iterator] = None
     ):
-        super().__init__(name, declaredItems)
+        super().__init__(identifier, declaredItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -236,44 +257,44 @@ class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin):
 
 @export
 class AccessType(VHDLModel_AccessType, DOMMixin):
-    def __init__(self, node: Iir, name: str, designatedSubType: SubTypeOrSymbol):
-        super().__init__(name, designatedSubType)
+    def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol):
+        super().__init__(identifier, designatedSubtype)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "AccessType":
-        from pyGHDL.dom._Translate import GetSubTypeIndicationFromIndicationNode
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromIndicationNode
 
         designatedSubtypeIndication = nodes.Get_Designated_Subtype_Indication(
             typeDefinitionNode
         )
-        designatedSubType = GetSubTypeIndicationFromIndicationNode(
+        designatedSubtype = GetSubtypeIndicationFromIndicationNode(
             designatedSubtypeIndication, "access type", typeName
         )
 
-        return cls(typeDefinitionNode, typeName, designatedSubType)
+        return cls(typeDefinitionNode, typeName, designatedSubtype)
 
 
 @export
 class FileType(VHDLModel_FileType, DOMMixin):
-    def __init__(self, node: Iir, name: str, designatedSubType: SubTypeOrSymbol):
-        super().__init__(name, designatedSubType)
+    def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol):
+        super().__init__(identifier, designatedSubtype)
         DOMMixin.__init__(self, node)
 
     @classmethod
     def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "FileType":
 
-        designatedSubTypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode)
-        designatedSubTypeName = GetNameOfNode(designatedSubTypeMark)
-        designatedSubType = SimpleSubTypeSymbol(
-            typeDefinitionNode, designatedSubTypeName
+        designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode)
+        designatedSubtypeName = GetNameOfNode(designatedSubtypeMark)
+        designatedSubtype = SimpleSubtypeSymbol(
+            typeDefinitionNode, designatedSubtypeName
         )
 
-        return cls(typeDefinitionNode, typeName, designatedSubType)
+        return cls(typeDefinitionNode, typeName, designatedSubtype)
 
 
 @export
-class SubType(VHDLModel_SubType, DOMMixin):
+class Subtype(VHDLModel_Subtype, DOMMixin):
     def __init__(self, node: Iir, subtypeName: str):
         super().__init__(subtypeName)
         DOMMixin.__init__(self, node)
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 502a94ad3..a9ead8c2c 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -36,11 +36,12 @@ from pydecor import export
 
 from pyGHDL.dom import Position, DOMException
 from pyGHDL.dom.Object import Variable
+from pyGHDL.dom.PSL import DefaultClock
 from pyVHDLModel.VHDLModel import (
     Constraint,
     Direction,
     Expression,
-    SubTypeOrSymbol,
+    SubtypeOrSymbol,
     BaseType,
     GenericInterfaceItem,
     PortInterfaceItem,
@@ -65,14 +66,14 @@ from pyGHDL.dom.Names import (
 )
 from pyGHDL.dom.Symbol import (
     SimpleObjectOrFunctionCallSymbol,
-    SimpleSubTypeSymbol,
-    ConstrainedCompositeSubTypeSymbol,
+    SimpleSubtypeSymbol,
+    ConstrainedCompositeSubtypeSymbol,
     IndexedObjectOrFunctionCallSymbol,
-    ConstrainedScalarSubTypeSymbol,
+    ConstrainedScalarSubtypeSymbol,
 )
 from pyGHDL.dom.Type import (
     IntegerType,
-    SubType,
+    Subtype,
     ArrayType,
     RecordType,
     EnumeratedType,
@@ -81,6 +82,7 @@ from pyGHDL.dom.Type import (
     ProtectedTypeBody,
     FileType,
     PhysicalType,
+    IncompleteType,
 )
 from pyGHDL.dom.Range import Range
 from pyGHDL.dom.Literal import (
@@ -125,6 +127,16 @@ from pyGHDL.dom.Expression import (
     RotateLeftExpression,
     RotateRightExpression,
     RangeExpression,
+    QualifiedExpressionAllocation,
+    SubtypeAllocation,
+    IdentityExpression,
+    AbsoluteExpression,
+    MatchingGreaterEqualExpression,
+    MatchingEqualExpression,
+    MatchingUnequalExpression,
+    MatchingLessThanExpression,
+    MatchingLessEqualExpression,
+    MatchingGreaterThanExpression,
 )
 from pyGHDL.dom.Subprogram import Function, Procedure
 from pyGHDL.dom.Misc import Alias
@@ -181,11 +193,11 @@ def GetAssociations(node: Iir) -> List:
 
 @export
 def GetArrayConstraintsFromSubtypeIndication(
-    subTypeIndication: Iir,
+    subtypeIndication: Iir,
 ) -> List[Constraint]:
     constraints = []
     for constraint in utils.flist_iter(
-        nodes.Get_Index_Constraint_List(subTypeIndication)
+        nodes.Get_Index_Constraint_List(subtypeIndication)
     ):
         constraintKind = GetIirKindOfNode(constraint)
         if constraintKind == nodes.Iir_Kind.Range_Expression:
@@ -203,7 +215,7 @@ def GetArrayConstraintsFromSubtypeIndication(
                 "Unknown constraint kind '{kind}' for constraint '{constraint}' in subtype indication '{indication}' at {file}:{line}:{column}.".format(
                     kind=constraintKind.name,
                     constraint=constraint,
-                    indication=subTypeIndication,
+                    indication=subtypeIndication,
                     file=position.Filename,
                     line=position.Line,
                     column=position.Column,
@@ -217,22 +229,14 @@ def GetArrayConstraintsFromSubtypeIndication(
 def GetTypeFromNode(node: Iir) -> BaseType:
     typeName = GetNameOfNode(node)
     typeDefinition = nodes.Get_Type_Definition(node)
+    if typeDefinition is nodes.Null_Iir:
+        return IncompleteType(node, typeName)
 
     kind = GetIirKindOfNode(typeDefinition)
-    if kind == nodes.Iir_Kind.Range_Expression:
-        r = GetRangeFromNode(typeDefinition)
-
-        return IntegerType(node, typeName, r)
-    elif kind == nodes.Iir_Kind.Physical_Type_Definition:
-        return PhysicalType.parse(typeName, typeDefinition)
-    elif kind == nodes.Iir_Kind.Enumeration_Type_Definition:
+    if kind == nodes.Iir_Kind.Enumeration_Type_Definition:
         return EnumeratedType.parse(typeName, typeDefinition)
     elif kind == nodes.Iir_Kind.Array_Type_Definition:
         return ArrayType.parse(typeName, typeDefinition)
-    elif kind == nodes.Iir_Kind.Array_Subtype_Definition:
-        print("[NOT IMPLEMENTED] Array_Subtype_Definition")
-
-        return ArrayType(typeDefinition, "????", [], None)
     elif kind == nodes.Iir_Kind.Record_Type_Definition:
         return RecordType.parse(typeName, typeDefinition)
     elif kind == nodes.Iir_Kind.Access_Type_Definition:
@@ -244,9 +248,45 @@ def GetTypeFromNode(node: Iir) -> BaseType:
     else:
         position = Position.parse(typeDefinition)
         raise DOMException(
-            "Unknown type definition kind '{kindName}'({kind}) for type '{name}' at {file}:{line}:{column}.".format(
-                kind=kind,
-                kindName=kind.name,
+            "GetTypeFromNode: Unknown type definition kind '{kind}' for type '{name}' at {file}:{line}:{column}.".format(
+                kind=kind.name,
+                name=typeName,
+                file=position.Filename,
+                line=position.Line,
+                column=position.Column,
+            )
+        )
+
+
+@export
+def GetAnonymousTypeFromNode(node: Iir) -> BaseType:
+    typeName = GetNameOfNode(node)
+    typeDefinition = nodes.Get_Type_Definition(node)
+    if typeDefinition is nodes.Null_Iir:
+        print(1, node, typeName)
+        return IncompleteType(node, typeName)
+
+    kind = GetIirKindOfNode(typeDefinition)
+    if kind == nodes.Iir_Kind.Range_Expression:
+        r = GetRangeFromNode(typeDefinition)
+        return IntegerType(node, typeName, r)
+
+    elif kind in (nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name):
+        n = GetNameFromNode(typeDefinition)
+
+        return IntegerType(node, typeName, n)
+    elif kind == nodes.Iir_Kind.Physical_Type_Definition:
+        return PhysicalType.parse(typeName, typeDefinition)
+
+    elif kind == nodes.Iir_Kind.Array_Subtype_Definition:
+        print("[NOT IMPLEMENTED] Array_Subtype_Definition")
+
+        return ArrayType(typeDefinition, "????", [], None)
+    else:
+        position = Position.parse(typeDefinition)
+        raise DOMException(
+            "GetAnonymousTypeFromNode: Unknown type definition kind '{kind}' for type '{name}' at {file}:{line}:{column}.".format(
+                kind=kind.name,
                 name=typeName,
                 file=position.Filename,
                 line=position.Line,
@@ -256,35 +296,35 @@ def GetTypeFromNode(node: Iir) -> BaseType:
 
 
 @export
-def GetSubTypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubTypeOrSymbol:
-    subTypeIndicationNode = nodes.Get_Subtype_Indication(node)
-    #     if subTypeIndicationNode is nodes.Null_Iir:
+def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubtypeOrSymbol:
+    subtypeIndicationNode = nodes.Get_Subtype_Indication(node)
+    #     if subtypeIndicationNode is nodes.Null_Iir:
     #         return None
-    return GetSubTypeIndicationFromIndicationNode(subTypeIndicationNode, entity, name)
+    return GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode, entity, name)
 
 
 @export
-def GetSubTypeIndicationFromIndicationNode(
-    subTypeIndicationNode: Iir, entity: str, name: str
-) -> SubTypeOrSymbol:
-    if subTypeIndicationNode is nodes.Null_Iir:
+def GetSubtypeIndicationFromIndicationNode(
+    subtypeIndicationNode: Iir, entity: str, name: str
+) -> SubtypeOrSymbol:
+    if subtypeIndicationNode is nodes.Null_Iir:
         print(
             "[NOT IMPLEMENTED]: Unhandled multiple declarations for {entity} '{name}'.".format(
                 entity=entity, name=name
             )
         )
         return None
-    kind = GetIirKindOfNode(subTypeIndicationNode)
+    kind = GetIirKindOfNode(subtypeIndicationNode)
     if kind in (
         nodes.Iir_Kind.Simple_Name,
         nodes.Iir_Kind.Selected_Name,
         nodes.Iir_Kind.Attribute_Name,
     ):
-        return GetSimpleTypeFromNode(subTypeIndicationNode)
+        return GetSimpleTypeFromNode(subtypeIndicationNode)
     elif kind == nodes.Iir_Kind.Subtype_Definition:
-        return GetScalarConstrainedSubTypeFromNode(subTypeIndicationNode)
+        return GetScalarConstrainedSubtypeFromNode(subtypeIndicationNode)
     elif kind == nodes.Iir_Kind.Array_Subtype_Definition:
-        return GetCompositeConstrainedSubTypeFromNode(subTypeIndicationNode)
+        return GetCompositeConstrainedSubtypeFromNode(subtypeIndicationNode)
     else:
         raise DOMException(
             "Unknown kind '{kind}' for an subtype indication in a {entity} of `{name}`.".format(
@@ -294,40 +334,40 @@ def GetSubTypeIndicationFromIndicationNode(
 
 
 @export
-def GetSimpleTypeFromNode(subTypeIndicationNode: Iir) -> SimpleSubTypeSymbol:
-    subTypeName = GetNameFromNode(subTypeIndicationNode)
-    return SimpleSubTypeSymbol(subTypeIndicationNode, subTypeName)
+def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol:
+    subtypeName = GetNameFromNode(subtypeIndicationNode)
+    return SimpleSubtypeSymbol(subtypeIndicationNode, subtypeName)
 
 
 @export
-def GetScalarConstrainedSubTypeFromNode(
-    subTypeIndicationNode: Iir,
-) -> ConstrainedScalarSubTypeSymbol:
-    typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndicationNode)
+def GetScalarConstrainedSubtypeFromNode(
+    subtypeIndicationNode: Iir,
+) -> ConstrainedScalarSubtypeSymbol:
+    typeMark = nodes.Get_Subtype_Type_Mark(subtypeIndicationNode)
     typeMarkName = GetNameOfNode(typeMark)
-    rangeConstraint = nodes.Get_Range_Constraint(subTypeIndicationNode)
+    rangeConstraint = nodes.Get_Range_Constraint(subtypeIndicationNode)
     r = GetRangeFromNode(rangeConstraint)
-    return ConstrainedScalarSubTypeSymbol(subTypeIndicationNode, typeMarkName, r)
+    return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, typeMarkName, r)
 
 
 @export
-def GetCompositeConstrainedSubTypeFromNode(
-    subTypeIndicationNode: Iir,
-) -> ConstrainedCompositeSubTypeSymbol:
-    typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndicationNode)
+def GetCompositeConstrainedSubtypeFromNode(
+    subtypeIndicationNode: Iir,
+) -> ConstrainedCompositeSubtypeSymbol:
+    typeMark = nodes.Get_Subtype_Type_Mark(subtypeIndicationNode)
     typeMarkName = GetNameOfNode(typeMark)
 
-    constraints = GetArrayConstraintsFromSubtypeIndication(subTypeIndicationNode)
-    return ConstrainedCompositeSubTypeSymbol(
-        subTypeIndicationNode, typeMarkName, constraints
+    constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode)
+    return ConstrainedCompositeSubtypeSymbol(
+        subtypeIndicationNode, typeMarkName, constraints
     )
 
 
 @export
-def GetSubTypeFromNode(subTypeNode: Iir) -> SubTypeOrSymbol:
-    subTypeName = GetNameOfNode(subTypeNode)
+def GetSubtypeFromNode(subtypeNode: Iir) -> SubtypeOrSymbol:
+    subtypeName = GetNameOfNode(subtypeNode)
 
-    return SubType(subTypeNode, subTypeName)
+    return Subtype(subtypeNode, subtypeName)
 
 
 @export
@@ -355,7 +395,9 @@ __EXPRESSION_TRANSLATION = {
     nodes.Iir_Kind.Physical_Fp_Literal: PhysicalFloatingLiteral,
     nodes.Iir_Kind.Character_Literal: CharacterLiteral,
     nodes.Iir_Kind.String_Literal8: StringLiteral,
+    nodes.Iir_Kind.Identity_Operator: IdentityExpression,
     nodes.Iir_Kind.Negation_Operator: NegationExpression,
+    nodes.Iir_Kind.Absolute_Operator: AbsoluteExpression,
     nodes.Iir_Kind.Range_Expression: RangeExpression,
     nodes.Iir_Kind.Addition_Operator: AdditionExpression,
     nodes.Iir_Kind.Concatenation_Operator: ConcatenationExpression,
@@ -378,7 +420,13 @@ __EXPRESSION_TRANSLATION = {
     nodes.Iir_Kind.Less_Than_Operator: LessThanExpression,
     nodes.Iir_Kind.Less_Than_Or_Equal_Operator: LessEqualExpression,
     nodes.Iir_Kind.Greater_Than_Operator: GreaterThanExpression,
-    nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: GreaterEqualExpression,
+    nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: MatchingGreaterEqualExpression,
+    nodes.Iir_Kind.Match_Equality_Operator: MatchingEqualExpression,
+    nodes.Iir_Kind.Match_Inequality_Operator: MatchingUnequalExpression,
+    nodes.Iir_Kind.Match_Less_Than_Operator: MatchingLessThanExpression,
+    nodes.Iir_Kind.Match_Less_Than_Or_Equal_Operator: MatchingLessEqualExpression,
+    nodes.Iir_Kind.Match_Greater_Than_Operator: MatchingGreaterThanExpression,
+    nodes.Iir_Kind.Match_Greater_Than_Or_Equal_Operator: MatchingGreaterEqualExpression,
     nodes.Iir_Kind.Sll_Operator: ShiftLeftLogicExpression,
     nodes.Iir_Kind.Srl_Operator: ShiftRightLogicExpression,
     nodes.Iir_Kind.Sla_Operator: ShiftLeftArithmeticExpression,
@@ -387,6 +435,8 @@ __EXPRESSION_TRANSLATION = {
     nodes.Iir_Kind.Ror_Operator: RotateRightExpression,
     nodes.Iir_Kind.Qualified_Expression: QualifiedExpression,
     nodes.Iir_Kind.Aggregate: Aggregate,
+    nodes.Iir_Kind.Allocator_By_Subtype: SubtypeAllocation,
+    nodes.Iir_Kind.Allocator_By_Expression: QualifiedExpressionAllocation,
 }
 
 
@@ -399,9 +449,8 @@ def GetExpressionFromNode(node: Iir) -> Expression:
     except KeyError:
         position = Position.parse(node)
         raise DOMException(
-            "Unknown expression kind '{kindName}'({kind}) in expression '{expr}' at {file}:{line}:{column}.".format(
-                kind=kind,
-                kindName=kind.name,
+            "Unknown expression kind '{kind}' in expression '{expr}' at {file}:{line}:{column}.".format(
+                kind=kind.name,
                 expr=node,
                 file=position.Filename,
                 line=position.Line,
@@ -416,6 +465,13 @@ def GetExpressionFromNode(node: Iir) -> Expression:
 def GetGenericsFromChainedNodes(
     nodeChain: Iir,
 ) -> Generator[GenericInterfaceItem, None, None]:
+    from pyGHDL.dom.InterfaceItem import (
+        GenericTypeInterfaceItem,
+        GenericPackageInterfaceItem,
+        GenericProcedureInterfaceItem,
+        GenericFunctionInterfaceItem,
+    )
+
     for generic in utils.chain_iter(nodeChain):
         kind = GetIirKindOfNode(generic)
         if kind == nodes.Iir_Kind.Interface_Constant_Declaration:
@@ -423,13 +479,13 @@ def GetGenericsFromChainedNodes(
 
             yield GenericConstantInterfaceItem.parse(generic)
         elif kind == nodes.Iir_Kind.Interface_Type_Declaration:
-            print("[NOT IMPLEMENTED] generic type")
+            yield GenericTypeInterfaceItem.parse(generic)
         elif kind == nodes.Iir_Kind.Interface_Package_Declaration:
-            print("[NOT IMPLEMENTED] generic package")
+            yield GenericPackageInterfaceItem.parse(generic)
         elif kind == nodes.Iir_Kind.Interface_Procedure_Declaration:
-            print("[NOT IMPLEMENTED] generic procedure")
+            yield GenericProcedureInterfaceItem.parse(generic)
         elif kind == nodes.Iir_Kind.Interface_Function_Declaration:
-            print("[NOT IMPLEMENTED] generic function")
+            yield GenericFunctionInterfaceItem.parse(generic)
         else:
             position = Position.parse(generic)
             raise DOMException(
@@ -534,12 +590,16 @@ def GetDeclaredItemsFromChainedNodes(
             yield File.parse(item)
         elif kind == nodes.Iir_Kind.Type_Declaration:
             yield GetTypeFromNode(item)
+
         elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration:
-            yield GetTypeFromNode(item)
+            yield GetAnonymousTypeFromNode(item)
+
         elif kind == nodes.Iir_Kind.Subtype_Declaration:
-            yield GetSubTypeFromNode(item)
+            yield GetSubtypeFromNode(item)
+
         elif kind == nodes.Iir_Kind.Function_Declaration:
             yield Function.parse(item)
+
         elif kind == nodes.Iir_Kind.Function_Body:
             #                procedureName = NodeToName(item)
             print("found function body '{name}'".format(name="????"))
@@ -568,6 +628,10 @@ def GetDeclaredItemsFromChainedNodes(
             from pyGHDL.dom.DesignUnit import UseClause
 
             yield UseClause.parse(item)
+        elif kind == nodes.Iir_Kind.Package_Declaration:
+            from pyGHDL.dom.DesignUnit import Package
+
+            yield Package.parse(item)
         elif kind == nodes.Iir_Kind.Package_Instantiation_Declaration:
             from pyGHDL.dom.DesignUnit import PackageInstantiation
 
@@ -578,6 +642,20 @@ def GetDeclaredItemsFromChainedNodes(
                     name=name
                 )
             )
+        elif kind == nodes.Iir_Kind.Psl_Default_Clock:
+            yield DefaultClock.parse(item)
+        elif kind == nodes.Iir_Kind.Group_Declaration:
+            print("[NOT IMPLEMENTED] Group declaration in {name}".format(name=name))
+        elif kind == nodes.Iir_Kind.Group_Template_Declaration:
+            print(
+                "[NOT IMPLEMENTED] Group template declaration in {name}".format(
+                    name=name
+                )
+            )
+        elif kind == nodes.Iir_Kind.Disconnection_Specification:
+            print(
+                "[NOT IMPLEMENTED] Disconnect specification in {name}".format(name=name)
+            )
         else:
             position = Position.parse(item)
             raise DOMException(
diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py
index 19f23a94b..20c90a1d1 100644
--- a/pyGHDL/dom/__init__.py
+++ b/pyGHDL/dom/__init__.py
@@ -32,13 +32,12 @@
 # ============================================================================
 from pathlib import Path
 
-from pyGHDL import GHDLBaseException
-from pyGHDL.libghdl import files_map, name_table
-
-from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
+from pyGHDL import GHDLBaseException
+from pyGHDL.libghdl import files_map, name_table
 from pyGHDL.libghdl._types import Iir
+from pyGHDL.libghdl.vhdl import nodes
 
 __all__ = []
 
@@ -85,6 +84,11 @@ class Position:
     def Column(self) -> int:
         return self._column
 
+    def __str__(self):
+        return "{file}:{line}:{column}".format(
+            file=self._filename, line=self._line, column=self._column
+        )
+
 
 @export
 class DOMMixin:
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index f055f3f51..4d6e5dccb 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -4,10 +4,11 @@ from pydecor import export
 
 from pyGHDL.dom.Attribute import Attribute, AttributeSpecification
 from pyGHDL.dom.Misc import Alias
+from pyGHDL.dom.PSL import DefaultClock
 from pyGHDL.dom.Subprogram import Procedure
 from pyGHDL.dom.Type import (
     IntegerType,
-    SubType,
+    Subtype,
     ArrayType,
     RecordType,
     AccessType,
@@ -16,15 +17,16 @@ from pyGHDL.dom.Type import (
     ProtectedType,
     ProtectedTypeBody,
     PhysicalType,
+    IncompleteType,
 )
 from pyVHDLModel.VHDLModel import (
     GenericInterfaceItem,
     NamedEntity,
     PortInterfaceItem,
-    WithDefaultExpression,
+    WithDefaultExpressionMixin,
     Function,
     BaseType,
-    Type,
+    FullType,
 )
 
 from pyGHDL import GHDLBaseException
@@ -44,10 +46,11 @@ from pyGHDL.dom.Object import Constant, Signal, SharedVariable, File
 from pyGHDL.dom.InterfaceItem import (
     GenericConstantInterfaceItem,
     PortSignalInterfaceItem,
+    GenericTypeInterfaceItem,
 )
 from pyGHDL.dom.Symbol import (
-    SimpleSubTypeSymbol,
-    ConstrainedCompositeSubTypeSymbol,
+    SimpleSubtypeSymbol,
+    ConstrainedCompositeSubtypeSymbol,
 )
 
 
@@ -96,7 +99,12 @@ class PrettyPrint:
         #         buffer.append(line)
         buffer.append("{prefix}Packages:".format(prefix=prefix))
         for package in library.Packages:
-            for line in self.formatPackage(package, level + 1):
+            if isinstance(package, Package):
+                gen = self.formatPackage
+            else:
+                gen = self.formatPackageInstance
+
+            for line in gen(package, level + 1):
                 buffer.append(line)
         # buffer.append("{prefix}PackageBodies:".format(prefix=prefix))
         # for packageBodies in library.PackageBodies:
@@ -126,7 +134,12 @@ class PrettyPrint:
                 buffer.append(line)
         buffer.append("{prefix}Packages:".format(prefix=prefix))
         for package in document.Packages:
-            for line in self.formatPackage(package, level + 1):
+            if isinstance(package, Package):
+                gen = self.formatPackage
+            else:
+                gen = self.formatPackageInstance
+
+            for line in gen(package, level + 1):
                 buffer.append(line)
         buffer.append("{prefix}PackageBodies:".format(prefix=prefix))
         for packageBodies in document.PackageBodies:
@@ -148,7 +161,7 @@ class PrettyPrint:
         prefix = "  " * level
         buffer.append(
             "{prefix}- Name: {name} at {file}:{line}:{column}".format(
-                name=entity.Name,
+                name=entity.Identifier,
                 prefix=prefix,
                 file=entity.Position.Filename.name,
                 line=entity.Position.Line,
@@ -177,7 +190,7 @@ class PrettyPrint:
         prefix = "  " * level
         buffer.append(
             "{prefix}- Name: {name} at {file}:{line}:{column}".format(
-                name=architecture.Name,
+                name=architecture.Identifier,
                 prefix=prefix,
                 file=architecture.Position.Filename.name,
                 line=architecture.Position.Line,
@@ -200,7 +213,9 @@ class PrettyPrint:
         buffer = []
         prefix = "  " * level
         buffer.append(
-            "{prefix}- Component: {name}".format(name=component.Name, prefix=prefix)
+            "{prefix}- Component: {name}".format(
+                name=component.Identifier, prefix=prefix
+            )
         )
         buffer.append("{prefix}  Generics:".format(prefix=prefix))
         for generic in component.GenericItems:
@@ -216,7 +231,9 @@ class PrettyPrint:
     def formatPackage(self, package: Package, level: int = 0) -> StringBuffer:
         buffer = []
         prefix = "  " * level
-        buffer.append("{prefix}- Name: {name}".format(name=package.Name, prefix=prefix))
+        buffer.append(
+            "{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)
+        )
         buffer.append("{prefix}  Declared:".format(prefix=prefix))
         for item in package.DeclaredItems:
             for line in self.formatDeclaredItems(item, level + 1):
@@ -224,13 +241,33 @@ class PrettyPrint:
 
         return buffer
 
+    def formatPackageInstance(
+        self, package: PackageInstantiation, level: int = 0
+    ) -> StringBuffer:
+        buffer = []
+        prefix = "  " * level
+        buffer.append(
+            "{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)
+        )
+        buffer.append(
+            "{prefix}  Package: {name!s}".format(
+                prefix=prefix, name=package.PackageReference
+            )
+        )
+        buffer.append("{prefix}  Generic Map: ...".format(prefix=prefix))
+        #        for item in package.GenericItems:
+        #            for line in self.formatGeneric(item, level + 1):
+        #                buffer.append(line)
+
+        return buffer
+
     def formatPackageBody(
         self, packageBody: PackageBody, level: int = 0
     ) -> StringBuffer:
         buffer = []
         prefix = "  " * level
         buffer.append(
-            "{prefix}- Name: {name}".format(name=packageBody.Name, prefix=prefix)
+            "{prefix}- Name: {name}".format(name=packageBody.Identifier, prefix=prefix)
         )
         buffer.append("{prefix}  Declared:".format(prefix=prefix))
         for item in packageBody.DeclaredItems:
@@ -245,7 +282,9 @@ class PrettyPrint:
         buffer = []
         prefix = "  " * level
         buffer.append(
-            "{prefix}- Name: {name}".format(name=configuration.Name, prefix=prefix)
+            "{prefix}- Name: {name}".format(
+                name=configuration.Identifier, prefix=prefix
+            )
         )
 
         return buffer
@@ -253,7 +292,9 @@ class PrettyPrint:
     def formatContext(self, context: Context, level: int = 0) -> StringBuffer:
         buffer = []
         prefix = "  " * level
-        buffer.append("{prefix}- Name: {name}".format(name=context.Name, prefix=prefix))
+        buffer.append(
+            "{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix)
+        )
 
         return buffer
 
@@ -262,9 +303,13 @@ class PrettyPrint:
     ) -> StringBuffer:
         if isinstance(generic, GenericConstantInterfaceItem):
             return self.formatGenericConstant(generic, level)
+        elif isinstance(generic, GenericTypeInterfaceItem):
+            return self.formatGenericType(generic, level)
         else:
             raise PrettyPrintException(
-                "Unhandled generic kind for generic '{name}'.".format(name=generic.Name)
+                "Unhandled generic kind for generic '{name}'.".format(
+                    name=generic.Identifier
+                )
             )
 
     def formatPort(
@@ -274,7 +319,7 @@ class PrettyPrint:
             return self.formatPortSignal(port, level)
         else:
             raise PrettyPrintException(
-                "Unhandled port kind for port '{name}'.".format(name=port.Name)
+                "Unhandled port kind for port '{name}'.".format(name=port.Identifier)
             )
 
     def formatGenericConstant(
@@ -286,10 +331,10 @@ class PrettyPrint:
         buffer.append(
             "{prefix}  - {name} : {mode!s} {subtypeindication}{initialValue}".format(
                 prefix=prefix,
-                name=generic.Name,
+                name=generic.Identifier,
                 mode=generic.Mode,
                 subtypeindication=self.formatSubtypeIndication(
-                    generic.SubType, "generic", generic.Name
+                    generic.Subtype, "generic", generic.Identifier
                 ),
                 initialValue=self.formatInitialValue(generic),
             )
@@ -297,6 +342,21 @@ class PrettyPrint:
 
         return buffer
 
+    def formatGenericType(
+        self, generic: GenericConstantInterfaceItem, level: int = 0
+    ) -> StringBuffer:
+        buffer = []
+        prefix = "  " * level
+
+        buffer.append(
+            "{prefix}  - type {name}".format(
+                prefix=prefix,
+                name=generic.Identifier,
+            )
+        )
+
+        return buffer
+
     def formatPortSignal(
         self, port: PortSignalInterfaceItem, level: int = 0
     ) -> StringBuffer:
@@ -306,10 +366,10 @@ class PrettyPrint:
         buffer.append(
             "{prefix}  - {name} : {mode!s} {subtypeindication}{initialValue}".format(
                 prefix=prefix,
-                name=port.Name,
+                name=port.Identifier,
                 mode=port.Mode,
                 subtypeindication=self.formatSubtypeIndication(
-                    port.SubType, "port", port.Name
+                    port.Subtype, "port", port.Identifier
                 ),
                 initialValue=self.formatInitialValue(port),
             )
@@ -325,9 +385,9 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- constant {name} : {subtype} := {expr}".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                     subtype=self.formatSubtypeIndication(
-                        item.SubType, "constant", item.Name
+                        item.Subtype, "constant", item.Identifier
                     ),
                     expr=str(item.DefaultExpression),
                 )
@@ -336,9 +396,9 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- shared variable {name} : {subtype}".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                     subtype=self.formatSubtypeIndication(
-                        item.SubType, "shared variable", item.Name
+                        item.Subtype, "shared variable", item.Identifier
                     ),
                 )
             )
@@ -346,9 +406,9 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- signal {name} : {subtype}{initValue}".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                     subtype=self.formatSubtypeIndication(
-                        item.SubType, "signal", item.Name
+                        item.Subtype, "signal", item.Identifier
                     ),
                     initValue=" := {expr}".format(expr=str(item.DefaultExpression))
                     if item.DefaultExpression is not None
@@ -359,41 +419,41 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- File {name} : {subtype}".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                     subtype=self.formatSubtypeIndication(
-                        item.SubType, "file", item.Name
+                        item.Subtype, "file", item.Identifier
                     ),
                 )
             )
-        elif isinstance(item, Type):
+        elif isinstance(item, (FullType, IncompleteType)):
             buffer.append(
                 "{prefix}- {type}".format(prefix=prefix, type=self.formatType(item))
             )
-        elif isinstance(item, SubType):
+        elif isinstance(item, Subtype):
             buffer.append(
                 "{prefix}- subtype {name} is ?????".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                 )
             )
         elif isinstance(item, Alias):
             buffer.append(
                 "{prefix}- alias {name} is ?????".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                 )
             )
         elif isinstance(item, Function):
             buffer.append(
                 "{prefix}- function {name} return {returnType!s}".format(
-                    prefix=prefix, name=item.Name, returnType=item.ReturnType
+                    prefix=prefix, name=item.Identifier, returnType=item.ReturnType
                 )
             )
         elif isinstance(item, Procedure):
             buffer.append(
                 "{prefix}- procedure {name}".format(
                     prefix=prefix,
-                    name=item.Name,
+                    name=item.Identifier,
                 )
             )
         elif isinstance(item, Component):
@@ -402,7 +462,7 @@ class PrettyPrint:
         elif isinstance(item, Attribute):
             buffer.append(
                 "{prefix}- attribute {name} : {type!s}".format(
-                    prefix=prefix, name=item.Name, type=item.SubType
+                    prefix=prefix, name=item.Identifier, type=item.Subtype
                 )
             )
         elif isinstance(item, AttributeSpecification):
@@ -419,10 +479,22 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- use {name!s}".format(prefix=prefix, name=item.Item)
             )
+        elif isinstance(item, Package):
+            buffer.append(
+                "{prefix}- package {name} is ..... end package".format(
+                    prefix=prefix, name=item.Identifier
+                )
+            )
         elif isinstance(item, PackageInstantiation):
             buffer.append(
                 "{prefix}- package {name} is new {name2!s} generic map (.....)".format(
-                    prefix=prefix, name=item.Name, name2=item.PackageReference
+                    prefix=prefix, name=item.Identifier, name2=item.PackageReference
+                )
+            )
+        elif isinstance(item, DefaultClock):
+            buffer.append(
+                "{prefix}- default {name} is {expr}".format(
+                    prefix=prefix, name=item.Identifier, expr="..."
                 )
             )
         else:
@@ -435,11 +507,11 @@ class PrettyPrint:
         return buffer
 
     def formatType(self, item: BaseType) -> str:
-        result = "type {name} is ".format(name=item.Name)
-        if isinstance(item, IntegerType):
-            result += "range {left!s} to {right!s}".format(
-                left=item.LeftBound, right=item.RightBound
-            )
+        result = "type {name} is ".format(name=item.Identifier)
+        if isinstance(item, IncompleteType):
+            result += ""
+        elif isinstance(item, IntegerType):
+            result += "range {range!s}".format(range=item.Range)
         elif isinstance(item, EnumeratedType):
             result += "(........)"
         elif isinstance(item, PhysicalType):
@@ -463,25 +535,25 @@ class PrettyPrint:
 
         return result
 
-    def formatSubtypeIndication(self, subTypeIndication, entity: str, name: str) -> str:
-        if isinstance(subTypeIndication, SimpleSubTypeSymbol):
-            return "{type}".format(type=subTypeIndication.SymbolName)
-        elif isinstance(subTypeIndication, ConstrainedCompositeSubTypeSymbol):
+    def formatSubtypeIndication(self, subtypeIndication, entity: str, name: str) -> str:
+        if isinstance(subtypeIndication, SimpleSubtypeSymbol):
+            return "{type}".format(type=subtypeIndication.SymbolName)
+        elif isinstance(subtypeIndication, ConstrainedCompositeSubtypeSymbol):
             constraints = []
-            for constraint in subTypeIndication.Constraints:
+            for constraint in subtypeIndication.Constraints:
                 constraints.append(str(constraint))
 
             return "{type}({constraints})".format(
-                type=subTypeIndication.SymbolName, constraints=", ".join(constraints)
+                type=subtypeIndication.SymbolName, constraints=", ".join(constraints)
             )
         else:
             raise PrettyPrintException(
                 "Unhandled subtype kind '{type}' for {entity} '{name}'.".format(
-                    type=subTypeIndication.__class__.__name__, entity=entity, name=name
+                    type=subtypeIndication.__class__.__name__, entity=entity, name=name
                 )
             )
 
-    def formatInitialValue(self, item: WithDefaultExpression) -> str:
+    def formatInitialValue(self, item: WithDefaultExpressionMixin) -> str:
         if item.DefaultExpression is None:
             return ""
 
diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt
new file mode 100644
index 000000000..66e3025ae
--- /dev/null
+++ b/pyGHDL/dom/requirements.txt
@@ -0,0 +1,4 @@
+-r ../libghdl/requirements.txt
+
+pyVHDLModel==0.11.1
+#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel
diff --git a/pyGHDL/libghdl/__init__.py b/pyGHDL/libghdl/__init__.py
index 39722f3b9..8c9d132e9 100644
--- a/pyGHDL/libghdl/__init__.py
+++ b/pyGHDL/libghdl/__init__.py
@@ -36,7 +36,7 @@ from sys import platform as sys_platform, version_info as sys_version_info
 from os import environ as os_environ
 from pathlib import Path
 from shutil import which
-from typing import List
+from typing import List, Optional
 
 from pydecor import export
 
@@ -46,16 +46,18 @@ from pyGHDL.libghdl._types import Iir
 # from pyGHDL.libghdl._decorator import BindToLibGHDL
 from pyGHDL.libghdl.version import __version__
 
+Nullable = Optional
+
 
 class LibGHDLException(GHDLBaseException):
-    _internalErrors: List[str]
+    _internalErrors: Nullable[List[str]]
 
-    def __init__(self, message: str, errors: List[str]):
+    def __init__(self, message: str, errors: List[str] = None):
         super().__init__(message)
         self._internalErrors = errors
 
     @property
-    def InternalErrors(self):
+    def InternalErrors(self) -> Nullable[List[str]]:
         return self._internalErrors
 
 
diff --git a/pyGHDL/libghdl/errorout_memory.py b/pyGHDL/libghdl/errorout_memory.py
index c6577540d..3f85a03c9 100644
--- a/pyGHDL/libghdl/errorout_memory.py
+++ b/pyGHDL/libghdl/errorout_memory.py
@@ -94,6 +94,7 @@ def Get_Nbr_Messages() -> ErrorIndex:
 
     :return: Number of messages available.
     """
+    return 0
 
 
 @export
@@ -110,7 +111,7 @@ def Get_Error_Record(Idx: ErrorIndex) -> Error_Message:
 # @export
 @BindToLibGHDL("errorout__memory__get_error_message_addr")
 def _Get_Error_Message(Idx: ErrorIndex) -> c_char_p:
-    pass
+    return ""
 
 
 @export
diff --git a/pyGHDL/libghdl/files_map.py b/pyGHDL/libghdl/files_map.py
index 1726225bc..d57de13cc 100644
--- a/pyGHDL/libghdl/files_map.py
+++ b/pyGHDL/libghdl/files_map.py
@@ -59,6 +59,7 @@ def Location_To_File(Location: LocationType) -> SourceFileEntry:
     :param Location: Location
     :return:         Source file. Return ``No_Source_File_Entry`` if location is incorrect.
     """
+    return 0
 
 
 @export
@@ -71,6 +72,7 @@ def Location_File_To_Pos(Location: LocationType, File: SourceFileEntry) -> int:
     :param File:     Source file
     :return:         Offset
     """
+    return 0
 
 
 @export
@@ -83,6 +85,7 @@ def Location_File_To_Line(Location: LocationType, File: SourceFileEntry) -> int:
     :param File:     Source file
     :return:         Line number
     """
+    return 0
 
 
 @export
@@ -98,6 +101,7 @@ def Location_File_Line_To_Offset(
     :param Line:     Line number
     :return:         Offset
     """
+    return 0
 
 
 @export
@@ -114,6 +118,7 @@ def Location_File_Line_To_Col(
     :param Line:     Line number
     :return:         logical column (horizontal tabs are expanded)
     """
+    return 0
 
 
 @export
@@ -124,6 +129,7 @@ def File_To_Location(File: SourceFileEntry) -> LocationType:
     :param File: Source file
     :return:     Location.
     """
+    return 0
 
 
 @export
@@ -136,6 +142,7 @@ def File_Pos_To_Location(File: SourceFileEntry, Pos: int) -> LocationType:
     :param Pos:  Offset in the file
     :return:     Location.
     """
+    return 0
 
 
 @export
@@ -148,6 +155,7 @@ def File_Line_To_Position(File: SourceFileEntry, Line: int) -> int:
     :param Line: Line number
     :return:     Return ``Source_Ptr_Bad`` in case of error (:obj:`Line` out of bounds).
     """
+    return 0
 
 
 @export
@@ -159,6 +167,7 @@ def Get_File_Name(File: SourceFileEntry) -> NameId:
     :param File: Source file to get the filename from.
     :return:     NameId for the filename.
     """
+    return 0
 
 
 @export
@@ -170,6 +179,7 @@ def Get_Directory_Name(File: SourceFileEntry) -> NameId:
     :param File: Source file to get the directory name from.
     :return:     NameId for the directory.
     """
+    return 0
 
 
 @export
@@ -181,6 +191,7 @@ def Get_File_Buffer(File: SourceFileEntry) -> bytes:
     :param File: Source file to get the buffer from.
     :return:     Type: ``File_Buffer_Ptr``
     """
+    return 0
 
 
 @export
@@ -192,6 +203,7 @@ def Get_File_Length(File: SourceFileEntry) -> int:
     :param File: Source file
     :return:     Type: ``Source_Ptr``
     """
+    return 0
 
 
 @export
@@ -205,6 +217,7 @@ def Set_File_Length(File: SourceFileEntry, Length: int) -> None:
     :param File:   Source file
     :param Length: Length for the file. Type: ``Source_Ptr``
     """
+    return 0
 
 
 # @export
@@ -219,6 +232,7 @@ def Read_Source_File(Directory: NameId, Name: NameId) -> SourceFileEntry:
     :param Name:      File name
     :return:          Return ``No_Source_File_Entry``, if the file does not exist.
     """
+    return 0
 
 
 @export
@@ -236,6 +250,7 @@ def Reserve_Source_File(
     :param Length:    Length to reserve. Type: ``Source_Ptr``
     :return:          SourceFile
     """
+    return 0
 
 
 @export
@@ -272,3 +287,4 @@ def Get_Last_Source_File_Entry() -> SourceFileEntry:
 
     :return: Last SourceFileEntry. Type: ``SourceFileEntry``
     """
+    return 0
diff --git a/pyGHDL/libghdl/files_map_editor.py b/pyGHDL/libghdl/files_map_editor.py
index 2009af882..996db5931 100644
--- a/pyGHDL/libghdl/files_map_editor.py
+++ b/pyGHDL/libghdl/files_map_editor.py
@@ -63,6 +63,7 @@ def _Replace_Text(
     :param Text_Length:  Type: ``Source_Ptr``
     :return:             Return True in case of success, False in case of failure (the gap is too small).
     """
+    return False
 
 
 @export
diff --git a/pyGHDL/libghdl/libraries.py b/pyGHDL/libghdl/libraries.py
index 7dd417054..07075044d 100644
--- a/pyGHDL/libghdl/libraries.py
+++ b/pyGHDL/libghdl/libraries.py
@@ -72,6 +72,7 @@ def Get_Libraries_Chain() -> Iir_Library_Declaration:
 
     :return: undocumented
     """
+    return 0
 
 
 @export
@@ -116,6 +117,7 @@ def Find_Entity_For_Component(Name: NameId) -> Iir_Design_Unit:
     :param Name: Entity name to search for.
     :return:     undocumented
     """
+    return 0
 
 
 @export
@@ -127,6 +129,7 @@ def Get_Library_No_Create(Ident: NameId) -> Iir_Library_Declaration:
     :param Ident: Library to look for.
     :return:      Return :attr:`~pyGHDL.libghdl.vhdl.nodes.Null_Iir` if it doesn't exist.
     """
+    return 0
 
 
 @export
@@ -141,3 +144,4 @@ def Find_Primary_Unit(
     :param Name:    Primary unit to search for.
     :return:        undocumented
     """
+    return 0
diff --git a/pyGHDL/libghdl/name_table.py b/pyGHDL/libghdl/name_table.py
index 408168797..8718982af 100644
--- a/pyGHDL/libghdl/name_table.py
+++ b/pyGHDL/libghdl/name_table.py
@@ -53,12 +53,14 @@ def Get_Name_Length(Id: NameId) -> int:
     :param Id: NameId for the identifier to query.
     :return:   Length of the identifier.
     """
+    return 0
 
 
 # @export
 @BindToLibGHDL("name_table__get_name_ptr")
 def _Get_Name_Ptr(Id: NameId) -> c_char_p:
     """"""
+    return ""
 
 
 @export
@@ -78,6 +80,7 @@ def Get_Name_Ptr(Id: NameId) -> str:
 @BindToLibGHDL("name_table__get_character")
 def _Get_Character(Id: NameId) -> c_char:
     """"""
+    return 0
 
 
 @export
@@ -99,6 +102,7 @@ def Get_Character(Id: NameId) -> str:
 @BindToLibGHDL("name_table__get_identifier_with_len")
 def _Get_Identifier(string: c_char_p, length: int) -> NameId:
     """"""
+    return 0
 
 
 @export
diff --git a/pyGHDL/libghdl/requirements.txt b/pyGHDL/libghdl/requirements.txt
new file mode 100644
index 000000000..b0f362aea
--- /dev/null
+++ b/pyGHDL/libghdl/requirements.txt
@@ -0,0 +1 @@
+pydecor>=2.0.1
diff --git a/pyGHDL/libghdl/vhdl/flists.py b/pyGHDL/libghdl/vhdl/flists.py
index 3829921f3..9d5b7fdb7 100644
--- a/pyGHDL/libghdl/vhdl/flists.py
+++ b/pyGHDL/libghdl/vhdl/flists.py
@@ -56,6 +56,7 @@ def Flast(FList: int) -> int:
     :param FList: List to query.
     :return:      Index of the last element in the list.
     """
+    return 0
 
 
 @export
@@ -67,6 +68,7 @@ def Length(FList: int) -> int:
     :param FList: List to query.
     :return:      Number of elements in the list.
     """
+    return 0
 
 
 @export
@@ -80,3 +82,4 @@ def Get_Nth_Element(FList: int, N: int) -> int:
     :param FList: List to query.
     :return:      Type: ``El_Type``
     """
+    return 0
diff --git a/pyGHDL/libghdl/vhdl/lists.py b/pyGHDL/libghdl/vhdl/lists.py
index d9e4fda6c..6f8370a09 100644
--- a/pyGHDL/libghdl/vhdl/lists.py
+++ b/pyGHDL/libghdl/vhdl/lists.py
@@ -125,6 +125,7 @@ def Get_Nbr_Elements(List: int) -> int:
     :param List: The list to use.
     :return:     Number of list elements.
     """
+    return 0
 
 
 @export
@@ -135,6 +136,7 @@ def Create_Iir_List() -> int:
 
     :return: undocumented; Type: ``List_Type``
     """
+    return 0
 
 
 @export
diff --git a/pyGHDL/libghdl/vhdl/nodes.py b/pyGHDL/libghdl/vhdl/nodes.py
index 923f49606..9bffe757c 100644
--- a/pyGHDL/libghdl/vhdl/nodes.py
+++ b/pyGHDL/libghdl/vhdl/nodes.py
@@ -1803,18 +1803,21 @@ class Iir_Predefined(IntEnum):
 @BindToLibGHDL("vhdl__nodes__get_kind")
 def Get_Kind(node: Iir) -> IirKind:
     """Get node kind."""
+    return 0
 
 
 @export
 @BindToLibGHDL("vhdl__nodes__get_location")
 def Get_Location(node: Iir) -> LocationType:
     """"""
+    return 0
 
 
 @export
 @BindToLibGHDL("vhdl__nodes__get_first_design_unit")
 def Get_First_Design_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1827,6 +1830,7 @@ def Set_First_Design_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_last_design_unit")
 def Get_Last_Design_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1839,6 +1843,7 @@ def Set_Last_Design_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_library_declaration")
 def Get_Library_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1851,6 +1856,7 @@ def Set_Library_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_file_checksum")
 def Get_File_Checksum(obj: Iir) -> FileChecksumId:
     """"""
+    return 0
 
 
 @export
@@ -1863,6 +1869,7 @@ def Set_File_Checksum(obj: Iir, value: FileChecksumId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_analysis_time_stamp")
 def Get_Analysis_Time_Stamp(obj: Iir) -> TimeStampId:
     """"""
+    return 0
 
 
 @export
@@ -1875,6 +1882,7 @@ def Set_Analysis_Time_Stamp(obj: Iir, value: TimeStampId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_file_source")
 def Get_Design_File_Source(obj: Iir) -> SourceFileEntry:
     """"""
+    return 0
 
 
 @export
@@ -1887,6 +1895,7 @@ def Set_Design_File_Source(obj: Iir, value: SourceFileEntry) -> None:
 @BindToLibGHDL("vhdl__nodes__get_library")
 def Get_Library(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1899,6 +1908,7 @@ def Set_Library(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_file_dependence_list")
 def Get_File_Dependence_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1911,6 +1921,7 @@ def Set_File_Dependence_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_file_filename")
 def Get_Design_File_Filename(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -1923,6 +1934,7 @@ def Set_Design_File_Filename(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_file_directory")
 def Get_Design_File_Directory(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -1935,6 +1947,7 @@ def Set_Design_File_Directory(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_file")
 def Get_Design_File(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1947,6 +1960,7 @@ def Set_Design_File(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_file_chain")
 def Get_Design_File_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1959,6 +1973,7 @@ def Set_Design_File_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_library_directory")
 def Get_Library_Directory(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -1971,6 +1986,7 @@ def Set_Library_Directory(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_date")
 def Get_Date(obj: Iir) -> DateType:
     """"""
+    return 0
 
 
 @export
@@ -1983,6 +1999,7 @@ def Set_Date(obj: Iir, value: DateType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_context_items")
 def Get_Context_Items(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -1995,6 +2012,7 @@ def Set_Context_Items(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_dependence_list")
 def Get_Dependence_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2007,6 +2025,7 @@ def Set_Dependence_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_analysis_checks_list")
 def Get_Analysis_Checks_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2019,6 +2038,7 @@ def Set_Analysis_Checks_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_date_state")
 def Get_Date_State(obj: Iir) -> DateStateType:
     """"""
+    return 0
 
 
 @export
@@ -2031,6 +2051,7 @@ def Set_Date_State(obj: Iir, value: DateStateType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guarded_target_state")
 def Get_Guarded_Target_State(obj: Iir) -> TriStateType:
     """"""
+    return 0
 
 
 @export
@@ -2043,6 +2064,7 @@ def Set_Guarded_Target_State(obj: Iir, value: TriStateType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_library_unit")
 def Get_Library_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2055,6 +2077,7 @@ def Set_Library_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_hash_chain")
 def Get_Hash_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2067,6 +2090,7 @@ def Set_Hash_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_unit_source_pos")
 def Get_Design_Unit_Source_Pos(obj: Iir) -> SourcePtr:
     """"""
+    return 0
 
 
 @export
@@ -2079,6 +2103,7 @@ def Set_Design_Unit_Source_Pos(obj: Iir, value: SourcePtr) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_unit_source_line")
 def Get_Design_Unit_Source_Line(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
@@ -2091,6 +2116,7 @@ def Set_Design_Unit_Source_Line(obj: Iir, value: Int32) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_unit_source_col")
 def Get_Design_Unit_Source_Col(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
@@ -2103,6 +2129,7 @@ def Set_Design_Unit_Source_Col(obj: Iir, value: Int32) -> None:
 @BindToLibGHDL("vhdl__nodes__get_value")
 def Get_Value(obj: Iir) -> Int64:
     """"""
+    return 0
 
 
 @export
@@ -2115,6 +2142,7 @@ def Set_Value(obj: Iir, value: Int64) -> None:
 @BindToLibGHDL("vhdl__nodes__get_enum_pos")
 def Get_Enum_Pos(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2127,6 +2155,7 @@ def Set_Enum_Pos(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_physical_literal")
 def Get_Physical_Literal(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2139,6 +2168,7 @@ def Set_Physical_Literal(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_fp_value")
 def Get_Fp_Value(obj: Iir) -> Fp64:
     """"""
+    return 0
 
 
 @export
@@ -2151,6 +2181,7 @@ def Set_Fp_Value(obj: Iir, value: Fp64) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simple_aggregate_list")
 def Get_Simple_Aggregate_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2163,6 +2194,7 @@ def Set_Simple_Aggregate_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_string8_id")
 def Get_String8_Id(obj: Iir) -> String8Id:
     """"""
+    return 0
 
 
 @export
@@ -2175,6 +2207,7 @@ def Set_String8_Id(obj: Iir, value: String8Id) -> None:
 @BindToLibGHDL("vhdl__nodes__get_string_length")
 def Get_String_Length(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
@@ -2187,6 +2220,7 @@ def Set_String_Length(obj: Iir, value: Int32) -> None:
 @BindToLibGHDL("vhdl__nodes__get_bit_string_base")
 def Get_Bit_String_Base(obj: Iir) -> NumberBaseType:
     """"""
+    return 0
 
 
 @export
@@ -2199,6 +2233,7 @@ def Set_Bit_String_Base(obj: Iir, value: NumberBaseType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_signed")
 def Get_Has_Signed(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2211,6 +2246,7 @@ def Set_Has_Signed(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_sign")
 def Get_Has_Sign(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2223,6 +2259,7 @@ def Set_Has_Sign(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_length")
 def Get_Has_Length(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2235,6 +2272,7 @@ def Set_Has_Length(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_literal_length")
 def Get_Literal_Length(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
@@ -2247,6 +2285,7 @@ def Set_Literal_Length(obj: Iir, value: Int32) -> None:
 @BindToLibGHDL("vhdl__nodes__get_literal_origin")
 def Get_Literal_Origin(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2259,6 +2298,7 @@ def Set_Literal_Origin(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_range_origin")
 def Get_Range_Origin(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2271,6 +2311,7 @@ def Set_Range_Origin(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_literal_subtype")
 def Get_Literal_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2283,6 +2324,7 @@ def Set_Literal_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_allocator_subtype")
 def Get_Allocator_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2295,6 +2337,7 @@ def Set_Allocator_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_entity_class")
 def Get_Entity_Class(obj: Iir) -> Tok:
     """"""
+    return 0
 
 
 @export
@@ -2307,6 +2350,7 @@ def Set_Entity_Class(obj: Iir, value: Tok) -> None:
 @BindToLibGHDL("vhdl__nodes__get_entity_name_list")
 def Get_Entity_Name_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2319,6 +2363,7 @@ def Set_Entity_Name_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_designator")
 def Get_Attribute_Designator(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2331,6 +2376,7 @@ def Set_Attribute_Designator(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_specification_chain")
 def Get_Attribute_Specification_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2343,6 +2389,7 @@ def Set_Attribute_Specification_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_specification")
 def Get_Attribute_Specification(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2355,6 +2402,7 @@ def Set_Attribute_Specification(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_static_attribute_flag")
 def Get_Static_Attribute_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2367,6 +2415,7 @@ def Set_Static_Attribute_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_list")
 def Get_Signal_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2379,6 +2428,7 @@ def Set_Signal_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_quantity_list")
 def Get_Quantity_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2391,6 +2441,7 @@ def Set_Quantity_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_designated_entity")
 def Get_Designated_Entity(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2403,6 +2454,7 @@ def Set_Designated_Entity(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_formal")
 def Get_Formal(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2415,6 +2467,7 @@ def Set_Formal(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_actual")
 def Get_Actual(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2427,6 +2480,7 @@ def Set_Actual(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_actual_conversion")
 def Get_Actual_Conversion(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2439,6 +2493,7 @@ def Set_Actual_Conversion(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_formal_conversion")
 def Get_Formal_Conversion(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2451,6 +2506,7 @@ def Set_Formal_Conversion(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_whole_association_flag")
 def Get_Whole_Association_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2463,6 +2519,7 @@ def Set_Whole_Association_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_collapse_signal_flag")
 def Get_Collapse_Signal_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2475,6 +2532,7 @@ def Set_Collapse_Signal_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_artificial_flag")
 def Get_Artificial_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2487,6 +2545,7 @@ def Set_Artificial_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_open_flag")
 def Get_Open_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2499,6 +2558,7 @@ def Set_Open_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_after_drivers_flag")
 def Get_After_Drivers_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2511,6 +2571,7 @@ def Set_After_Drivers_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_we_value")
 def Get_We_Value(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2523,6 +2584,7 @@ def Set_We_Value(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_time")
 def Get_Time(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2535,6 +2597,7 @@ def Set_Time(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_associated_expr")
 def Get_Associated_Expr(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2547,6 +2610,7 @@ def Set_Associated_Expr(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_associated_block")
 def Get_Associated_Block(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2559,6 +2623,7 @@ def Set_Associated_Block(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_associated_chain")
 def Get_Associated_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2571,6 +2636,7 @@ def Set_Associated_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_choice_name")
 def Get_Choice_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2583,6 +2649,7 @@ def Set_Choice_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_choice_expression")
 def Get_Choice_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2595,6 +2662,7 @@ def Set_Choice_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_choice_range")
 def Get_Choice_Range(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2607,6 +2675,7 @@ def Set_Choice_Range(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_same_alternative_flag")
 def Get_Same_Alternative_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2619,6 +2688,7 @@ def Set_Same_Alternative_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_type_flag")
 def Get_Element_Type_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2631,6 +2701,7 @@ def Set_Element_Type_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_architecture")
 def Get_Architecture(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2643,6 +2714,7 @@ def Set_Architecture(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_block_specification")
 def Get_Block_Specification(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2655,6 +2727,7 @@ def Set_Block_Specification(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_prev_block_configuration")
 def Get_Prev_Block_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2667,6 +2740,7 @@ def Set_Prev_Block_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_configuration_item_chain")
 def Get_Configuration_Item_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2679,6 +2753,7 @@ def Set_Configuration_Item_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_value_chain")
 def Get_Attribute_Value_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2691,6 +2766,7 @@ def Set_Attribute_Value_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_spec_chain")
 def Get_Spec_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2703,6 +2779,7 @@ def Set_Spec_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_value_chain")
 def Get_Value_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2715,6 +2792,7 @@ def Set_Value_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_value_spec_chain")
 def Get_Attribute_Value_Spec_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2727,6 +2805,7 @@ def Set_Attribute_Value_Spec_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_entity_name")
 def Get_Entity_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2739,6 +2818,7 @@ def Set_Entity_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_package")
 def Get_Package(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2751,6 +2831,7 @@ def Set_Package(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_package_body")
 def Get_Package_Body(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2763,6 +2844,7 @@ def Set_Package_Body(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_instance_package_body")
 def Get_Instance_Package_Body(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2775,6 +2857,7 @@ def Set_Instance_Package_Body(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_need_body")
 def Get_Need_Body(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2787,6 +2870,7 @@ def Set_Need_Body(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_macro_expanded_flag")
 def Get_Macro_Expanded_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2799,6 +2883,7 @@ def Set_Macro_Expanded_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_need_instance_bodies")
 def Get_Need_Instance_Bodies(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -2811,6 +2896,7 @@ def Set_Need_Instance_Bodies(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_hierarchical_name")
 def Get_Hierarchical_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2823,6 +2909,7 @@ def Set_Hierarchical_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_inherit_spec_chain")
 def Get_Inherit_Spec_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2835,6 +2922,7 @@ def Set_Inherit_Spec_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_vunit_item_chain")
 def Get_Vunit_Item_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2847,6 +2935,7 @@ def Set_Vunit_Item_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_bound_vunit_chain")
 def Get_Bound_Vunit_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2859,6 +2948,7 @@ def Set_Bound_Vunit_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_verification_block_configuration")
 def Get_Verification_Block_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2871,6 +2961,7 @@ def Set_Verification_Block_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_block_configuration")
 def Get_Block_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2883,6 +2974,7 @@ def Set_Block_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_concurrent_statement_chain")
 def Get_Concurrent_Statement_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2895,6 +2987,7 @@ def Set_Concurrent_Statement_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_chain")
 def Get_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2907,6 +3000,7 @@ def Set_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_port_chain")
 def Get_Port_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2919,6 +3013,7 @@ def Set_Port_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_generic_chain")
 def Get_Generic_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2931,6 +3026,7 @@ def Set_Generic_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type")
 def Get_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2943,6 +3039,7 @@ def Set_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subtype_indication")
 def Get_Subtype_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2955,6 +3052,7 @@ def Set_Subtype_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_discrete_range")
 def Get_Discrete_Range(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2967,6 +3065,7 @@ def Set_Discrete_Range(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_definition")
 def Get_Type_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2979,6 +3078,7 @@ def Set_Type_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subtype_definition")
 def Get_Subtype_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -2991,6 +3091,7 @@ def Set_Subtype_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_incomplete_type_declaration")
 def Get_Incomplete_Type_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3003,6 +3104,7 @@ def Set_Incomplete_Type_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_interface_type_subprograms")
 def Get_Interface_Type_Subprograms(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3015,6 +3117,7 @@ def Set_Interface_Type_Subprograms(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_nature_definition")
 def Get_Nature_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3027,6 +3130,7 @@ def Set_Nature_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_nature")
 def Get_Nature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3039,6 +3143,7 @@ def Set_Nature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subnature_indication")
 def Get_Subnature_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3051,6 +3156,7 @@ def Set_Subnature_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_mode")
 def Get_Mode(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3063,6 +3169,7 @@ def Set_Mode(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guarded_signal_flag")
 def Get_Guarded_Signal_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3075,6 +3182,7 @@ def Set_Guarded_Signal_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_kind")
 def Get_Signal_Kind(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3087,6 +3195,7 @@ def Set_Signal_Kind(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_base_name")
 def Get_Base_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3099,6 +3208,7 @@ def Set_Base_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_interface_declaration_chain")
 def Get_Interface_Declaration_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3111,6 +3221,7 @@ def Set_Interface_Declaration_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subprogram_specification")
 def Get_Subprogram_Specification(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3123,6 +3234,7 @@ def Set_Subprogram_Specification(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_sequential_statement_chain")
 def Get_Sequential_Statement_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3135,6 +3247,7 @@ def Set_Sequential_Statement_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simultaneous_statement_chain")
 def Get_Simultaneous_Statement_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3147,6 +3260,7 @@ def Set_Simultaneous_Statement_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subprogram_body")
 def Get_Subprogram_Body(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3159,6 +3273,7 @@ def Set_Subprogram_Body(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_overload_number")
 def Get_Overload_Number(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3171,6 +3286,7 @@ def Set_Overload_Number(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subprogram_depth")
 def Get_Subprogram_Depth(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3183,6 +3299,7 @@ def Set_Subprogram_Depth(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subprogram_hash")
 def Get_Subprogram_Hash(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3195,6 +3312,7 @@ def Set_Subprogram_Hash(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_impure_depth")
 def Get_Impure_Depth(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3207,6 +3325,7 @@ def Set_Impure_Depth(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_return_type")
 def Get_Return_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3219,6 +3338,7 @@ def Set_Return_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_implicit_definition")
 def Get_Implicit_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3231,6 +3351,7 @@ def Set_Implicit_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_uninstantiated_subprogram_name")
 def Get_Uninstantiated_Subprogram_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3243,6 +3364,7 @@ def Set_Uninstantiated_Subprogram_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_default_value")
 def Get_Default_Value(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3255,6 +3377,7 @@ def Set_Default_Value(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_deferred_declaration")
 def Get_Deferred_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3267,6 +3390,7 @@ def Set_Deferred_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_deferred_declaration_flag")
 def Get_Deferred_Declaration_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3279,6 +3403,7 @@ def Set_Deferred_Declaration_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_shared_flag")
 def Get_Shared_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3291,6 +3416,7 @@ def Set_Shared_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_design_unit")
 def Get_Design_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3303,6 +3429,7 @@ def Set_Design_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_block_statement")
 def Get_Block_Statement(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3315,6 +3442,7 @@ def Set_Block_Statement(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_driver")
 def Get_Signal_Driver(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3327,6 +3455,7 @@ def Set_Signal_Driver(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_declaration_chain")
 def Get_Declaration_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3339,6 +3468,7 @@ def Set_Declaration_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_file_logical_name")
 def Get_File_Logical_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3351,6 +3481,7 @@ def Set_File_Logical_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_file_open_kind")
 def Get_File_Open_Kind(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3363,6 +3494,7 @@ def Set_File_Open_Kind(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_position")
 def Get_Element_Position(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3375,6 +3507,7 @@ def Set_Element_Position(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_use_clause_chain")
 def Get_Use_Clause_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3387,6 +3520,7 @@ def Set_Use_Clause_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_context_reference_chain")
 def Get_Context_Reference_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3399,6 +3533,7 @@ def Set_Context_Reference_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_selected_name")
 def Get_Selected_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3411,6 +3546,7 @@ def Set_Selected_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_declarator")
 def Get_Type_Declarator(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3423,6 +3559,7 @@ def Set_Type_Declarator(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_complete_type_definition")
 def Get_Complete_Type_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3435,6 +3572,7 @@ def Set_Complete_Type_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_incomplete_type_ref_chain")
 def Get_Incomplete_Type_Ref_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3447,6 +3585,7 @@ def Set_Incomplete_Type_Ref_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_associated_type")
 def Get_Associated_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3459,6 +3598,7 @@ def Set_Associated_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_enumeration_literal_list")
 def Get_Enumeration_Literal_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3471,6 +3611,7 @@ def Set_Enumeration_Literal_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_entity_class_entry_chain")
 def Get_Entity_Class_Entry_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3483,6 +3624,7 @@ def Set_Entity_Class_Entry_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_group_constituent_list")
 def Get_Group_Constituent_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3495,6 +3637,7 @@ def Set_Group_Constituent_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_unit_chain")
 def Get_Unit_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3507,6 +3650,7 @@ def Set_Unit_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_primary_unit")
 def Get_Primary_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3519,6 +3663,7 @@ def Set_Primary_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_identifier")
 def Get_Identifier(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -3531,6 +3676,7 @@ def Set_Identifier(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_label")
 def Get_Label(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -3543,6 +3689,7 @@ def Set_Label(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_visible_flag")
 def Get_Visible_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3555,6 +3702,7 @@ def Set_Visible_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_range_constraint")
 def Get_Range_Constraint(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3567,6 +3715,7 @@ def Set_Range_Constraint(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_direction")
 def Get_Direction(obj: Iir) -> DirectionType:
     """"""
+    return 0
 
 
 @export
@@ -3579,6 +3728,7 @@ def Set_Direction(obj: Iir, value: DirectionType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_left_limit")
 def Get_Left_Limit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3591,6 +3741,7 @@ def Set_Left_Limit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_right_limit")
 def Get_Right_Limit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3603,6 +3754,7 @@ def Set_Right_Limit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_left_limit_expr")
 def Get_Left_Limit_Expr(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3615,6 +3767,7 @@ def Set_Left_Limit_Expr(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_right_limit_expr")
 def Get_Right_Limit_Expr(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3627,6 +3780,7 @@ def Set_Right_Limit_Expr(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parent_type")
 def Get_Parent_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3639,6 +3793,7 @@ def Set_Parent_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simple_nature")
 def Get_Simple_Nature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3651,6 +3806,7 @@ def Set_Simple_Nature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_base_nature")
 def Get_Base_Nature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3663,6 +3819,7 @@ def Set_Base_Nature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_resolution_indication")
 def Get_Resolution_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3675,6 +3832,7 @@ def Set_Resolution_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_record_element_resolution_chain")
 def Get_Record_Element_Resolution_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3687,6 +3845,7 @@ def Set_Record_Element_Resolution_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_tolerance")
 def Get_Tolerance(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3699,6 +3858,7 @@ def Set_Tolerance(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_plus_terminal_name")
 def Get_Plus_Terminal_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3711,6 +3871,7 @@ def Set_Plus_Terminal_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_minus_terminal_name")
 def Get_Minus_Terminal_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3723,6 +3884,7 @@ def Set_Minus_Terminal_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_plus_terminal")
 def Get_Plus_Terminal(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3735,6 +3897,7 @@ def Set_Plus_Terminal(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_minus_terminal")
 def Get_Minus_Terminal(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3747,6 +3910,7 @@ def Set_Minus_Terminal(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_magnitude_expression")
 def Get_Magnitude_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3759,6 +3923,7 @@ def Set_Magnitude_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_phase_expression")
 def Get_Phase_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3771,6 +3936,7 @@ def Set_Phase_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_power_expression")
 def Get_Power_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3783,6 +3949,7 @@ def Set_Power_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simultaneous_left")
 def Get_Simultaneous_Left(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3795,6 +3962,7 @@ def Set_Simultaneous_Left(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simultaneous_right")
 def Get_Simultaneous_Right(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3807,6 +3975,7 @@ def Set_Simultaneous_Right(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_text_file_flag")
 def Get_Text_File_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3819,6 +3988,7 @@ def Set_Text_File_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_only_characters_flag")
 def Get_Only_Characters_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3831,6 +4001,7 @@ def Set_Only_Characters_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_is_character_type")
 def Get_Is_Character_Type(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3843,6 +4014,7 @@ def Set_Is_Character_Type(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_nature_staticness")
 def Get_Nature_Staticness(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3855,6 +4027,7 @@ def Set_Nature_Staticness(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_staticness")
 def Get_Type_Staticness(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3867,6 +4040,7 @@ def Set_Type_Staticness(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_constraint_state")
 def Get_Constraint_State(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3879,6 +4053,7 @@ def Set_Constraint_State(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_subtype_list")
 def Get_Index_Subtype_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3891,6 +4066,7 @@ def Set_Index_Subtype_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_subtype_definition_list")
 def Get_Index_Subtype_Definition_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3903,6 +4079,7 @@ def Set_Index_Subtype_Definition_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_subtype_indication")
 def Get_Element_Subtype_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3915,6 +4092,7 @@ def Set_Element_Subtype_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_subtype")
 def Get_Element_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3927,6 +4105,7 @@ def Set_Element_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_subnature_indication")
 def Get_Element_Subnature_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3939,6 +4118,7 @@ def Set_Element_Subnature_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_element_subnature")
 def Get_Element_Subnature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3951,6 +4131,7 @@ def Set_Element_Subnature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_constraint_list")
 def Get_Index_Constraint_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3963,6 +4144,7 @@ def Set_Index_Constraint_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_array_element_constraint")
 def Get_Array_Element_Constraint(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -3975,6 +4157,7 @@ def Set_Array_Element_Constraint(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_array_constraint_flag")
 def Get_Has_Array_Constraint_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3987,6 +4170,7 @@ def Set_Has_Array_Constraint_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_element_constraint_flag")
 def Get_Has_Element_Constraint_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -3999,6 +4183,7 @@ def Set_Has_Element_Constraint_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_elements_declaration_list")
 def Get_Elements_Declaration_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4011,6 +4196,7 @@ def Set_Elements_Declaration_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_owned_elements_chain")
 def Get_Owned_Elements_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4023,6 +4209,7 @@ def Set_Owned_Elements_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_designated_type")
 def Get_Designated_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4035,6 +4222,7 @@ def Set_Designated_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_designated_subtype_indication")
 def Get_Designated_Subtype_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4047,6 +4235,7 @@ def Set_Designated_Subtype_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_list")
 def Get_Index_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4059,6 +4248,7 @@ def Set_Index_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_reference")
 def Get_Reference(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4071,6 +4261,7 @@ def Set_Reference(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_nature_declarator")
 def Get_Nature_Declarator(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4083,6 +4274,7 @@ def Set_Nature_Declarator(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_across_type_mark")
 def Get_Across_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4095,6 +4287,7 @@ def Set_Across_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_through_type_mark")
 def Get_Through_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4107,6 +4300,7 @@ def Set_Through_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_across_type_definition")
 def Get_Across_Type_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4119,6 +4313,7 @@ def Set_Across_Type_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_through_type_definition")
 def Get_Through_Type_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4131,6 +4326,7 @@ def Set_Through_Type_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_across_type")
 def Get_Across_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4143,6 +4339,7 @@ def Set_Across_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_through_type")
 def Get_Through_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4155,6 +4352,7 @@ def Set_Through_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_target")
 def Get_Target(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4167,6 +4365,7 @@ def Set_Target(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_waveform_chain")
 def Get_Waveform_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4179,6 +4378,7 @@ def Set_Waveform_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guard")
 def Get_Guard(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4191,6 +4391,7 @@ def Set_Guard(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_delay_mechanism")
 def Get_Delay_Mechanism(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4203,6 +4404,7 @@ def Set_Delay_Mechanism(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_reject_time_expression")
 def Get_Reject_Time_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4215,6 +4417,7 @@ def Set_Reject_Time_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_force_mode")
 def Get_Force_Mode(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4227,6 +4430,7 @@ def Set_Force_Mode(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_force_mode")
 def Get_Has_Force_Mode(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4239,6 +4443,7 @@ def Set_Has_Force_Mode(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_sensitivity_list")
 def Get_Sensitivity_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4251,6 +4456,7 @@ def Set_Sensitivity_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_process_origin")
 def Get_Process_Origin(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4263,6 +4469,7 @@ def Set_Process_Origin(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_package_origin")
 def Get_Package_Origin(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4275,6 +4482,7 @@ def Set_Package_Origin(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_condition_clause")
 def Get_Condition_Clause(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4287,6 +4495,7 @@ def Set_Condition_Clause(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_break_element")
 def Get_Break_Element(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4299,6 +4508,7 @@ def Set_Break_Element(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_selector_quantity")
 def Get_Selector_Quantity(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4311,6 +4521,7 @@ def Set_Selector_Quantity(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_break_quantity")
 def Get_Break_Quantity(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4323,6 +4534,7 @@ def Set_Break_Quantity(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_timeout_clause")
 def Get_Timeout_Clause(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4335,6 +4547,7 @@ def Set_Timeout_Clause(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_postponed_flag")
 def Get_Postponed_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4347,6 +4560,7 @@ def Set_Postponed_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_callees_list")
 def Get_Callees_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4359,6 +4573,7 @@ def Set_Callees_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_passive_flag")
 def Get_Passive_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4371,6 +4586,7 @@ def Set_Passive_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_resolution_function_flag")
 def Get_Resolution_Function_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4383,6 +4599,7 @@ def Set_Resolution_Function_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_wait_state")
 def Get_Wait_State(obj: Iir) -> TriStateType:
     """"""
+    return 0
 
 
 @export
@@ -4395,6 +4612,7 @@ def Set_Wait_State(obj: Iir, value: TriStateType) -> None:
 @BindToLibGHDL("vhdl__nodes__get_all_sensitized_state")
 def Get_All_Sensitized_State(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4407,6 +4625,7 @@ def Set_All_Sensitized_State(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_seen_flag")
 def Get_Seen_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4419,6 +4638,7 @@ def Set_Seen_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_pure_flag")
 def Get_Pure_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4431,6 +4651,7 @@ def Set_Pure_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_foreign_flag")
 def Get_Foreign_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4443,6 +4664,7 @@ def Set_Foreign_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_resolved_flag")
 def Get_Resolved_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4455,6 +4677,7 @@ def Set_Resolved_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_type_flag")
 def Get_Signal_Type_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4467,6 +4690,7 @@ def Set_Signal_Type_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_signal_flag")
 def Get_Has_Signal_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4479,6 +4703,7 @@ def Set_Has_Signal_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_purity_state")
 def Get_Purity_State(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4491,6 +4716,7 @@ def Set_Purity_State(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_elab_flag")
 def Get_Elab_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4503,6 +4729,7 @@ def Set_Elab_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_vendor_library_flag")
 def Get_Vendor_Library_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4515,6 +4742,7 @@ def Set_Vendor_Library_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_configuration_mark_flag")
 def Get_Configuration_Mark_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4527,6 +4755,7 @@ def Set_Configuration_Mark_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_configuration_done_flag")
 def Get_Configuration_Done_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4539,6 +4768,7 @@ def Set_Configuration_Done_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_constraint_flag")
 def Get_Index_Constraint_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4551,6 +4781,7 @@ def Set_Index_Constraint_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_hide_implicit_flag")
 def Get_Hide_Implicit_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4563,6 +4794,7 @@ def Set_Hide_Implicit_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_assertion_condition")
 def Get_Assertion_Condition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4575,6 +4807,7 @@ def Set_Assertion_Condition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_report_expression")
 def Get_Report_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4587,6 +4820,7 @@ def Set_Report_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_severity_expression")
 def Get_Severity_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4599,6 +4833,7 @@ def Set_Severity_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_instantiated_unit")
 def Get_Instantiated_Unit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4611,6 +4846,7 @@ def Set_Instantiated_Unit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_generic_map_aspect_chain")
 def Get_Generic_Map_Aspect_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4623,6 +4859,7 @@ def Set_Generic_Map_Aspect_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_port_map_aspect_chain")
 def Get_Port_Map_Aspect_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4635,6 +4872,7 @@ def Set_Port_Map_Aspect_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_configuration_name")
 def Get_Configuration_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4647,6 +4885,7 @@ def Set_Configuration_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_component_configuration")
 def Get_Component_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4659,6 +4898,7 @@ def Set_Component_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_configuration_specification")
 def Get_Configuration_Specification(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4671,6 +4911,7 @@ def Set_Configuration_Specification(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_default_binding_indication")
 def Get_Default_Binding_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4683,6 +4924,7 @@ def Set_Default_Binding_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_default_configuration_declaration")
 def Get_Default_Configuration_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4695,6 +4937,7 @@ def Set_Default_Configuration_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_expression")
 def Get_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4707,6 +4950,7 @@ def Set_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_conditional_expression_chain")
 def Get_Conditional_Expression_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4719,6 +4963,7 @@ def Set_Conditional_Expression_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_allocator_designated_type")
 def Get_Allocator_Designated_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4731,6 +4976,7 @@ def Set_Allocator_Designated_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_selected_waveform_chain")
 def Get_Selected_Waveform_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4743,6 +4989,7 @@ def Set_Selected_Waveform_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_conditional_waveform_chain")
 def Get_Conditional_Waveform_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4755,6 +5002,7 @@ def Set_Conditional_Waveform_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guard_expression")
 def Get_Guard_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4767,6 +5015,7 @@ def Set_Guard_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guard_decl")
 def Get_Guard_Decl(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4779,6 +5028,7 @@ def Set_Guard_Decl(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_guard_sensitivity_list")
 def Get_Guard_Sensitivity_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4791,6 +5041,7 @@ def Set_Guard_Sensitivity_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_attribute_chain")
 def Get_Signal_Attribute_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4803,6 +5054,7 @@ def Set_Signal_Attribute_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_block_block_configuration")
 def Get_Block_Block_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4815,6 +5067,7 @@ def Set_Block_Block_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_package_header")
 def Get_Package_Header(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4827,6 +5080,7 @@ def Set_Package_Header(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_block_header")
 def Get_Block_Header(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4839,6 +5093,7 @@ def Set_Block_Header(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_uninstantiated_package_name")
 def Get_Uninstantiated_Package_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4851,6 +5106,7 @@ def Set_Uninstantiated_Package_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_uninstantiated_package_decl")
 def Get_Uninstantiated_Package_Decl(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4863,6 +5119,7 @@ def Set_Uninstantiated_Package_Decl(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_instance_source_file")
 def Get_Instance_Source_File(obj: Iir) -> SourceFileEntry:
     """"""
+    return 0
 
 
 @export
@@ -4875,6 +5132,7 @@ def Set_Instance_Source_File(obj: Iir, value: SourceFileEntry) -> None:
 @BindToLibGHDL("vhdl__nodes__get_generate_block_configuration")
 def Get_Generate_Block_Configuration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4887,6 +5145,7 @@ def Set_Generate_Block_Configuration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_generate_statement_body")
 def Get_Generate_Statement_Body(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4899,6 +5158,7 @@ def Set_Generate_Statement_Body(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_alternative_label")
 def Get_Alternative_Label(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -4911,6 +5171,7 @@ def Set_Alternative_Label(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_generate_else_clause")
 def Get_Generate_Else_Clause(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4923,6 +5184,7 @@ def Set_Generate_Else_Clause(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_condition")
 def Get_Condition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4935,6 +5197,7 @@ def Set_Condition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_else_clause")
 def Get_Else_Clause(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4947,6 +5210,7 @@ def Set_Else_Clause(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter_specification")
 def Get_Parameter_Specification(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4959,6 +5223,7 @@ def Set_Parameter_Specification(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parent")
 def Get_Parent(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4971,6 +5236,7 @@ def Set_Parent(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_loop_label")
 def Get_Loop_Label(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -4983,6 +5249,7 @@ def Set_Loop_Label(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_exit_flag")
 def Get_Exit_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -4995,6 +5262,7 @@ def Set_Exit_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_next_flag")
 def Get_Next_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5007,6 +5275,7 @@ def Set_Next_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_component_name")
 def Get_Component_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5019,6 +5288,7 @@ def Set_Component_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_instantiation_list")
 def Get_Instantiation_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5031,6 +5301,7 @@ def Set_Instantiation_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_entity_aspect")
 def Get_Entity_Aspect(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5043,6 +5314,7 @@ def Set_Entity_Aspect(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_default_entity_aspect")
 def Get_Default_Entity_Aspect(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5055,6 +5327,7 @@ def Set_Default_Entity_Aspect(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_binding_indication")
 def Get_Binding_Indication(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5067,6 +5340,7 @@ def Set_Binding_Indication(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_named_entity")
 def Get_Named_Entity(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5079,6 +5353,7 @@ def Set_Named_Entity(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_referenced_name")
 def Get_Referenced_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5091,6 +5366,7 @@ def Set_Referenced_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_expr_staticness")
 def Get_Expr_Staticness(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5103,6 +5379,7 @@ def Set_Expr_Staticness(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_scalar_size")
 def Get_Scalar_Size(obj: Iir) -> ScalarSize:
     """"""
+    return 0
 
 
 @export
@@ -5115,6 +5392,7 @@ def Set_Scalar_Size(obj: Iir, value: ScalarSize) -> None:
 @BindToLibGHDL("vhdl__nodes__get_error_origin")
 def Get_Error_Origin(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5127,6 +5405,7 @@ def Set_Error_Origin(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_operand")
 def Get_Operand(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5139,6 +5418,7 @@ def Set_Operand(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_left")
 def Get_Left(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5151,6 +5431,7 @@ def Set_Left(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_right")
 def Get_Right(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5163,6 +5444,7 @@ def Set_Right(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_unit_name")
 def Get_Unit_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5175,6 +5457,7 @@ def Set_Unit_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_name")
 def Get_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5187,6 +5470,7 @@ def Set_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_group_template_name")
 def Get_Group_Template_Name(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5199,6 +5483,7 @@ def Set_Group_Template_Name(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_name_staticness")
 def Get_Name_Staticness(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5211,6 +5496,7 @@ def Set_Name_Staticness(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_prefix")
 def Get_Prefix(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5223,6 +5509,7 @@ def Set_Prefix(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signature_prefix")
 def Get_Signature_Prefix(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5235,6 +5522,7 @@ def Set_Signature_Prefix(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_external_pathname")
 def Get_External_Pathname(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5247,6 +5535,7 @@ def Set_External_Pathname(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_pathname_suffix")
 def Get_Pathname_Suffix(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5259,6 +5548,7 @@ def Set_Pathname_Suffix(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_pathname_expression")
 def Get_Pathname_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5271,6 +5561,7 @@ def Set_Pathname_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_in_formal_flag")
 def Get_In_Formal_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5283,6 +5574,7 @@ def Set_In_Formal_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_slice_subtype")
 def Get_Slice_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5295,6 +5587,7 @@ def Set_Slice_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_suffix")
 def Get_Suffix(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5307,6 +5600,7 @@ def Set_Suffix(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_index_subtype")
 def Get_Index_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5319,6 +5613,7 @@ def Set_Index_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter")
 def Get_Parameter(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5331,6 +5626,7 @@ def Set_Parameter(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter_2")
 def Get_Parameter_2(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5343,6 +5639,7 @@ def Set_Parameter_2(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter_3")
 def Get_Parameter_3(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5355,6 +5652,7 @@ def Set_Parameter_3(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter_4")
 def Get_Parameter_4(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5367,6 +5665,7 @@ def Set_Parameter_4(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attr_chain")
 def Get_Attr_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5379,6 +5678,7 @@ def Set_Attr_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_signal_attribute_declaration")
 def Get_Signal_Attribute_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5391,6 +5691,7 @@ def Set_Signal_Attribute_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_actual_type")
 def Get_Actual_Type(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5403,6 +5704,7 @@ def Set_Actual_Type(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_actual_type_definition")
 def Get_Actual_Type_Definition(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5415,6 +5717,7 @@ def Set_Actual_Type_Definition(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_association_chain")
 def Get_Association_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5427,6 +5730,7 @@ def Set_Association_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_individual_association_chain")
 def Get_Individual_Association_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5439,6 +5743,7 @@ def Set_Individual_Association_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subprogram_association_chain")
 def Get_Subprogram_Association_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5451,6 +5756,7 @@ def Set_Subprogram_Association_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggregate_info")
 def Get_Aggregate_Info(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5463,6 +5769,7 @@ def Set_Aggregate_Info(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_sub_aggregate_info")
 def Get_Sub_Aggregate_Info(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5475,6 +5782,7 @@ def Set_Sub_Aggregate_Info(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_dynamic_flag")
 def Get_Aggr_Dynamic_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5487,6 +5795,7 @@ def Set_Aggr_Dynamic_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_min_length")
 def Get_Aggr_Min_Length(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5499,6 +5808,7 @@ def Set_Aggr_Min_Length(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_low_limit")
 def Get_Aggr_Low_Limit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5511,6 +5821,7 @@ def Set_Aggr_Low_Limit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_high_limit")
 def Get_Aggr_High_Limit(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5523,6 +5834,7 @@ def Set_Aggr_High_Limit(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_others_flag")
 def Get_Aggr_Others_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5535,6 +5847,7 @@ def Set_Aggr_Others_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggr_named_flag")
 def Get_Aggr_Named_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5547,6 +5860,7 @@ def Set_Aggr_Named_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_aggregate_expand_flag")
 def Get_Aggregate_Expand_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5559,6 +5873,7 @@ def Set_Aggregate_Expand_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_association_choices_chain")
 def Get_Association_Choices_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5571,6 +5886,7 @@ def Set_Association_Choices_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_case_statement_alternative_chain")
 def Get_Case_Statement_Alternative_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5583,6 +5899,7 @@ def Set_Case_Statement_Alternative_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_choice_staticness")
 def Get_Choice_Staticness(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5595,6 +5912,7 @@ def Set_Choice_Staticness(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_procedure_call")
 def Get_Procedure_Call(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5607,6 +5925,7 @@ def Set_Procedure_Call(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_implementation")
 def Get_Implementation(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5619,6 +5938,7 @@ def Set_Implementation(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_parameter_association_chain")
 def Get_Parameter_Association_Chain(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5631,6 +5951,7 @@ def Set_Parameter_Association_Chain(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_method_object")
 def Get_Method_Object(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5643,6 +5964,7 @@ def Set_Method_Object(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subtype_type_mark")
 def Get_Subtype_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5655,6 +5977,7 @@ def Set_Subtype_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_subnature_nature_mark")
 def Get_Subnature_Nature_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5667,6 +5990,7 @@ def Set_Subnature_Nature_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_conversion_subtype")
 def Get_Type_Conversion_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5679,6 +6003,7 @@ def Set_Type_Conversion_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_mark")
 def Get_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5691,6 +6016,7 @@ def Set_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_file_type_mark")
 def Get_File_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5703,6 +6029,7 @@ def Set_File_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_return_type_mark")
 def Get_Return_Type_Mark(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5715,6 +6042,7 @@ def Set_Return_Type_Mark(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_disconnect_flag")
 def Get_Has_Disconnect_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5727,6 +6055,7 @@ def Set_Has_Disconnect_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_active_flag")
 def Get_Has_Active_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5739,6 +6068,7 @@ def Set_Has_Active_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_is_within_flag")
 def Get_Is_Within_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5751,6 +6081,7 @@ def Set_Is_Within_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_type_marks_list")
 def Get_Type_Marks_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5763,6 +6094,7 @@ def Set_Type_Marks_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_implicit_alias_flag")
 def Get_Implicit_Alias_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5775,6 +6107,7 @@ def Set_Implicit_Alias_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_alias_signature")
 def Get_Alias_Signature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5787,6 +6120,7 @@ def Set_Alias_Signature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_attribute_signature")
 def Get_Attribute_Signature(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5799,6 +6133,7 @@ def Set_Attribute_Signature(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_overload_list")
 def Get_Overload_List(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5811,6 +6146,7 @@ def Set_Overload_List(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simple_name_identifier")
 def Get_Simple_Name_Identifier(obj: Iir) -> NameId:
     """"""
+    return 0
 
 
 @export
@@ -5823,6 +6159,7 @@ def Set_Simple_Name_Identifier(obj: Iir, value: NameId) -> None:
 @BindToLibGHDL("vhdl__nodes__get_simple_name_subtype")
 def Get_Simple_Name_Subtype(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5835,6 +6172,7 @@ def Set_Simple_Name_Subtype(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_protected_type_body")
 def Get_Protected_Type_Body(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5847,6 +6185,7 @@ def Set_Protected_Type_Body(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_protected_type_declaration")
 def Get_Protected_Type_Declaration(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -5859,6 +6198,7 @@ def Set_Protected_Type_Declaration(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_use_flag")
 def Get_Use_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5871,6 +6211,7 @@ def Set_Use_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_end_has_reserved_id")
 def Get_End_Has_Reserved_Id(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5883,6 +6224,7 @@ def Set_End_Has_Reserved_Id(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_end_has_identifier")
 def Get_End_Has_Identifier(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5895,6 +6237,7 @@ def Set_End_Has_Identifier(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_end_has_postponed")
 def Get_End_Has_Postponed(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5907,6 +6250,7 @@ def Set_End_Has_Postponed(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_label")
 def Get_Has_Label(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5919,6 +6263,7 @@ def Set_Has_Label(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_begin")
 def Get_Has_Begin(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5931,6 +6276,7 @@ def Set_Has_Begin(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_end")
 def Get_Has_End(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5943,6 +6289,7 @@ def Set_Has_End(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_is")
 def Get_Has_Is(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5955,6 +6302,7 @@ def Set_Has_Is(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_pure")
 def Get_Has_Pure(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5967,6 +6315,7 @@ def Set_Has_Pure(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_body")
 def Get_Has_Body(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5979,6 +6328,7 @@ def Set_Has_Body(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_parameter")
 def Get_Has_Parameter(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -5991,6 +6341,7 @@ def Set_Has_Parameter(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_component")
 def Get_Has_Component(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6003,6 +6354,7 @@ def Set_Has_Component(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_identifier_list")
 def Get_Has_Identifier_List(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6015,6 +6367,7 @@ def Set_Has_Identifier_List(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_mode")
 def Get_Has_Mode(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6027,6 +6380,7 @@ def Set_Has_Mode(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_class")
 def Get_Has_Class(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6039,6 +6393,7 @@ def Set_Has_Class(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_has_delay_mechanism")
 def Get_Has_Delay_Mechanism(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6051,6 +6406,7 @@ def Set_Has_Delay_Mechanism(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_suspend_flag")
 def Get_Suspend_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6063,6 +6419,7 @@ def Set_Suspend_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_is_ref")
 def Get_Is_Ref(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6075,6 +6432,7 @@ def Set_Is_Ref(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_is_forward_ref")
 def Get_Is_Forward_Ref(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6087,6 +6445,7 @@ def Set_Is_Forward_Ref(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_property")
 def Get_Psl_Property(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6099,6 +6458,7 @@ def Set_Psl_Property(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_sequence")
 def Get_Psl_Sequence(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6111,6 +6471,7 @@ def Set_Psl_Sequence(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_declaration")
 def Get_Psl_Declaration(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6123,6 +6484,7 @@ def Set_Psl_Declaration(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_expression")
 def Get_Psl_Expression(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6135,6 +6497,7 @@ def Set_Psl_Expression(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_boolean")
 def Get_Psl_Boolean(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6147,6 +6510,7 @@ def Set_Psl_Boolean(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_clock")
 def Get_PSL_Clock(obj: Iir) -> PSLNode:
     """"""
+    return 0
 
 
 @export
@@ -6159,6 +6523,7 @@ def Set_PSL_Clock(obj: Iir, value: PSLNode) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_nfa")
 def Get_PSL_NFA(obj: Iir) -> PSLNFA:
     """"""
+    return 0
 
 
 @export
@@ -6171,6 +6536,7 @@ def Set_PSL_NFA(obj: Iir, value: PSLNFA) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_nbr_states")
 def Get_PSL_Nbr_States(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
@@ -6183,6 +6549,7 @@ def Set_PSL_Nbr_States(obj: Iir, value: Int32) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_clock_sensitivity")
 def Get_PSL_Clock_Sensitivity(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -6195,6 +6562,7 @@ def Set_PSL_Clock_Sensitivity(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_psl_eos_flag")
 def Get_PSL_EOS_Flag(obj: Iir) -> Boolean:
     """"""
+    return 0
 
 
 @export
@@ -6207,6 +6575,7 @@ def Set_PSL_EOS_Flag(obj: Iir, value: Boolean) -> None:
 @BindToLibGHDL("vhdl__nodes__get_count_expression")
 def Get_Count_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -6219,6 +6588,7 @@ def Set_Count_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_clock_expression")
 def Get_Clock_Expression(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -6231,6 +6601,7 @@ def Set_Clock_Expression(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_default_clock")
 def Get_Default_Clock(obj: Iir) -> Iir:
     """"""
+    return 0
 
 
 @export
@@ -6243,6 +6614,7 @@ def Set_Default_Clock(obj: Iir, value: Iir) -> None:
 @BindToLibGHDL("vhdl__nodes__get_foreign_node")
 def Get_Foreign_Node(obj: Iir) -> Int32:
     """"""
+    return 0
 
 
 @export
diff --git a/pyGHDL/libghdl/vhdl/nodes_meta.py b/pyGHDL/libghdl/vhdl/nodes_meta.py
index 0ad2b247e..c7ba7c5dd 100644
--- a/pyGHDL/libghdl/vhdl/nodes_meta.py
+++ b/pyGHDL/libghdl/vhdl/nodes_meta.py
@@ -25,6 +25,7 @@ def get_fields_first(K: IirKind) -> int:
 
     :param K: Node to get first array index from.
     """
+    return 0
 
 
 @export
@@ -41,12 +42,14 @@ def get_fields_last(K: IirKind) -> int:
 
     :param K: Node to get last array index from.
     """
+    return 0
 
 
 @export
 @BindToLibGHDL("vhdl__nodes_meta__get_field_by_index")
 def get_field_by_index(K: IirKind) -> int:
     """"""
+    return 0
 
 
 @export
diff --git a/pyGHDL/libghdl/vhdl/nodes_utils.py b/pyGHDL/libghdl/vhdl/nodes_utils.py
index 7cecb6825..31d495d85 100644
--- a/pyGHDL/libghdl/vhdl/nodes_utils.py
+++ b/pyGHDL/libghdl/vhdl/nodes_utils.py
@@ -48,6 +48,7 @@ def Strip_Denoting_Name(Name: Iir) -> Iir:
     :param Name: Simple or an expanded name.
     :return:     Denoted declaration.
     """
+    return 0
 
 
 @export
@@ -60,6 +61,7 @@ def Get_Entity(Decl: Iir) -> Iir:
     :param Decl: Declaration
     :return:     Entity
     """
+    return 0
 
 
 @export
@@ -73,6 +75,7 @@ def Is_Second_Subprogram_Specification(Spec: Iir) -> bool:
     :param Spec: Specification
     :return:     ``True`` if subprogram specification and previously declared subprogram body match
     """
+    return False
 
 
 @export
@@ -87,6 +90,7 @@ def Get_Entity_From_Entity_Aspect(Aspect: Iir) -> Iir:
     :param Aspect: Aspect
     :return:       Entity
     """
+    return 0
 
 
 @export
@@ -99,3 +103,4 @@ def Get_Interface_Of_Formal(Formal: Iir) -> Iir:
     :param Formal: The formal.
     :return:       The corresponding interface.
     """
+    return 0
diff --git a/pyGHDL/libghdl/vhdl/parse.py b/pyGHDL/libghdl/vhdl/parse.py
index c3135961f..a61cdfef7 100644
--- a/pyGHDL/libghdl/vhdl/parse.py
+++ b/pyGHDL/libghdl/vhdl/parse.py
@@ -57,3 +57,4 @@ def Parse_Design_File() -> Iir:
 
     :return: Return :obj:`~pyGHDL.libghdl.vhdl.nodes.Null_Iir` in case of error. Type: ``Iir_Design_File``
     """
+    return 0
diff --git a/pyGHDL/libghdl/vhdl/scanner.py b/pyGHDL/libghdl/vhdl/scanner.py
index 15d41e9a9..f9db890a0 100644
--- a/pyGHDL/libghdl/vhdl/scanner.py
+++ b/pyGHDL/libghdl/vhdl/scanner.py
@@ -81,6 +81,7 @@ def Get_Current_Line() -> int:
 
     :return: Current token's line.
     """
+    return 0
 
 
 @export
@@ -91,6 +92,7 @@ def Get_Token_Offset() -> int:
 
     :return: Current token's offset.
     """
+    return 0
 
 
 @export
@@ -101,6 +103,7 @@ def Get_Token_Position():
 
     :return: Current token's position. Type: ``Source_Ptr``
     """
+    return 0
 
 
 @export
@@ -111,6 +114,7 @@ def Get_Position():
 
     :return: Current position. Type: ``Source_Ptr``
     """
+    return 0
 
 
 @export
@@ -123,3 +127,4 @@ def Current_Identifier() -> NameId:
 
     :return: NameId of the current token.
     """
+    return 0
diff --git a/pyGHDL/libghdl/vhdl/sem_lib.py b/pyGHDL/libghdl/vhdl/sem_lib.py
index c281a299c..0126c1ef5 100644
--- a/pyGHDL/libghdl/vhdl/sem_lib.py
+++ b/pyGHDL/libghdl/vhdl/sem_lib.py
@@ -47,6 +47,7 @@ def Load_File(File: SourceFileEntry) -> Iir_Design_File:
     :param File: File to analyse.
     :return:     Return :attr:`~pyGHDL.libghdl.vhdl.nodes.Null_Iir` in case of parse error. Type: ``Iir_Design_File``
     """
+    return 0
 
 
 @export
diff --git a/pyGHDL/lsp/requirements.txt b/pyGHDL/lsp/requirements.txt
new file mode 100644
index 000000000..ae04e54bc
--- /dev/null
+++ b/pyGHDL/lsp/requirements.txt
@@ -0,0 +1 @@
+-r ../libghdl/requirements.txt
diff --git a/pyGHDL/requirements.txt b/pyGHDL/requirements.txt
index 974fef2ed..0efc39c23 100644
--- a/pyGHDL/requirements.txt
+++ b/pyGHDL/requirements.txt
@@ -1,3 +1,4 @@
-pydecor>=2.0.1
-pyVHDLModel==0.10.4
-#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel
+-r libghdl/requirements.txt
+-r dom/requirements.txt
+-r lsp/requirements.txt
+-r cli/requirements.txt
diff --git a/scripts/pnodespy.py b/scripts/pnodespy.py
index 1f016a82d..f1f637ea7 100755
--- a/scripts/pnodespy.py
+++ b/scripts/pnodespy.py
@@ -66,11 +66,13 @@ def do_iirs_subprg():
         @BindToLibGHDL("{classname}__get_kind")
         def Get_Kind(node: Iir) -> IirKind:
             \"\"\"Get node kind.\"\"\"
+            return 0
 
         @export
         @BindToLibGHDL("{classname}__get_location")
         def Get_Location(node: Iir) -> LocationType:
             \"\"\"\"\"\"
+            return 0
         """).format(libname=libname, classname=classname)
     )
     for k in pnodes.funcs:
@@ -85,6 +87,7 @@ def do_iirs_subprg():
             @BindToLibGHDL("{classname}__get_{kname_lower}")
             def Get_{kname}(obj: Iir) -> {rtype}:
                 \"\"\"\"\"\"
+                return 0
             @export
             @BindToLibGHDL("{classname}__set_{kname_lower}")
             def Set_{kname}(obj: Iir, value: {rtype}) -> None:
@@ -259,6 +262,7 @@ def do_libghdl_meta():
 
             :param K: Node to get first array index from.
             \"\"\"
+            return 0
 
 
         @export
@@ -275,11 +279,13 @@ def do_libghdl_meta():
 
             :param K: Node to get last array index from.
             \"\"\"
+            return 0
 
         @export
         @BindToLibGHDL("vhdl__nodes_meta__get_field_by_index")
         def get_field_by_index(K: IirKind) -> int:
             \"\"\"\"\"\"
+            return 0
 
         @export
         def get_field_type(*args):
diff --git a/setup.py b/setup.py
index 6b816f24b..c8372146b 100644
--- a/setup.py
+++ b/setup.py
@@ -119,7 +119,7 @@ setuptools_setup(
     entry_points={
         "console_scripts": [
             "ghdl-ls = pyGHDL.cli.lsp:main",
-            "ghdl-dom = pyGHDL.cli.DOM:main",
+            "ghdl-dom = pyGHDL.cli.dom:main",
         ]
     },
     keywords="Python3 VHDL Parser Compiler Simulator GHDL",
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index a017b9f46..eae346375 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -5,12 +5,14 @@ use     ieee.numeric_std.all;
 entity entity_1 is
 	generic (
 		FREQ : real     := 100.0;
-		BITS : positive := 8
+		BITS : positive := 8.5 ns;
+		type Typ
 	);
 	port (
-	  Clock: in  std_logic;
+	  Clock: in  std_logic := 5 ns;
 	  Reset: in  std_logic := '0';
-	  Q:     out std_logic_vector(BITS - 1 downto 0)
+	  D:     inout bit_vector(clock'range);
+	  Q:     out std_logic_vector(BITS'left - 1 downto Re.set)
 	);
 
 	constant fire : boolean := True;
@@ -20,6 +22,7 @@ end entity entity_1;
 
 architecture behav of entity_1 is
 	constant MAX : positive := -25;
+
 	signal rst : std_logic := foo('U');
 	signal vec : bit_vector(pack(3 to 2).signaal'range'value);
 	signal copy : input'subtype;
@@ -74,6 +77,13 @@ architecture behav of entity_1 is
 	attribute att : boolean;
 
 	alias bar is boolean;
+
+	disconnect address_bus : resolved_word after 3 ns;
+	disconnect others : resolved_word after 2 ns;
+
+	default clock is rising_edge(clk);
+	package inner_pack is
+	end package;
 begin
 	process(Clock)
 	begin
@@ -94,18 +104,28 @@ package package_1 is
 
 	use lib.pack.all;
 
-	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3;
-	attribute fixed of ghdl : constant is true;
+  type cell;
+
+	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10, others => 10, 2.3);
+	attribute fixed of ghdl, gtkwave [x, y] : constant is true;
 
 	component comp is
 		port (
 			clk : std
 		);
 	end component;
+
+	constant Pointer_1 : List := new List(1 to 1);
+	constant Pointer_2 : List := new List'(1 => 0);
+	signal init : std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0);
+	constant fid : real := +val;
+	constant ceq11 : std_logic := '1' ?= '1';
+	type rt321 is range t3'reverse_range;
+	type rt321 is range t3'reverse_range(1);
 end package;
 
 package body package_1 is
-	constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5;
+	constant ghdl : float := 1.5;
 
 	type CAPACITY is range 0 to 1E5	units
 		pF;
@@ -115,3 +135,7 @@ package body package_1 is
 		F = 1000 mF;
 	end units;
 end package body;
+
+vunit vu (component_1) {
+
+}
diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py
index 4de36a2b2..113e541ac 100644
--- a/testsuite/pyunit/dom/Expressions.py
+++ b/testsuite/pyunit/dom/Expressions.py
@@ -87,9 +87,9 @@ class Expressions(TestCase):
         default: Expression = self.parse(filename, constantDeclartion)
 
         # Start checks
-        self.assertTrue(isinstance(default, InverseExpression))
-        self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
-        self.assertTrue(default.Operand.SymbolName == "true")
+        self.assertIsInstance(default, InverseExpression)
+        self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
+        self.assertEqual("true", str(default.Operand.SymbolName))
 
     # def test_AbsExpression(self):
     #     filename: Path = self._root / "{className}_{funcName}.vhdl".format(
@@ -103,8 +103,8 @@ class Expressions(TestCase):
     #     default: Expression = self.parse(filename, constantDeclartion)
     #
     #     # Start checks
-    #     self.assertTrue(isinstance(default, AbsoluteExpression))
-    #     self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
+    #     self.assertIsInstance(default, AbsoluteExpression)
+    #     self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
     #     self.assertTrue(default.Operand.SymbolName == "-3")
 
     # def test_Aggregare(self):
@@ -130,6 +130,6 @@ class Expressions(TestCase):
     #     package: Package = design.Documents[0].Packages[0]
     #     item: Constant = package.DeclaredItems[0]
     #     default: Expression = item.DefaultExpression
-    #     self.assertTrue(isinstance(default, InverseExpression))
-    #     self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
+    #     self.assertIsInstance(default, InverseExpression)
+    #     self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
     #     self.assertTrue(default.Operand.SymbolName == "true")
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index a69481ef4..418a1b76d 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -34,6 +34,10 @@ from pathlib import Path
 from textwrap import dedent
 from unittest import TestCase
 
+from pyVHDLModel.VHDLModel import Expression
+
+from pyGHDL.dom.DesignUnit import Package
+
 from pyGHDL.dom.NonStandard import Design, Document
 from pyGHDL.dom.Object import Constant
 from pyGHDL.dom.Literal import IntegerLiteral
@@ -47,39 +51,38 @@ if __name__ == "__main__":
 
 class Literals(TestCase):
     _root = Path(__file__).resolve().parent.parent
-
-    def test_IntegerLiteral(self):
-        self._filename: Path = self._root / "{className}.vhdl".format(
-            className=self.__class__.__name__
-        )
-
-        sourceCode = dedent(
+    _design = Design()
+    _packageTemplate = dedent(
             """\
             package package_1 is
-              constant c0 : integer := 0;
-              constant c1 : integer := 1;
-              constant c2 : integer := 1024;
-              constant c3 : integer := 1048576;
+              {code}
             end package;
             """
         )
-        expected = (0, 1, 1024, 1048576)
 
-        with self._filename.open(mode="w", encoding="utf-8") as file:
-            file.write(sourceCode)
+    def parse(self, filename: Path, code: str) -> Expression:
+        sourceCode = self._packageTemplate.format(code=code)
+
+        document = Document(filename, sourceCode)
+        self._design.Documents.append(document)
+
+        # Traverse already to default value expression
+        package: Package = document.Packages[0]
+        item: Constant = package.DeclaredItems[0]
+        default: Expression = item.DefaultExpression
+
+        return default
+
+    def test_IntegerLiteral(self):
+        _filename: Path = self._root / "{className}.vhdl".format(
+            className=self.__class__.__name__
+        )
+
+        constantDeclartion = "constant c0 : integer := 0;"
+        expected = (0, 1, 1024, 1048576)
 
-        design = Design()
-        document = Document(self._filename)
-        design.Documents.append(document)
+        # Parse in-memory
+        default: Expression = self.parse(_filename, constantDeclartion)
 
-        self.assertEqual(len(design.Documents[0].Packages), 1)
-        package = design.Documents[0].Packages[0]
-        self.assertTrue(package.Name == "package_1")
-        self.assertEqual(len(package.DeclaredItems), len(expected))
-        for i in range(len(expected)):
-            item: Constant = package.DeclaredItems[i]
-            self.assertTrue(isinstance(item, Constant))
-            self.assertTrue(item.Name == "c{}".format(i))
-            self.assertTrue(str(item.SubType.SymbolName) == "integer")
-            self.assertTrue(isinstance(item.DefaultExpression, IntegerLiteral))
-            self.assertTrue(item.DefaultExpression.Value == expected[i])
+        self.assertIsInstance(default, IntegerLiteral)
+        self.assertEqual(expected[0], default.Value)
diff --git a/testsuite/pyunit/dom/Sanity.py b/testsuite/pyunit/dom/Sanity.py
index b0177f8b3..adf838646 100644
--- a/testsuite/pyunit/dom/Sanity.py
+++ b/testsuite/pyunit/dom/Sanity.py
@@ -49,10 +49,9 @@ _GHDL_ROOT = _TESTSUITE_ROOT.parent
 
 design = Design()
 
-@mark.xfail
 @mark.parametrize("file", [str(f.relative_to(_TESTSUITE_ROOT)) for f in _TESTSUITE_ROOT.glob("sanity/**/*.vhdl")])
 def test_AllVHDLSources(file):
-    check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/DOM.py", file], stderr=STDOUT)
+    check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/dom.py", "pretty", "-f", file], stderr=STDOUT)
 
 #    document = Document(Path(file))
 #    design.Documents.append(document)
diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/SimpleEntity.py
index 9ee55508c..68f702410 100644
--- a/testsuite/pyunit/dom/SimpleEntity.py
+++ b/testsuite/pyunit/dom/SimpleEntity.py
@@ -59,20 +59,20 @@ class SimpleEntity(TestCase):
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertTrue(len(design.Documents) == 1)
+        self.assertEqual(1, len(design.Documents))
 
     def test_Entity(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Entities), 1)
-        self.assertTrue(design.Documents[0].Entities[0].Name == "entity_1")
+        self.assertEqual(1, len(design.Documents[0].Entities))
+        self.assertEqual("entity_1", design.Documents[0].Entities[0].Identifier)
 
     def test_Architecture(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Architectures), 1)
-        self.assertTrue(design.Documents[0].Architectures[0].Name == "behav")
+        self.assertEqual(1, len(design.Documents[0].Architectures))
+        self.assertEqual("behav", design.Documents[0].Architectures[0].Identifier)
diff --git a/testsuite/pyunit/dom/SimplePackage.py b/testsuite/pyunit/dom/SimplePackage.py
index 399a676b4..9c62db4a1 100644
--- a/testsuite/pyunit/dom/SimplePackage.py
+++ b/testsuite/pyunit/dom/SimplePackage.py
@@ -51,13 +51,13 @@ class SimplePackage(TestCase):
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Packages), 1)
-        self.assertTrue(design.Documents[0].Packages[0].Name == "pack_1")
+        self.assertEqual(1, len(design.Documents[0].Packages))
+        self.assertEqual("pack_1", design.Documents[0].Packages[0].Identifier)
 
     def test_PackageBody(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].PackageBodies), 1)
-        self.assertTrue(design.Documents[0].PackageBodies[0].Name == "pack_1")
+        self.assertEqual(1, len(design.Documents[0].PackageBodies))
+        self.assertEqual("pack_1", design.Documents[0].PackageBodies[0].Identifier)