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| author | Tristan Gingold <tgingold@free.fr> | 2016-03-18 05:25:28 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2016-03-18 05:25:28 +0100 |
| commit | 1c8872240feffcc2324a1b46a055d5afcfa3e2bb (patch) | |
| tree | ae6835c95ca84b7cbf0b1aab8e8e0cefddee98f9 | |
| parent | 73a6ed8e5e982034920d8c9fe95faddefdcffa43 (diff) | |
| download | ghdl-1c8872240feffcc2324a1b46a055d5afcfa3e2bb.tar.gz ghdl-1c8872240feffcc2324a1b46a055d5afcfa3e2bb.tar.bz2 ghdl-1c8872240feffcc2324a1b46a055d5afcfa3e2bb.zip | |
Document --psl-report
| -rw-r--r-- | doc/Simulation_and_runtime.rst | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/doc/Simulation_and_runtime.rst b/doc/Simulation_and_runtime.rst index 329dca8d8..9a925da4b 100644 --- a/doc/Simulation_and_runtime.rst +++ b/doc/Simulation_and_runtime.rst @@ -187,6 +187,13 @@ all options available, including the debugging one. Contrary to VCD files, any VHDL type can be dumped into a GHW file. +.. option:: --psl-report=<FILENAME> + + Write a report for PSL assertions and coverage at the end of + simulation. The file is written using the JSON format, but still + being human readable. + + .. option:: --sdf=<PATH>=<FILENAME> Do VITAL annotation on `PATH` with SDF file :file:`FILENAME`. |