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author | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:32:13 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:32:13 +0200 |
commit | 170d114587a84c58c18c33f9f564b508f4d82544 (patch) | |
tree | b7c6f93413b839e93eac866c9d39e489cea07556 | |
parent | cea222fe918c82de7b8ce75f3bd42c011677e06d (diff) | |
download | ghdl-170d114587a84c58c18c33f9f564b508f4d82544.tar.gz ghdl-170d114587a84c58c18c33f9f564b508f4d82544.tar.bz2 ghdl-170d114587a84c58c18c33f9f564b508f4d82544.zip |
testsuite/synth: add testcase for previous commit.
-rw-r--r-- | testsuite/synth/synth58/function_test.vhdl | 31 | ||||
-rw-r--r-- | testsuite/synth/synth58/repro1.vhdl | 26 | ||||
-rwxr-xr-x | testsuite/synth/synth58/testsuite.sh | 13 |
3 files changed, 70 insertions, 0 deletions
diff --git a/testsuite/synth/synth58/function_test.vhdl b/testsuite/synth/synth58/function_test.vhdl new file mode 100644 index 000000000..a612fea10 --- /dev/null +++ b/testsuite/synth/synth58/function_test.vhdl @@ -0,0 +1,31 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity function_test is + generic ( + g : std_logic := '1' + ); + port ( + i : in std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0) + ); +end function_test; + +architecture rtl of function_test is + + function assign_value(value : in std_logic_vector(7 downto 0); + invert : in std_logic) + return std_logic_vector is + variable slv_out : std_logic_vector(7 downto 0); + begin + if invert = '0' then + slv_out := value; + elsif invert = '1' then + slv_out := not value; + end if; + return slv_out; + end; + +begin + o <= assign_value(i, g); +end rtl; diff --git a/testsuite/synth/synth58/repro1.vhdl b/testsuite/synth/synth58/repro1.vhdl new file mode 100644 index 000000000..391017cf3 --- /dev/null +++ b/testsuite/synth/synth58/repro1.vhdl @@ -0,0 +1,26 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity repro1 is + generic ( + g : std_logic := '1' + ); + port ( + i : in std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0) + ); +end repro1; + +architecture rtl of repro1 is +begin + process (i) + variable slv_out : std_logic_vector(7 downto 0); + begin + if g = '0' then + slv_out := i; + elsif g = '1' then + slv_out := not i; + end if; + o <= slv_out; + end process; +end rtl; diff --git a/testsuite/synth/synth58/testsuite.sh b/testsuite/synth/synth58/testsuite.sh new file mode 100755 index 000000000..041a83a72 --- /dev/null +++ b/testsuite/synth/synth58/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +synth function_test.vhdl -e > syn_function_test.vhdl +analyze syn_function_test.vhdl + +synth repro1.vhdl -e > syn_repro1.vhdl +analyze syn_repro1.vhdl + +clean + +echo "Test successful" |