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authorTristan Gingold <tgingold@free.fr>2019-08-16 12:13:54 +0200
committerTristan Gingold <tgingold@free.fr>2019-08-16 12:13:54 +0200
commitbd29c849be41a8d15a6f6231a7664e8a7841a1b2 (patch)
treeba07c740df5df11f327da6df132adeea540d1574 /.travis.yml
parentfb72fae0a907684c00bb19950ad9a20c21732f77 (diff)
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synth: handle integers for displaying vhdl ports.
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