test_or.vhdl « issue11 « issues « testsuite - iCE40/ghdl-yosys-plugin - clone of https://github.com/ghdl/ghdl-yosys-plugin

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library ieee;
use ieee.std_logic_1164.all;

entity test_or is port (
    sel0, sel1: in std_logic;
    c: out std_logic);
end test_or;

architecture synth of test_or is
begin

    c <= sel1 or sel0;

end synth;