blob: 522ce8623c9f84e724e375adcd1bea7397b64bd9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
library ieee;
use ieee.std_logic_1164.all;
entity psl_p_plus is
generic(
DATA_BITS: natural := 8
);
port(
clk_in: in std_logic;
a_in: in std_logic;
b_in: in std_logic;
c_in: in std_logic
);
end;
architecture psl of psl_p_plus is
begin
default clock is rising_edge(clk_in);
p_plus_psl: assert {a_in[+]; b_in} |-> {c_in};
end;
|
