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-rw-r--r--library/ecp5u/components.vhdl8486
1 files changed, 4243 insertions, 4243 deletions
diff --git a/library/ecp5u/components.vhdl b/library/ecp5u/components.vhdl
index 3f1f428..74b667c 100644
--- a/library/ecp5u/components.vhdl
+++ b/library/ecp5u/components.vhdl
@@ -1,5 +1,5 @@
--- This module is generated by vhdl_comp.xsl
--- (2016-2019, hackfin@section5.ch)
+-- This module is generated by vhdl_pkg.xsl
+-- (2016-2020, hackfin@section5.ch)
--
-- Changes may be void.
--
@@ -12,1478 +12,1478 @@ library ieee;
package components is
-component ccu2c is
+component CCU2C is
generic (
- inject1_0 : string := "YES";
- inject1_1 : string := "YES";
- init0 : std_logic_vector := "0000000000000000";
- init1 : std_logic_vector := "0000000000000000" );
+ INJECT1_0 : string := "YES";
+ INJECT1_1 : string := "YES";
+ INIT0 : std_logic_vector := "0000000000000000";
+ INIT1 : std_logic_vector := "0000000000000000" );
port (
- a0 : in std_ulogic;
- a1 : in std_ulogic;
- b0 : in std_ulogic;
- b1 : in std_ulogic;
- c0 : in std_ulogic;
- c1 : in std_ulogic;
- d0 : in std_ulogic;
- d1 : in std_ulogic;
- cin : in std_ulogic;
- s0 : out std_ulogic;
- s1 : out std_ulogic;
- cout : out std_ulogic );
+ A0 : in std_ulogic;
+ A1 : in std_ulogic;
+ B0 : in std_ulogic;
+ B1 : in std_ulogic;
+ C0 : in std_ulogic;
+ C1 : in std_ulogic;
+ D0 : in std_ulogic;
+ D1 : in std_ulogic;
+ CIN : in std_ulogic;
+ S0 : out std_ulogic;
+ S1 : out std_ulogic;
+ COUT : out std_ulogic );
end component;
-component and2 is
+component AND2 is
port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
end component;
-component and3 is
+component AND3 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
end component;
-component and4 is
+component AND4 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
end component;
-component and5 is
+component AND5 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
end component;
-component fd1p3ax is
+component FD1P3AX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ Q : out std_logic );
end component;
-component fd1p3ay is
+component FD1P3AY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ Q : out std_logic );
end component;
-component fd1p3bx is
+component FD1P3BX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1p3dx is
+component FD1P3DX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1p3ix is
+component FD1P3IX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1p3jx is
+component FD1P3JX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3ax is
+component FD1S3AX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3ay is
+component FD1S3AY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3bx is
+component FD1S3BX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3dx is
+component FD1S3DX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3ix is
+component FD1S3IX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fd1s3jx is
+component FD1S3JX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- ck : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ CK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3az is
+component FL1P3AZ is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3ay is
+component FL1P3AY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3bx is
+component FL1P3BX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3dx is
+component FL1P3DX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3iy is
+component FL1P3IY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1p3jy is
+component FL1P3JY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- sp : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1s3ax is
+component FL1S3AX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ Q : out std_logic );
end component;
-component fl1s3ay is
+component FL1S3AY is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d0 : in std_logic;
- d1 : in std_logic;
- ck : in std_logic;
- sd : in std_logic;
- q : out std_logic );
+ D0 : in std_logic;
+ D1 : in std_logic;
+ CK : in std_logic;
+ SD : in std_logic;
+ Q : out std_logic );
end component;
-component gsr is
+component GSR is
port (
- gsr : in std_logic );
+ GSR : in std_logic );
end component;
-component sgsr is
+component SGSR is
port (
- gsr : in std_logic;
- clk : in std_logic );
+ GSR : in std_logic;
+ CLK : in std_logic );
end component;
-component inv is
+component INV is
port (
- a : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ Z : out std_logic );
end component;
-component ifs1p3bx is
+component IFS1P3BX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1p3dx is
+component IFS1P3DX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1p3ix is
+component IFS1P3IX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1p3jx is
+component IFS1P3JX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1s1b is
+component IFS1S1B is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1s1d is
+component IFS1S1D is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1s1i is
+component IFS1S1I is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ifs1s1j is
+component IFS1S1J is
generic (
- gsr : string := "ENABLED" );
- port (
- d : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
-end component;
-
-component l6mux21 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- sd : in std_logic;
- z : out std_logic );
-end component;
-
-component mux21 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- sd : in std_logic;
- z : out std_logic );
-end component;
-
-component mux41 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- d2 : in std_logic;
- d3 : in std_logic;
- sd1 : in std_logic;
- sd2 : in std_logic;
- z : out std_logic );
-end component;
-
-component mux81 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- d2 : in std_logic;
- d3 : in std_logic;
- d4 : in std_logic;
- d5 : in std_logic;
- d6 : in std_logic;
- d7 : in std_logic;
- sd1 : in std_logic;
- sd2 : in std_logic;
- sd3 : in std_logic;
- z : out std_logic );
-end component;
-
-component mux161 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- d2 : in std_logic;
- d3 : in std_logic;
- d4 : in std_logic;
- d5 : in std_logic;
- d6 : in std_logic;
- d7 : in std_logic;
- d8 : in std_logic;
- d9 : in std_logic;
- d10 : in std_logic;
- d11 : in std_logic;
- d12 : in std_logic;
- d13 : in std_logic;
- d14 : in std_logic;
- d15 : in std_logic;
- sd1 : in std_logic;
- sd2 : in std_logic;
- sd3 : in std_logic;
- sd4 : in std_logic;
- z : out std_logic );
-end component;
-
-component mux321 is
- port (
- d0 : in std_logic;
- d1 : in std_logic;
- d2 : in std_logic;
- d3 : in std_logic;
- d4 : in std_logic;
- d5 : in std_logic;
- d6 : in std_logic;
- d7 : in std_logic;
- d8 : in std_logic;
- d9 : in std_logic;
- d10 : in std_logic;
- d11 : in std_logic;
- d12 : in std_logic;
- d13 : in std_logic;
- d14 : in std_logic;
- d15 : in std_logic;
- d16 : in std_logic;
- d17 : in std_logic;
- d18 : in std_logic;
- d19 : in std_logic;
- d20 : in std_logic;
- d21 : in std_logic;
- d22 : in std_logic;
- d23 : in std_logic;
- d24 : in std_logic;
- d25 : in std_logic;
- d26 : in std_logic;
- d27 : in std_logic;
- d28 : in std_logic;
- d29 : in std_logic;
- d30 : in std_logic;
- d31 : in std_logic;
- sd1 : in std_logic;
- sd2 : in std_logic;
- sd3 : in std_logic;
- sd4 : in std_logic;
- sd5 : in std_logic;
- z : out std_logic );
-end component;
-
-component nd2 is
- port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
-end component;
-
-component nd3 is
- port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
-end component;
-
-component nd4 is
- port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
-end component;
-
-component nd5 is
- port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
-end component;
-
-component nr2 is
- port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
-end component;
-
-component nr3 is
- port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
-end component;
-
-component nr4 is
+ GSR : string := "ENABLED" );
+ port (
+ D : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
+end component;
+
+component L6MUX21 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SD : in std_logic;
+ Z : out std_logic );
+end component;
+
+component MUX21 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ SD : in std_logic;
+ Z : out std_logic );
+end component;
+
+component MUX41 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ D2 : in std_logic;
+ D3 : in std_logic;
+ SD1 : in std_logic;
+ SD2 : in std_logic;
+ Z : out std_logic );
+end component;
+
+component MUX81 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ D2 : in std_logic;
+ D3 : in std_logic;
+ D4 : in std_logic;
+ D5 : in std_logic;
+ D6 : in std_logic;
+ D7 : in std_logic;
+ SD1 : in std_logic;
+ SD2 : in std_logic;
+ SD3 : in std_logic;
+ Z : out std_logic );
+end component;
+
+component MUX161 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ D2 : in std_logic;
+ D3 : in std_logic;
+ D4 : in std_logic;
+ D5 : in std_logic;
+ D6 : in std_logic;
+ D7 : in std_logic;
+ D8 : in std_logic;
+ D9 : in std_logic;
+ D10 : in std_logic;
+ D11 : in std_logic;
+ D12 : in std_logic;
+ D13 : in std_logic;
+ D14 : in std_logic;
+ D15 : in std_logic;
+ SD1 : in std_logic;
+ SD2 : in std_logic;
+ SD3 : in std_logic;
+ SD4 : in std_logic;
+ Z : out std_logic );
+end component;
+
+component MUX321 is
+ port (
+ D0 : in std_logic;
+ D1 : in std_logic;
+ D2 : in std_logic;
+ D3 : in std_logic;
+ D4 : in std_logic;
+ D5 : in std_logic;
+ D6 : in std_logic;
+ D7 : in std_logic;
+ D8 : in std_logic;
+ D9 : in std_logic;
+ D10 : in std_logic;
+ D11 : in std_logic;
+ D12 : in std_logic;
+ D13 : in std_logic;
+ D14 : in std_logic;
+ D15 : in std_logic;
+ D16 : in std_logic;
+ D17 : in std_logic;
+ D18 : in std_logic;
+ D19 : in std_logic;
+ D20 : in std_logic;
+ D21 : in std_logic;
+ D22 : in std_logic;
+ D23 : in std_logic;
+ D24 : in std_logic;
+ D25 : in std_logic;
+ D26 : in std_logic;
+ D27 : in std_logic;
+ D28 : in std_logic;
+ D29 : in std_logic;
+ D30 : in std_logic;
+ D31 : in std_logic;
+ SD1 : in std_logic;
+ SD2 : in std_logic;
+ SD3 : in std_logic;
+ SD4 : in std_logic;
+ SD5 : in std_logic;
+ Z : out std_logic );
+end component;
+
+component ND2 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
+end component;
+
+component ND3 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
+end component;
+
+component ND4 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
+end component;
+
+component ND5 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
+end component;
+
+component NR2 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
+end component;
+
+component NR3 is
+ port (
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
+end component;
+
+component NR4 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
end component;
-component nr5 is
+component NR5 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
end component;
-component ofs1p3bx is
+component OFS1P3BX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component ofs1p3dx is
+component OFS1P3DX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ofs1p3ix is
+component OFS1P3IX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- cd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic );
end component;
-component ofs1p3jx is
+component OFS1P3JX is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sp : in std_logic;
- sclk : in std_logic;
- pd : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ SP : in std_logic;
+ SCLK : in std_logic;
+ PD : in std_logic;
+ Q : out std_logic );
end component;
-component or2 is
+component OR2 is
port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
end component;
-component or3 is
+component OR3 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
end component;
-component or4 is
+component OR4 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
end component;
-component or5 is
+component OR5 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
end component;
-component pfumx is
+component PFUMX is
port (
- alut : in std_logic;
- blut : in std_logic;
- c0 : in std_logic;
- z : out std_logic );
+ ALUT : in std_logic;
+ BLUT : in std_logic;
+ C0 : in std_logic;
+ Z : out std_logic );
end component;
-component rom16x1a is
+component ROM16X1A is
generic (
- initval : std_logic_vector := "0000000000000000" );
+ INITVAL : std_logic_vector := "0000000000000000" );
port (
- ad0 : in std_logic;
- ad1 : in std_logic;
- ad2 : in std_logic;
- ad3 : in std_logic;
- do0 : out std_logic );
+ AD0 : in std_logic;
+ AD1 : in std_logic;
+ AD2 : in std_logic;
+ AD3 : in std_logic;
+ DO0 : out std_logic );
end component;
-component rom32x1a is
+component ROM32X1A is
generic (
- initval : std_logic_vector := "00000000000000000000000000000000" );
+ INITVAL : std_logic_vector := "00000000000000000000000000000000" );
port (
- ad0 : in std_logic;
- ad1 : in std_logic;
- ad2 : in std_logic;
- ad3 : in std_logic;
- ad4 : in std_logic;
- do0 : out std_logic );
+ AD0 : in std_logic;
+ AD1 : in std_logic;
+ AD2 : in std_logic;
+ AD3 : in std_logic;
+ AD4 : in std_logic;
+ DO0 : out std_logic );
end component;
-component rom64x1a is
+component ROM64X1A is
generic (
- initval : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000" );
+ INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000" );
port (
- ad0 : in std_logic;
- ad1 : in std_logic;
- ad2 : in std_logic;
- ad3 : in std_logic;
- ad4 : in std_logic;
- ad5 : in std_logic;
- do0 : out std_logic );
+ AD0 : in std_logic;
+ AD1 : in std_logic;
+ AD2 : in std_logic;
+ AD3 : in std_logic;
+ AD4 : in std_logic;
+ AD5 : in std_logic;
+ DO0 : out std_logic );
end component;
-component rom128x1a is
+component ROM128X1A is
generic (
- initval : std_logic_vector := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
+ INITVAL : std_logic_vector := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
port (
- ad0 : in std_logic;
- ad1 : in std_logic;
- ad2 : in std_logic;
- ad3 : in std_logic;
- ad4 : in std_logic;
- ad5 : in std_logic;
- ad6 : in std_logic;
- do0 : out std_logic );
+ AD0 : in std_logic;
+ AD1 : in std_logic;
+ AD2 : in std_logic;
+ AD3 : in std_logic;
+ AD4 : in std_logic;
+ AD5 : in std_logic;
+ AD6 : in std_logic;
+ DO0 : out std_logic );
end component;
-component rom256x1a is
+component ROM256X1A is
generic (
- initval : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
+ INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
port (
- ad0 : in std_logic;
- ad1 : in std_logic;
- ad2 : in std_logic;
- ad3 : in std_logic;
- ad4 : in std_logic;
- ad5 : in std_logic;
- ad6 : in std_logic;
- ad7 : in std_logic;
- do0 : out std_logic );
+ AD0 : in std_logic;
+ AD1 : in std_logic;
+ AD2 : in std_logic;
+ AD3 : in std_logic;
+ AD4 : in std_logic;
+ AD5 : in std_logic;
+ AD6 : in std_logic;
+ AD7 : in std_logic;
+ DO0 : out std_logic );
end component;
-component vhi is
+component VHI is
port (
- z : out std_logic );
+ Z : out std_logic );
end component;
-component vlo is
+component VLO is
port (
- z : out std_logic );
+ Z : out std_logic );
end component;
-component xor2 is
+component XOR2 is
port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
end component;
-component xor3 is
+component XOR3 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
end component;
-component xor4 is
+component XOR4 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
end component;
-component xor5 is
+component XOR5 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
end component;
-component xor11 is
+component XOR11 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- f : in std_logic;
- g : in std_logic;
- h : in std_logic;
- i : in std_logic;
- j : in std_logic;
- k : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ F : in std_logic;
+ G : in std_logic;
+ H : in std_logic;
+ I : in std_logic;
+ J : in std_logic;
+ K : in std_logic;
+ Z : out std_logic );
end component;
-component xor21 is
+component XOR21 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- f : in std_logic;
- g : in std_logic;
- h : in std_logic;
- i : in std_logic;
- j : in std_logic;
- k : in std_logic;
- l : in std_logic;
- m : in std_logic;
- n : in std_logic;
- o : in std_logic;
- p : in std_logic;
- q : in std_logic;
- r : in std_logic;
- s : in std_logic;
- t : in std_logic;
- u : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ F : in std_logic;
+ G : in std_logic;
+ H : in std_logic;
+ I : in std_logic;
+ J : in std_logic;
+ K : in std_logic;
+ L : in std_logic;
+ M : in std_logic;
+ N : in std_logic;
+ O : in std_logic;
+ P : in std_logic;
+ Q : in std_logic;
+ R : in std_logic;
+ S : in std_logic;
+ T : in std_logic;
+ U : in std_logic;
+ Z : out std_logic );
end component;
-component xnor2 is
+component XNOR2 is
port (
- a : in std_logic;
- b : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ Z : out std_logic );
end component;
-component xnor3 is
+component XNOR3 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ Z : out std_logic );
end component;
-component xnor4 is
+component XNOR4 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ Z : out std_logic );
end component;
-component xnor5 is
+component XNOR5 is
port (
- a : in std_logic;
- b : in std_logic;
- c : in std_logic;
- d : in std_logic;
- e : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ E : in std_logic;
+ Z : out std_logic );
end component;
-component ilvds is
+component ILVDS is
port (
- a : in std_logic;
- an : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ AN : in std_logic;
+ Z : out std_logic );
end component;
-component olvds is
+component OLVDS is
port (
- a : in std_logic;
- z : out std_logic;
- zn : out std_logic );
+ A : in std_logic;
+ Z : out std_logic;
+ ZN : out std_logic );
end component;
-component bb is
+component BB is
port (
- b : inout std_logic;
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ B : inout std_logic;
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component bbpd is
+component BBPD is
port (
- b : inout std_logic;
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ B : inout std_logic;
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component bbpu is
+component BBPU is
port (
- b : inout std_logic;
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ B : inout std_logic;
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component ib is
+component IB is
port (
- i : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ O : out std_logic );
end component;
-component ibpd is
+component IBPD is
port (
- i : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ O : out std_logic );
end component;
-component ibpu is
+component IBPU is
port (
- i : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ O : out std_logic );
end component;
-component ob is
+component OB is
port (
- i : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ O : out std_logic );
end component;
-component obco is
+component OBCO is
port (
- i : in std_logic;
- ot : out std_logic;
- oc : out std_logic );
+ I : in std_logic;
+ OT : out std_logic;
+ OC : out std_logic );
end component;
-component obz is
+component OBZ is
port (
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component obzpu is
+component OBZPU is
port (
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component lut4 is
+component LUT4 is
generic (
- init : std_logic_vector := "" );
+ INIT : std_logic_vector := "" );
port (
- a : in std_ulogic;
- b : in std_ulogic;
- c : in std_ulogic;
- d : in std_ulogic;
- z : out std_ulogic );
+ A : in std_ulogic;
+ B : in std_ulogic;
+ C : in std_ulogic;
+ D : in std_ulogic;
+ Z : out std_ulogic );
end component;
-component lut5 is
+component LUT5 is
generic (
- init : std_logic_vector := "" );
+ INIT : std_logic_vector := "" );
port (
- a : in std_ulogic;
- b : in std_ulogic;
- c : in std_ulogic;
- d : in std_ulogic;
- e : in std_ulogic;
- z : out std_ulogic );
+ A : in std_ulogic;
+ B : in std_ulogic;
+ C : in std_ulogic;
+ D : in std_ulogic;
+ E : in std_ulogic;
+ Z : out std_ulogic );
end component;
-component lut6 is
+component LUT6 is
generic (
- init : std_logic_vector := "" );
+ INIT : std_logic_vector := "" );
port (
- a : in std_ulogic;
- b : in std_ulogic;
- c : in std_ulogic;
- d : in std_ulogic;
- e : in std_ulogic;
- f : in std_ulogic;
- z : out std_ulogic );
+ A : in std_ulogic;
+ B : in std_ulogic;
+ C : in std_ulogic;
+ D : in std_ulogic;
+ E : in std_ulogic;
+ F : in std_ulogic;
+ Z : out std_ulogic );
end component;
-component lut7 is
+component LUT7 is
generic (
- init : std_logic_vector := "" );
+ INIT : std_logic_vector := "" );
port (
- a : in std_ulogic;
- b : in std_ulogic;
- c : in std_ulogic;
- d : in std_ulogic;
- e : in std_ulogic;
- f : in std_ulogic;
- g : in std_ulogic;
- z : out std_ulogic );
+ A : in std_ulogic;
+ B : in std_ulogic;
+ C : in std_ulogic;
+ D : in std_ulogic;
+ E : in std_ulogic;
+ F : in std_ulogic;
+ G : in std_ulogic;
+ Z : out std_ulogic );
end component;
-component lut8 is
+component LUT8 is
generic (
- init : std_logic_vector := "" );
+ INIT : std_logic_vector := "" );
port (
- a : in std_ulogic;
- b : in std_ulogic;
- c : in std_ulogic;
- d : in std_ulogic;
- e : in std_ulogic;
- f : in std_ulogic;
- g : in std_ulogic;
- h : in std_ulogic;
- z : out std_ulogic );
+ A : in std_ulogic;
+ B : in std_ulogic;
+ C : in std_ulogic;
+ D : in std_ulogic;
+ E : in std_ulogic;
+ F : in std_ulogic;
+ G : in std_ulogic;
+ H : in std_ulogic;
+ Z : out std_ulogic );
end component;
-component mult9x9c is
+component MULT9X9C is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_pipeline_clk : string := "NONE";
- reg_pipeline_ce : string := "CE0";
- reg_pipeline_rst : string := "RST0";
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- gsr : string := "ENABLED";
- cas_match_reg : string := "FALSE";
- mult_bypass : string := "DISABLED";
- resetmode : string := "SYNC" );
- port (
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- signeda : in std_logic;
- signedb : in std_logic;
- sourcea : in std_logic;
- sourceb : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- roa8 : out std_logic;
- roa7 : out std_logic;
- roa6 : out std_logic;
- roa5 : out std_logic;
- roa4 : out std_logic;
- roa3 : out std_logic;
- roa2 : out std_logic;
- roa1 : out std_logic;
- roa0 : out std_logic;
- rob8 : out std_logic;
- rob7 : out std_logic;
- rob6 : out std_logic;
- rob5 : out std_logic;
- rob4 : out std_logic;
- rob3 : out std_logic;
- rob2 : out std_logic;
- rob1 : out std_logic;
- rob0 : out std_logic;
- p17 : out std_logic;
- p16 : out std_logic;
- p15 : out std_logic;
- p14 : out std_logic;
- p13 : out std_logic;
- p12 : out std_logic;
- p11 : out std_logic;
- p10 : out std_logic;
- p9 : out std_logic;
- p8 : out std_logic;
- p7 : out std_logic;
- p6 : out std_logic;
- p5 : out std_logic;
- p4 : out std_logic;
- p3 : out std_logic;
- p2 : out std_logic;
- p1 : out std_logic;
- p0 : out std_logic;
- signedp : out std_logic );
-end component;
-
-component mult9x9d is
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_PIPELINE_CLK : string := "NONE";
+ REG_PIPELINE_CE : string := "CE0";
+ REG_PIPELINE_RST : string := "RST0";
+ REG_OUTPUT_CLK : string := "NONE";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
+ GSR : string := "ENABLED";
+ CAS_MATCH_REG : string := "FALSE";
+ MULT_BYPASS : string := "DISABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ SIGNEDA : in std_logic;
+ SIGNEDB : in std_logic;
+ SOURCEA : in std_logic;
+ SOURCEB : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ ROA8 : out std_logic;
+ ROA7 : out std_logic;
+ ROA6 : out std_logic;
+ ROA5 : out std_logic;
+ ROA4 : out std_logic;
+ ROA3 : out std_logic;
+ ROA2 : out std_logic;
+ ROA1 : out std_logic;
+ ROA0 : out std_logic;
+ ROB8 : out std_logic;
+ ROB7 : out std_logic;
+ ROB6 : out std_logic;
+ ROB5 : out std_logic;
+ ROB4 : out std_logic;
+ ROB3 : out std_logic;
+ ROB2 : out std_logic;
+ ROB1 : out std_logic;
+ ROB0 : out std_logic;
+ P17 : out std_logic;
+ P16 : out std_logic;
+ P15 : out std_logic;
+ P14 : out std_logic;
+ P13 : out std_logic;
+ P12 : out std_logic;
+ P11 : out std_logic;
+ P10 : out std_logic;
+ P9 : out std_logic;
+ P8 : out std_logic;
+ P7 : out std_logic;
+ P6 : out std_logic;
+ P5 : out std_logic;
+ P4 : out std_logic;
+ P3 : out std_logic;
+ P2 : out std_logic;
+ P1 : out std_logic;
+ P0 : out std_logic;
+ SIGNEDP : out std_logic );
+end component;
+
+component MULT9X9D is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_inputc_clk : string := "NONE";
- reg_inputc_ce : string := "CE0";
- reg_inputc_rst : string := "RST0";
- reg_pipeline_clk : string := "NONE";
- reg_pipeline_ce : string := "CE0";
- reg_pipeline_rst : string := "RST0";
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- highspeed_clk : string := "NONE";
- gsr : string := "ENABLED";
- cas_match_reg : string := "FALSE";
- sourceb_mode : string := "B_SHIFT";
- mult_bypass : string := "DISABLED";
- resetmode : string := "SYNC" );
- port (
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- signeda : in std_logic;
- signedb : in std_logic;
- sourcea : in std_logic;
- sourceb : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- roa8 : out std_logic;
- roa7 : out std_logic;
- roa6 : out std_logic;
- roa5 : out std_logic;
- roa4 : out std_logic;
- roa3 : out std_logic;
- roa2 : out std_logic;
- roa1 : out std_logic;
- roa0 : out std_logic;
- rob8 : out std_logic;
- rob7 : out std_logic;
- rob6 : out std_logic;
- rob5 : out std_logic;
- rob4 : out std_logic;
- rob3 : out std_logic;
- rob2 : out std_logic;
- rob1 : out std_logic;
- rob0 : out std_logic;
- roc8 : out std_logic;
- roc7 : out std_logic;
- roc6 : out std_logic;
- roc5 : out std_logic;
- roc4 : out std_logic;
- roc3 : out std_logic;
- roc2 : out std_logic;
- roc1 : out std_logic;
- roc0 : out std_logic;
- p17 : out std_logic;
- p16 : out std_logic;
- p15 : out std_logic;
- p14 : out std_logic;
- p13 : out std_logic;
- p12 : out std_logic;
- p11 : out std_logic;
- p10 : out std_logic;
- p9 : out std_logic;
- p8 : out std_logic;
- p7 : out std_logic;
- p6 : out std_logic;
- p5 : out std_logic;
- p4 : out std_logic;
- p3 : out std_logic;
- p2 : out std_logic;
- p1 : out std_logic;
- p0 : out std_logic;
- signedp : out std_logic );
-end component;
-
-component mult18x18c is
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_INPUTC_CLK : string := "NONE";
+ REG_INPUTC_CE : string := "CE0";
+ REG_INPUTC_RST : string := "RST0";
+ REG_PIPELINE_CLK : string := "NONE";
+ REG_PIPELINE_CE : string := "CE0";
+ REG_PIPELINE_RST : string := "RST0";
+ REG_OUTPUT_CLK : string := "NONE";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ HIGHSPEED_CLK : string := "NONE";
+ GSR : string := "ENABLED";
+ CAS_MATCH_REG : string := "FALSE";
+ SOURCEB_MODE : string := "B_SHIFT";
+ MULT_BYPASS : string := "DISABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ SIGNEDA : in std_logic;
+ SIGNEDB : in std_logic;
+ SOURCEA : in std_logic;
+ SOURCEB : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ ROA8 : out std_logic;
+ ROA7 : out std_logic;
+ ROA6 : out std_logic;
+ ROA5 : out std_logic;
+ ROA4 : out std_logic;
+ ROA3 : out std_logic;
+ ROA2 : out std_logic;
+ ROA1 : out std_logic;
+ ROA0 : out std_logic;
+ ROB8 : out std_logic;
+ ROB7 : out std_logic;
+ ROB6 : out std_logic;
+ ROB5 : out std_logic;
+ ROB4 : out std_logic;
+ ROB3 : out std_logic;
+ ROB2 : out std_logic;
+ ROB1 : out std_logic;
+ ROB0 : out std_logic;
+ ROC8 : out std_logic;
+ ROC7 : out std_logic;
+ ROC6 : out std_logic;
+ ROC5 : out std_logic;
+ ROC4 : out std_logic;
+ ROC3 : out std_logic;
+ ROC2 : out std_logic;
+ ROC1 : out std_logic;
+ ROC0 : out std_logic;
+ P17 : out std_logic;
+ P16 : out std_logic;
+ P15 : out std_logic;
+ P14 : out std_logic;
+ P13 : out std_logic;
+ P12 : out std_logic;
+ P11 : out std_logic;
+ P10 : out std_logic;
+ P9 : out std_logic;
+ P8 : out std_logic;
+ P7 : out std_logic;
+ P6 : out std_logic;
+ P5 : out std_logic;
+ P4 : out std_logic;
+ P3 : out std_logic;
+ P2 : out std_logic;
+ P1 : out std_logic;
+ P0 : out std_logic;
+ SIGNEDP : out std_logic );
+end component;
+
+component MULT18X18C is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_pipeline_clk : string := "NONE";
- reg_pipeline_ce : string := "CE0";
- reg_pipeline_rst : string := "RST0";
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- cas_match_reg : string := "FALSE";
- mult_bypass : string := "DISABLED";
- gsr : string := "ENABLED";
- resetmode : string := "SYNC" );
- port (
- a17 : in std_logic;
- a16 : in std_logic;
- a15 : in std_logic;
- a14 : in std_logic;
- a13 : in std_logic;
- a12 : in std_logic;
- a11 : in std_logic;
- a10 : in std_logic;
- a9 : in std_logic;
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b17 : in std_logic;
- b16 : in std_logic;
- b15 : in std_logic;
- b14 : in std_logic;
- b13 : in std_logic;
- b12 : in std_logic;
- b11 : in std_logic;
- b10 : in std_logic;
- b9 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- signeda : in std_logic;
- signedb : in std_logic;
- sourcea : in std_logic;
- sourceb : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sria17 : in std_logic;
- sria16 : in std_logic;
- sria15 : in std_logic;
- sria14 : in std_logic;
- sria13 : in std_logic;
- sria12 : in std_logic;
- sria11 : in std_logic;
- sria10 : in std_logic;
- sria9 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib17 : in std_logic;
- srib16 : in std_logic;
- srib15 : in std_logic;
- srib14 : in std_logic;
- srib13 : in std_logic;
- srib12 : in std_logic;
- srib11 : in std_logic;
- srib10 : in std_logic;
- srib9 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- sroa17 : out std_logic;
- sroa16 : out std_logic;
- sroa15 : out std_logic;
- sroa14 : out std_logic;
- sroa13 : out std_logic;
- sroa12 : out std_logic;
- sroa11 : out std_logic;
- sroa10 : out std_logic;
- sroa9 : out std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob17 : out std_logic;
- srob16 : out std_logic;
- srob15 : out std_logic;
- srob14 : out std_logic;
- srob13 : out std_logic;
- srob12 : out std_logic;
- srob11 : out std_logic;
- srob10 : out std_logic;
- srob9 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- roa17 : out std_logic;
- roa16 : out std_logic;
- roa15 : out std_logic;
- roa14 : out std_logic;
- roa13 : out std_logic;
- roa12 : out std_logic;
- roa11 : out std_logic;
- roa10 : out std_logic;
- roa9 : out std_logic;
- roa8 : out std_logic;
- roa7 : out std_logic;
- roa6 : out std_logic;
- roa5 : out std_logic;
- roa4 : out std_logic;
- roa3 : out std_logic;
- roa2 : out std_logic;
- roa1 : out std_logic;
- roa0 : out std_logic;
- rob17 : out std_logic;
- rob16 : out std_logic;
- rob15 : out std_logic;
- rob14 : out std_logic;
- rob13 : out std_logic;
- rob12 : out std_logic;
- rob11 : out std_logic;
- rob10 : out std_logic;
- rob9 : out std_logic;
- rob8 : out std_logic;
- rob7 : out std_logic;
- rob6 : out std_logic;
- rob5 : out std_logic;
- rob4 : out std_logic;
- rob3 : out std_logic;
- rob2 : out std_logic;
- rob1 : out std_logic;
- rob0 : out std_logic;
- p35 : out std_logic;
- p34 : out std_logic;
- p33 : out std_logic;
- p32 : out std_logic;
- p31 : out std_logic;
- p30 : out std_logic;
- p29 : out std_logic;
- p28 : out std_logic;
- p27 : out std_logic;
- p26 : out std_logic;
- p25 : out std_logic;
- p24 : out std_logic;
- p23 : out std_logic;
- p22 : out std_logic;
- p21 : out std_logic;
- p20 : out std_logic;
- p19 : out std_logic;
- p18 : out std_logic;
- p17 : out std_logic;
- p16 : out std_logic;
- p15 : out std_logic;
- p14 : out std_logic;
- p13 : out std_logic;
- p12 : out std_logic;
- p11 : out std_logic;
- p10 : out std_logic;
- p9 : out std_logic;
- p8 : out std_logic;
- p7 : out std_logic;
- p6 : out std_logic;
- p5 : out std_logic;
- p4 : out std_logic;
- p3 : out std_logic;
- p2 : out std_logic;
- p1 : out std_logic;
- p0 : out std_logic;
- signedp : out std_logic );
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_PIPELINE_CLK : string := "NONE";
+ REG_PIPELINE_CE : string := "CE0";
+ REG_PIPELINE_RST : string := "RST0";
+ REG_OUTPUT_CLK : string := "NONE";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
+ CAS_MATCH_REG : string := "FALSE";
+ MULT_BYPASS : string := "DISABLED";
+ GSR : string := "ENABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ A17 : in std_logic;
+ A16 : in std_logic;
+ A15 : in std_logic;
+ A14 : in std_logic;
+ A13 : in std_logic;
+ A12 : in std_logic;
+ A11 : in std_logic;
+ A10 : in std_logic;
+ A9 : in std_logic;
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B17 : in std_logic;
+ B16 : in std_logic;
+ B15 : in std_logic;
+ B14 : in std_logic;
+ B13 : in std_logic;
+ B12 : in std_logic;
+ B11 : in std_logic;
+ B10 : in std_logic;
+ B9 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ SIGNEDA : in std_logic;
+ SIGNEDB : in std_logic;
+ SOURCEA : in std_logic;
+ SOURCEB : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SRIA17 : in std_logic;
+ SRIA16 : in std_logic;
+ SRIA15 : in std_logic;
+ SRIA14 : in std_logic;
+ SRIA13 : in std_logic;
+ SRIA12 : in std_logic;
+ SRIA11 : in std_logic;
+ SRIA10 : in std_logic;
+ SRIA9 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB17 : in std_logic;
+ SRIB16 : in std_logic;
+ SRIB15 : in std_logic;
+ SRIB14 : in std_logic;
+ SRIB13 : in std_logic;
+ SRIB12 : in std_logic;
+ SRIB11 : in std_logic;
+ SRIB10 : in std_logic;
+ SRIB9 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
+ SROA17 : out std_logic;
+ SROA16 : out std_logic;
+ SROA15 : out std_logic;
+ SROA14 : out std_logic;
+ SROA13 : out std_logic;
+ SROA12 : out std_logic;
+ SROA11 : out std_logic;
+ SROA10 : out std_logic;
+ SROA9 : out std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB17 : out std_logic;
+ SROB16 : out std_logic;
+ SROB15 : out std_logic;
+ SROB14 : out std_logic;
+ SROB13 : out std_logic;
+ SROB12 : out std_logic;
+ SROB11 : out std_logic;
+ SROB10 : out std_logic;
+ SROB9 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ ROA17 : out std_logic;
+ ROA16 : out std_logic;
+ ROA15 : out std_logic;
+ ROA14 : out std_logic;
+ ROA13 : out std_logic;
+ ROA12 : out std_logic;
+ ROA11 : out std_logic;
+ ROA10 : out std_logic;
+ ROA9 : out std_logic;
+ ROA8 : out std_logic;
+ ROA7 : out std_logic;
+ ROA6 : out std_logic;
+ ROA5 : out std_logic;
+ ROA4 : out std_logic;
+ ROA3 : out std_logic;
+ ROA2 : out std_logic;
+ ROA1 : out std_logic;
+ ROA0 : out std_logic;
+ ROB17 : out std_logic;
+ ROB16 : out std_logic;
+ ROB15 : out std_logic;
+ ROB14 : out std_logic;
+ ROB13 : out std_logic;
+ ROB12 : out std_logic;
+ ROB11 : out std_logic;
+ ROB10 : out std_logic;
+ ROB9 : out std_logic;
+ ROB8 : out std_logic;
+ ROB7 : out std_logic;
+ ROB6 : out std_logic;
+ ROB5 : out std_logic;
+ ROB4 : out std_logic;
+ ROB3 : out std_logic;
+ ROB2 : out std_logic;
+ ROB1 : out std_logic;
+ ROB0 : out std_logic;
+ P35 : out std_logic;
+ P34 : out std_logic;
+ P33 : out std_logic;
+ P32 : out std_logic;
+ P31 : out std_logic;
+ P30 : out std_logic;
+ P29 : out std_logic;
+ P28 : out std_logic;
+ P27 : out std_logic;
+ P26 : out std_logic;
+ P25 : out std_logic;
+ P24 : out std_logic;
+ P23 : out std_logic;
+ P22 : out std_logic;
+ P21 : out std_logic;
+ P20 : out std_logic;
+ P19 : out std_logic;
+ P18 : out std_logic;
+ P17 : out std_logic;
+ P16 : out std_logic;
+ P15 : out std_logic;
+ P14 : out std_logic;
+ P13 : out std_logic;
+ P12 : out std_logic;
+ P11 : out std_logic;
+ P10 : out std_logic;
+ P9 : out std_logic;
+ P8 : out std_logic;
+ P7 : out std_logic;
+ P6 : out std_logic;
+ P5 : out std_logic;
+ P4 : out std_logic;
+ P3 : out std_logic;
+ P2 : out std_logic;
+ P1 : out std_logic;
+ P0 : out std_logic;
+ SIGNEDP : out std_logic );
end component;
component MULT18X18D is
@@ -1495,23 +1495,23 @@ component MULT18X18D is
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_INPUTC_CLK : string := "NONE";
- --reg_inputc_ce : string := "CE0";
- --reg_inputc_rst : string := "RST0";
+ REG_INPUTC_CE : string := "CE0";
+ REG_INPUTC_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
- --reg_output_ce : string := "CE0";
- --reg_output_rst : string := "RST0";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
- --highspeed_clk : string := "NONE";
+ HIGHSPEED_CLK : string := "NONE";
GSR : string := "ENABLED";
- --Cas_match_reg : string := "FALSE";
+ CAS_MATCH_REG : string := "FALSE";
SOURCEB_MODE : string := "B_SHIFT";
- --mult_bypass : string := "DISABLED";
+ MULT_BYPASS : string := "DISABLED";
RESETMODE : string := "SYNC" );
port (
A17 : in std_logic;
@@ -1584,42 +1584,42 @@ component MULT18X18D is
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
- -- SRIA17 : in std_logic;
- -- SRIA16 : in std_logic;
- -- SRIA15 : in std_logic;
- -- SRIA14 : in std_logic;
- -- SRIA13 : in std_logic;
- -- SRIA12 : in std_logic;
- -- SRIA11 : in std_logic;
- -- SRIA10 : in std_logic;
- -- SRIA9 : in std_logic;
- -- SRIA8 : in std_logic;
- -- SRIA7 : in std_logic;
- -- SRIA6 : in std_logic;
- -- SRIA5 : in std_logic;
- -- SRIA4 : in std_logic;
- -- SRIA3 : in std_logic;
- -- SRIA2 : in std_logic;
- -- SRIA1 : in std_logic;
- -- SRIA0 : in std_logic;
- -- SRIB17 : in std_logic;
- -- SRIB16 : in std_logic;
- -- SRIB15 : in std_logic;
- -- SRIB14 : in std_logic;
- -- SRIB13 : in std_logic;
- -- SRIB12 : in std_logic;
- -- SRIB11 : in std_logic;
- -- SRIB10 : in std_logic;
- -- SRIB9 : in std_logic;
- -- SRIB8 : in std_logic;
- -- SRIB7 : in std_logic;
- -- SRIB6 : in std_logic;
- -- SRIB5 : in std_logic;
- -- SRIB4 : in std_logic;
- -- SRIB3 : in std_logic;
- -- SRIB2 : in std_logic;
- -- SRIB1 : in std_logic;
- -- SRIB0 : in std_logic;
+ SRIA17 : in std_logic;
+ SRIA16 : in std_logic;
+ SRIA15 : in std_logic;
+ SRIA14 : in std_logic;
+ SRIA13 : in std_logic;
+ SRIA12 : in std_logic;
+ SRIA11 : in std_logic;
+ SRIA10 : in std_logic;
+ SRIA9 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB17 : in std_logic;
+ SRIB16 : in std_logic;
+ SRIB15 : in std_logic;
+ SRIB14 : in std_logic;
+ SRIB13 : in std_logic;
+ SRIB12 : in std_logic;
+ SRIB11 : in std_logic;
+ SRIB10 : in std_logic;
+ SRIB9 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
SROA17 : out std_logic;
SROA16 : out std_logic;
SROA15 : out std_logic;
@@ -1746,1991 +1746,1991 @@ component MULT18X18D is
P2 : out std_logic;
P1 : out std_logic;
P0 : out std_logic;
- SIGNEDP : out std_logic );
+ SIGNEDP : out std_logic );
end component;
-component alu24a is
+component ALU24A is
generic (
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- reg_opcode_0_clk : string := "NONE";
- reg_opcode_0_ce : string := "CE0";
- reg_opcode_0_rst : string := "RST0";
- reg_opcode_1_clk : string := "NONE";
- reg_opcode_1_ce : string := "CE0";
- reg_opcode_1_rst : string := "RST0";
- gsr : string := "ENABLED";
- resetmode : string := "SYNC" );
- port (
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- signedia : in std_logic;
- signedib : in std_logic;
- ma17 : in std_logic;
- ma16 : in std_logic;
- ma15 : in std_logic;
- ma14 : in std_logic;
- ma13 : in std_logic;
- ma12 : in std_logic;
- ma11 : in std_logic;
- ma10 : in std_logic;
- ma9 : in std_logic;
- ma8 : in std_logic;
- ma7 : in std_logic;
- ma6 : in std_logic;
- ma5 : in std_logic;
- ma4 : in std_logic;
- ma3 : in std_logic;
- ma2 : in std_logic;
- ma1 : in std_logic;
- ma0 : in std_logic;
- mb17 : in std_logic;
- mb16 : in std_logic;
- mb15 : in std_logic;
- mb14 : in std_logic;
- mb13 : in std_logic;
- mb12 : in std_logic;
- mb11 : in std_logic;
- mb10 : in std_logic;
- mb9 : in std_logic;
- mb8 : in std_logic;
- mb7 : in std_logic;
- mb6 : in std_logic;
- mb5 : in std_logic;
- mb4 : in std_logic;
- mb3 : in std_logic;
- mb2 : in std_logic;
- mb1 : in std_logic;
- mb0 : in std_logic;
- cin23 : in std_logic;
- cin22 : in std_logic;
- cin21 : in std_logic;
- cin20 : in std_logic;
- cin19 : in std_logic;
- cin18 : in std_logic;
- cin17 : in std_logic;
- cin16 : in std_logic;
- cin15 : in std_logic;
- cin14 : in std_logic;
- cin13 : in std_logic;
- cin12 : in std_logic;
- cin11 : in std_logic;
- cin10 : in std_logic;
- cin9 : in std_logic;
- cin8 : in std_logic;
- cin7 : in std_logic;
- cin6 : in std_logic;
- cin5 : in std_logic;
- cin4 : in std_logic;
- cin3 : in std_logic;
- cin2 : in std_logic;
- cin1 : in std_logic;
- cin0 : in std_logic;
- opaddnsub : in std_logic;
- opcinsel : in std_logic;
- r23 : out std_logic;
- r22 : out std_logic;
- r21 : out std_logic;
- r20 : out std_logic;
- r19 : out std_logic;
- r18 : out std_logic;
- r17 : out std_logic;
- r16 : out std_logic;
- r15 : out std_logic;
- r14 : out std_logic;
- r13 : out std_logic;
- r12 : out std_logic;
- r11 : out std_logic;
- r10 : out std_logic;
- r9 : out std_logic;
- r8 : out std_logic;
- r7 : out std_logic;
- r6 : out std_logic;
- r5 : out std_logic;
- r4 : out std_logic;
- r3 : out std_logic;
- r2 : out std_logic;
- r1 : out std_logic;
- r0 : out std_logic );
-end component;
-
-component alu54a is
+ REG_OUTPUT_CLK : string := "NONE";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
+ REG_OPCODE_0_CLK : string := "NONE";
+ REG_OPCODE_0_CE : string := "CE0";
+ REG_OPCODE_0_RST : string := "RST0";
+ REG_OPCODE_1_CLK : string := "NONE";
+ REG_OPCODE_1_CE : string := "CE0";
+ REG_OPCODE_1_RST : string := "RST0";
+ GSR : string := "ENABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SIGNEDIA : in std_logic;
+ SIGNEDIB : in std_logic;
+ MA17 : in std_logic;
+ MA16 : in std_logic;
+ MA15 : in std_logic;
+ MA14 : in std_logic;
+ MA13 : in std_logic;
+ MA12 : in std_logic;
+ MA11 : in std_logic;
+ MA10 : in std_logic;
+ MA9 : in std_logic;
+ MA8 : in std_logic;
+ MA7 : in std_logic;
+ MA6 : in std_logic;
+ MA5 : in std_logic;
+ MA4 : in std_logic;
+ MA3 : in std_logic;
+ MA2 : in std_logic;
+ MA1 : in std_logic;
+ MA0 : in std_logic;
+ MB17 : in std_logic;
+ MB16 : in std_logic;
+ MB15 : in std_logic;
+ MB14 : in std_logic;
+ MB13 : in std_logic;
+ MB12 : in std_logic;
+ MB11 : in std_logic;
+ MB10 : in std_logic;
+ MB9 : in std_logic;
+ MB8 : in std_logic;
+ MB7 : in std_logic;
+ MB6 : in std_logic;
+ MB5 : in std_logic;
+ MB4 : in std_logic;
+ MB3 : in std_logic;
+ MB2 : in std_logic;
+ MB1 : in std_logic;
+ MB0 : in std_logic;
+ CIN23 : in std_logic;
+ CIN22 : in std_logic;
+ CIN21 : in std_logic;
+ CIN20 : in std_logic;
+ CIN19 : in std_logic;
+ CIN18 : in std_logic;
+ CIN17 : in std_logic;
+ CIN16 : in std_logic;
+ CIN15 : in std_logic;
+ CIN14 : in std_logic;
+ CIN13 : in std_logic;
+ CIN12 : in std_logic;
+ CIN11 : in std_logic;
+ CIN10 : in std_logic;
+ CIN9 : in std_logic;
+ CIN8 : in std_logic;
+ CIN7 : in std_logic;
+ CIN6 : in std_logic;
+ CIN5 : in std_logic;
+ CIN4 : in std_logic;
+ CIN3 : in std_logic;
+ CIN2 : in std_logic;
+ CIN1 : in std_logic;
+ CIN0 : in std_logic;
+ OPADDNSUB : in std_logic;
+ OPCINSEL : in std_logic;
+ R23 : out std_logic;
+ R22 : out std_logic;
+ R21 : out std_logic;
+ R20 : out std_logic;
+ R19 : out std_logic;
+ R18 : out std_logic;
+ R17 : out std_logic;
+ R16 : out std_logic;
+ R15 : out std_logic;
+ R14 : out std_logic;
+ R13 : out std_logic;
+ R12 : out std_logic;
+ R11 : out std_logic;
+ R10 : out std_logic;
+ R9 : out std_logic;
+ R8 : out std_logic;
+ R7 : out std_logic;
+ R6 : out std_logic;
+ R5 : out std_logic;
+ R4 : out std_logic;
+ R3 : out std_logic;
+ R2 : out std_logic;
+ R1 : out std_logic;
+ R0 : out std_logic );
+end component;
+
+component ALU54A is
generic (
- reg_inputc0_clk : string := "NONE";
- reg_inputc0_ce : string := "CE0";
- reg_inputc0_rst : string := "RST0";
- reg_inputc1_clk : string := "NONE";
- reg_inputc1_ce : string := "CE0";
- reg_inputc1_rst : string := "RST0";
- reg_opcodeop0_0_clk : string := "NONE";
- reg_opcodeop0_0_ce : string := "CE0";
- reg_opcodeop0_0_rst : string := "RST0";
- reg_opcodeop1_0_clk : string := "NONE";
- reg_opcodeop0_1_clk : string := "NONE";
- reg_opcodeop0_1_ce : string := "CE0";
- reg_opcodeop0_1_rst : string := "RST0";
- reg_opcodeop1_1_clk : string := "NONE";
- reg_opcodein_0_clk : string := "NONE";
- reg_opcodein_0_ce : string := "CE0";
- reg_opcodein_0_rst : string := "RST0";
- reg_opcodein_1_clk : string := "NONE";
- reg_opcodein_1_ce : string := "CE0";
- reg_opcodein_1_rst : string := "RST0";
- reg_output0_clk : string := "NONE";
- reg_output0_ce : string := "CE0";
- reg_output0_rst : string := "RST0";
- reg_output1_clk : string := "NONE";
- reg_output1_ce : string := "CE0";
- reg_output1_rst : string := "RST0";
- reg_flag_clk : string := "NONE";
- reg_flag_ce : string := "CE0";
- reg_flag_rst : string := "RST0";
- mcpat_source : string := "STATIC";
- maskpat_source : string := "STATIC";
- mask01 : string := "0x00000000000000";
- mcpat : string := "0x00000000000000";
- maskpat : string := "0x00000000000000";
- rndpat : string := "0x00000000000000";
- gsr : string := "ENABLED";
- resetmode : string := "SYNC";
- mult9_mode : string := "DISABLED";
- legacy : string := "DISABLED" );
- port (
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- signedia : in std_logic;
- signedib : in std_logic;
- signedcin : in std_logic;
- a35 : in std_logic;
- a34 : in std_logic;
- a33 : in std_logic;
- a32 : in std_logic;
- a31 : in std_logic;
- a30 : in std_logic;
- a29 : in std_logic;
- a28 : in std_logic;
- a27 : in std_logic;
- a26 : in std_logic;
- a25 : in std_logic;
- a24 : in std_logic;
- a23 : in std_logic;
- a22 : in std_logic;
- a21 : in std_logic;
- a20 : in std_logic;
- a19 : in std_logic;
- a18 : in std_logic;
- a17 : in std_logic;
- a16 : in std_logic;
- a15 : in std_logic;
- a14 : in std_logic;
- a13 : in std_logic;
- a12 : in std_logic;
- a11 : in std_logic;
- a10 : in std_logic;
- a9 : in std_logic;
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b35 : in std_logic;
- b34 : in std_logic;
- b33 : in std_logic;
- b32 : in std_logic;
- b31 : in std_logic;
- b30 : in std_logic;
- b29 : in std_logic;
- b28 : in std_logic;
- b27 : in std_logic;
- b26 : in std_logic;
- b25 : in std_logic;
- b24 : in std_logic;
- b23 : in std_logic;
- b22 : in std_logic;
- b21 : in std_logic;
- b20 : in std_logic;
- b19 : in std_logic;
- b18 : in std_logic;
- b17 : in std_logic;
- b16 : in std_logic;
- b15 : in std_logic;
- b14 : in std_logic;
- b13 : in std_logic;
- b12 : in std_logic;
- b11 : in std_logic;
- b10 : in std_logic;
- b9 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- c53 : in std_logic;
- c52 : in std_logic;
- c51 : in std_logic;
- c50 : in std_logic;
- c49 : in std_logic;
- c48 : in std_logic;
- c47 : in std_logic;
- c46 : in std_logic;
- c45 : in std_logic;
- c44 : in std_logic;
- c43 : in std_logic;
- c42 : in std_logic;
- c41 : in std_logic;
- c40 : in std_logic;
- c39 : in std_logic;
- c38 : in std_logic;
- c37 : in std_logic;
- c36 : in std_logic;
- c35 : in std_logic;
- c34 : in std_logic;
- c33 : in std_logic;
- c32 : in std_logic;
- c31 : in std_logic;
- c30 : in std_logic;
- c29 : in std_logic;
- c28 : in std_logic;
- c27 : in std_logic;
- c26 : in std_logic;
- c25 : in std_logic;
- c24 : in std_logic;
- c23 : in std_logic;
- c22 : in std_logic;
- c21 : in std_logic;
- c20 : in std_logic;
- c19 : in std_logic;
- c18 : in std_logic;
- c17 : in std_logic;
- c16 : in std_logic;
- c15 : in std_logic;
- c14 : in std_logic;
- c13 : in std_logic;
- c12 : in std_logic;
- c11 : in std_logic;
- c10 : in std_logic;
- c9 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- ma35 : in std_logic;
- ma34 : in std_logic;
- ma33 : in std_logic;
- ma32 : in std_logic;
- ma31 : in std_logic;
- ma30 : in std_logic;
- ma29 : in std_logic;
- ma28 : in std_logic;
- ma27 : in std_logic;
- ma26 : in std_logic;
- ma25 : in std_logic;
- ma24 : in std_logic;
- ma23 : in std_logic;
- ma22 : in std_logic;
- ma21 : in std_logic;
- ma20 : in std_logic;
- ma19 : in std_logic;
- ma18 : in std_logic;
- ma17 : in std_logic;
- ma16 : in std_logic;
- ma15 : in std_logic;
- ma14 : in std_logic;
- ma13 : in std_logic;
- ma12 : in std_logic;
- ma11 : in std_logic;
- ma10 : in std_logic;
- ma9 : in std_logic;
- ma8 : in std_logic;
- ma7 : in std_logic;
- ma6 : in std_logic;
- ma5 : in std_logic;
- ma4 : in std_logic;
- ma3 : in std_logic;
- ma2 : in std_logic;
- ma1 : in std_logic;
- ma0 : in std_logic;
- mb35 : in std_logic;
- mb34 : in std_logic;
- mb33 : in std_logic;
- mb32 : in std_logic;
- mb31 : in std_logic;
- mb30 : in std_logic;
- mb29 : in std_logic;
- mb28 : in std_logic;
- mb27 : in std_logic;
- mb26 : in std_logic;
- mb25 : in std_logic;
- mb24 : in std_logic;
- mb23 : in std_logic;
- mb22 : in std_logic;
- mb21 : in std_logic;
- mb20 : in std_logic;
- mb19 : in std_logic;
- mb18 : in std_logic;
- mb17 : in std_logic;
- mb16 : in std_logic;
- mb15 : in std_logic;
- mb14 : in std_logic;
- mb13 : in std_logic;
- mb12 : in std_logic;
- mb11 : in std_logic;
- mb10 : in std_logic;
- mb9 : in std_logic;
- mb8 : in std_logic;
- mb7 : in std_logic;
- mb6 : in std_logic;
- mb5 : in std_logic;
- mb4 : in std_logic;
- mb3 : in std_logic;
- mb2 : in std_logic;
- mb1 : in std_logic;
- mb0 : in std_logic;
- cin53 : in std_logic;
- cin52 : in std_logic;
- cin51 : in std_logic;
- cin50 : in std_logic;
- cin49 : in std_logic;
- cin48 : in std_logic;
- cin47 : in std_logic;
- cin46 : in std_logic;
- cin45 : in std_logic;
- cin44 : in std_logic;
- cin43 : in std_logic;
- cin42 : in std_logic;
- cin41 : in std_logic;
- cin40 : in std_logic;
- cin39 : in std_logic;
- cin38 : in std_logic;
- cin37 : in std_logic;
- cin36 : in std_logic;
- cin35 : in std_logic;
- cin34 : in std_logic;
- cin33 : in std_logic;
- cin32 : in std_logic;
- cin31 : in std_logic;
- cin30 : in std_logic;
- cin29 : in std_logic;
- cin28 : in std_logic;
- cin27 : in std_logic;
- cin26 : in std_logic;
- cin25 : in std_logic;
- cin24 : in std_logic;
- cin23 : in std_logic;
- cin22 : in std_logic;
- cin21 : in std_logic;
- cin20 : in std_logic;
- cin19 : in std_logic;
- cin18 : in std_logic;
- cin17 : in std_logic;
- cin16 : in std_logic;
- cin15 : in std_logic;
- cin14 : in std_logic;
- cin13 : in std_logic;
- cin12 : in std_logic;
- cin11 : in std_logic;
- cin10 : in std_logic;
- cin9 : in std_logic;
- cin8 : in std_logic;
- cin7 : in std_logic;
- cin6 : in std_logic;
- cin5 : in std_logic;
- cin4 : in std_logic;
- cin3 : in std_logic;
- cin2 : in std_logic;
- cin1 : in std_logic;
- cin0 : in std_logic;
- op10 : in std_logic;
- op9 : in std_logic;
- op8 : in std_logic;
- op7 : in std_logic;
- op6 : in std_logic;
- op5 : in std_logic;
- op4 : in std_logic;
- op3 : in std_logic;
- op2 : in std_logic;
- op1 : in std_logic;
- op0 : in std_logic;
- r53 : out std_logic;
- r52 : out std_logic;
- r51 : out std_logic;
- r50 : out std_logic;
- r49 : out std_logic;
- r48 : out std_logic;
- r47 : out std_logic;
- r46 : out std_logic;
- r45 : out std_logic;
- r44 : out std_logic;
- r43 : out std_logic;
- r42 : out std_logic;
- r41 : out std_logic;
- r40 : out std_logic;
- r39 : out std_logic;
- r38 : out std_logic;
- r37 : out std_logic;
- r36 : out std_logic;
- r35 : out std_logic;
- r34 : out std_logic;
- r33 : out std_logic;
- r32 : out std_logic;
- r31 : out std_logic;
- r30 : out std_logic;
- r29 : out std_logic;
- r28 : out std_logic;
- r27 : out std_logic;
- r26 : out std_logic;
- r25 : out std_logic;
- r24 : out std_logic;
- r23 : out std_logic;
- r22 : out std_logic;
- r21 : out std_logic;
- r20 : out std_logic;
- r19 : out std_logic;
- r18 : out std_logic;
- r17 : out std_logic;
- r16 : out std_logic;
- r15 : out std_logic;
- r14 : out std_logic;
- r13 : out std_logic;
- r12 : out std_logic;
- r11 : out std_logic;
- r10 : out std_logic;
- r9 : out std_logic;
- r8 : out std_logic;
- r7 : out std_logic;
- r6 : out std_logic;
- r5 : out std_logic;
- r4 : out std_logic;
- r3 : out std_logic;
- r2 : out std_logic;
- r1 : out std_logic;
- r0 : out std_logic;
- eqz : out std_logic;
- eqzm : out std_logic;
- eqom : out std_logic;
- eqpat : out std_logic;
- eqpatb : out std_logic;
- over : out std_logic;
- under : out std_logic;
- overunder : out std_logic;
- signedr : out std_logic );
-end component;
-
-component alu24b is
+ REG_INPUTC0_CLK : string := "NONE";
+ REG_INPUTC0_CE : string := "CE0";
+ REG_INPUTC0_RST : string := "RST0";
+ REG_INPUTC1_CLK : string := "NONE";
+ REG_INPUTC1_CE : string := "CE0";
+ REG_INPUTC1_RST : string := "RST0";
+ REG_OPCODEOP0_0_CLK : string := "NONE";
+ REG_OPCODEOP0_0_CE : string := "CE0";
+ REG_OPCODEOP0_0_RST : string := "RST0";
+ REG_OPCODEOP1_0_CLK : string := "NONE";
+ REG_OPCODEOP0_1_CLK : string := "NONE";
+ REG_OPCODEOP0_1_CE : string := "CE0";
+ REG_OPCODEOP0_1_RST : string := "RST0";
+ REG_OPCODEOP1_1_CLK : string := "NONE";
+ REG_OPCODEIN_0_CLK : string := "NONE";
+ REG_OPCODEIN_0_CE : string := "CE0";
+ REG_OPCODEIN_0_RST : string := "RST0";
+ REG_OPCODEIN_1_CLK : string := "NONE";
+ REG_OPCODEIN_1_CE : string := "CE0";
+ REG_OPCODEIN_1_RST : string := "RST0";
+ REG_OUTPUT0_CLK : string := "NONE";
+ REG_OUTPUT0_CE : string := "CE0";
+ REG_OUTPUT0_RST : string := "RST0";
+ REG_OUTPUT1_CLK : string := "NONE";
+ REG_OUTPUT1_CE : string := "CE0";
+ REG_OUTPUT1_RST : string := "RST0";
+ REG_FLAG_CLK : string := "NONE";
+ REG_FLAG_CE : string := "CE0";
+ REG_FLAG_RST : string := "RST0";
+ MCPAT_SOURCE : string := "STATIC";
+ MASKPAT_SOURCE : string := "STATIC";
+ MASK01 : string := "0x00000000000000";
+ MCPAT : string := "0x00000000000000";
+ MASKPAT : string := "0x00000000000000";
+ RNDPAT : string := "0x00000000000000";
+ GSR : string := "ENABLED";
+ RESETMODE : string := "SYNC";
+ MULT9_MODE : string := "DISABLED";
+ LEGACY : string := "DISABLED" );
+ port (
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SIGNEDIA : in std_logic;
+ SIGNEDIB : in std_logic;
+ SIGNEDCIN : in std_logic;
+ A35 : in std_logic;
+ A34 : in std_logic;
+ A33 : in std_logic;
+ A32 : in std_logic;
+ A31 : in std_logic;
+ A30 : in std_logic;
+ A29 : in std_logic;
+ A28 : in std_logic;
+ A27 : in std_logic;
+ A26 : in std_logic;
+ A25 : in std_logic;
+ A24 : in std_logic;
+ A23 : in std_logic;
+ A22 : in std_logic;
+ A21 : in std_logic;
+ A20 : in std_logic;
+ A19 : in std_logic;
+ A18 : in std_logic;
+ A17 : in std_logic;
+ A16 : in std_logic;
+ A15 : in std_logic;
+ A14 : in std_logic;
+ A13 : in std_logic;
+ A12 : in std_logic;
+ A11 : in std_logic;
+ A10 : in std_logic;
+ A9 : in std_logic;
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B35 : in std_logic;
+ B34 : in std_logic;
+ B33 : in std_logic;
+ B32 : in std_logic;
+ B31 : in std_logic;
+ B30 : in std_logic;
+ B29 : in std_logic;
+ B28 : in std_logic;
+ B27 : in std_logic;
+ B26 : in std_logic;
+ B25 : in std_logic;
+ B24 : in std_logic;
+ B23 : in std_logic;
+ B22 : in std_logic;
+ B21 : in std_logic;
+ B20 : in std_logic;
+ B19 : in std_logic;
+ B18 : in std_logic;
+ B17 : in std_logic;
+ B16 : in std_logic;
+ B15 : in std_logic;
+ B14 : in std_logic;
+ B13 : in std_logic;
+ B12 : in std_logic;
+ B11 : in std_logic;
+ B10 : in std_logic;
+ B9 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ C53 : in std_logic;
+ C52 : in std_logic;
+ C51 : in std_logic;
+ C50 : in std_logic;
+ C49 : in std_logic;
+ C48 : in std_logic;
+ C47 : in std_logic;
+ C46 : in std_logic;
+ C45 : in std_logic;
+ C44 : in std_logic;
+ C43 : in std_logic;
+ C42 : in std_logic;
+ C41 : in std_logic;
+ C40 : in std_logic;
+ C39 : in std_logic;
+ C38 : in std_logic;
+ C37 : in std_logic;
+ C36 : in std_logic;
+ C35 : in std_logic;
+ C34 : in std_logic;
+ C33 : in std_logic;
+ C32 : in std_logic;
+ C31 : in std_logic;
+ C30 : in std_logic;
+ C29 : in std_logic;
+ C28 : in std_logic;
+ C27 : in std_logic;
+ C26 : in std_logic;
+ C25 : in std_logic;
+ C24 : in std_logic;
+ C23 : in std_logic;
+ C22 : in std_logic;
+ C21 : in std_logic;
+ C20 : in std_logic;
+ C19 : in std_logic;
+ C18 : in std_logic;
+ C17 : in std_logic;
+ C16 : in std_logic;
+ C15 : in std_logic;
+ C14 : in std_logic;
+ C13 : in std_logic;
+ C12 : in std_logic;
+ C11 : in std_logic;
+ C10 : in std_logic;
+ C9 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ MA35 : in std_logic;
+ MA34 : in std_logic;
+ MA33 : in std_logic;
+ MA32 : in std_logic;
+ MA31 : in std_logic;
+ MA30 : in std_logic;
+ MA29 : in std_logic;
+ MA28 : in std_logic;
+ MA27 : in std_logic;
+ MA26 : in std_logic;
+ MA25 : in std_logic;
+ MA24 : in std_logic;
+ MA23 : in std_logic;
+ MA22 : in std_logic;
+ MA21 : in std_logic;
+ MA20 : in std_logic;
+ MA19 : in std_logic;
+ MA18 : in std_logic;
+ MA17 : in std_logic;
+ MA16 : in std_logic;
+ MA15 : in std_logic;
+ MA14 : in std_logic;
+ MA13 : in std_logic;
+ MA12 : in std_logic;
+ MA11 : in std_logic;
+ MA10 : in std_logic;
+ MA9 : in std_logic;
+ MA8 : in std_logic;
+ MA7 : in std_logic;
+ MA6 : in std_logic;
+ MA5 : in std_logic;
+ MA4 : in std_logic;
+ MA3 : in std_logic;
+ MA2 : in std_logic;
+ MA1 : in std_logic;
+ MA0 : in std_logic;
+ MB35 : in std_logic;
+ MB34 : in std_logic;
+ MB33 : in std_logic;
+ MB32 : in std_logic;
+ MB31 : in std_logic;
+ MB30 : in std_logic;
+ MB29 : in std_logic;
+ MB28 : in std_logic;
+ MB27 : in std_logic;
+ MB26 : in std_logic;
+ MB25 : in std_logic;
+ MB24 : in std_logic;
+ MB23 : in std_logic;
+ MB22 : in std_logic;
+ MB21 : in std_logic;
+ MB20 : in std_logic;
+ MB19 : in std_logic;
+ MB18 : in std_logic;
+ MB17 : in std_logic;
+ MB16 : in std_logic;
+ MB15 : in std_logic;
+ MB14 : in std_logic;
+ MB13 : in std_logic;
+ MB12 : in std_logic;
+ MB11 : in std_logic;
+ MB10 : in std_logic;
+ MB9 : in std_logic;
+ MB8 : in std_logic;
+ MB7 : in std_logic;
+ MB6 : in std_logic;
+ MB5 : in std_logic;
+ MB4 : in std_logic;
+ MB3 : in std_logic;
+ MB2 : in std_logic;
+ MB1 : in std_logic;
+ MB0 : in std_logic;
+ CIN53 : in std_logic;
+ CIN52 : in std_logic;
+ CIN51 : in std_logic;
+ CIN50 : in std_logic;
+ CIN49 : in std_logic;
+ CIN48 : in std_logic;
+ CIN47 : in std_logic;
+ CIN46 : in std_logic;
+ CIN45 : in std_logic;
+ CIN44 : in std_logic;
+ CIN43 : in std_logic;
+ CIN42 : in std_logic;
+ CIN41 : in std_logic;
+ CIN40 : in std_logic;
+ CIN39 : in std_logic;
+ CIN38 : in std_logic;
+ CIN37 : in std_logic;
+ CIN36 : in std_logic;
+ CIN35 : in std_logic;
+ CIN34 : in std_logic;
+ CIN33 : in std_logic;
+ CIN32 : in std_logic;
+ CIN31 : in std_logic;
+ CIN30 : in std_logic;
+ CIN29 : in std_logic;
+ CIN28 : in std_logic;
+ CIN27 : in std_logic;
+ CIN26 : in std_logic;
+ CIN25 : in std_logic;
+ CIN24 : in std_logic;
+ CIN23 : in std_logic;
+ CIN22 : in std_logic;
+ CIN21 : in std_logic;
+ CIN20 : in std_logic;
+ CIN19 : in std_logic;
+ CIN18 : in std_logic;
+ CIN17 : in std_logic;
+ CIN16 : in std_logic;
+ CIN15 : in std_logic;
+ CIN14 : in std_logic;
+ CIN13 : in std_logic;
+ CIN12 : in std_logic;
+ CIN11 : in std_logic;
+ CIN10 : in std_logic;
+ CIN9 : in std_logic;
+ CIN8 : in std_logic;
+ CIN7 : in std_logic;
+ CIN6 : in std_logic;
+ CIN5 : in std_logic;
+ CIN4 : in std_logic;
+ CIN3 : in std_logic;
+ CIN2 : in std_logic;
+ CIN1 : in std_logic;
+ CIN0 : in std_logic;
+ OP10 : in std_logic;
+ OP9 : in std_logic;
+ OP8 : in std_logic;
+ OP7 : in std_logic;
+ OP6 : in std_logic;
+ OP5 : in std_logic;
+ OP4 : in std_logic;
+ OP3 : in std_logic;
+ OP2 : in std_logic;
+ OP1 : in std_logic;
+ OP0 : in std_logic;
+ R53 : out std_logic;
+ R52 : out std_logic;
+ R51 : out std_logic;
+ R50 : out std_logic;
+ R49 : out std_logic;
+ R48 : out std_logic;
+ R47 : out std_logic;
+ R46 : out std_logic;
+ R45 : out std_logic;
+ R44 : out std_logic;
+ R43 : out std_logic;
+ R42 : out std_logic;
+ R41 : out std_logic;
+ R40 : out std_logic;
+ R39 : out std_logic;
+ R38 : out std_logic;
+ R37 : out std_logic;
+ R36 : out std_logic;
+ R35 : out std_logic;
+ R34 : out std_logic;
+ R33 : out std_logic;
+ R32 : out std_logic;
+ R31 : out std_logic;
+ R30 : out std_logic;
+ R29 : out std_logic;
+ R28 : out std_logic;
+ R27 : out std_logic;
+ R26 : out std_logic;
+ R25 : out std_logic;
+ R24 : out std_logic;
+ R23 : out std_logic;
+ R22 : out std_logic;
+ R21 : out std_logic;
+ R20 : out std_logic;
+ R19 : out std_logic;
+ R18 : out std_logic;
+ R17 : out std_logic;
+ R16 : out std_logic;
+ R15 : out std_logic;
+ R14 : out std_logic;
+ R13 : out std_logic;
+ R12 : out std_logic;
+ R11 : out std_logic;
+ R10 : out std_logic;
+ R9 : out std_logic;
+ R8 : out std_logic;
+ R7 : out std_logic;
+ R6 : out std_logic;
+ R5 : out std_logic;
+ R4 : out std_logic;
+ R3 : out std_logic;
+ R2 : out std_logic;
+ R1 : out std_logic;
+ R0 : out std_logic;
+ EQZ : out std_logic;
+ EQZM : out std_logic;
+ EQOM : out std_logic;
+ EQPAT : out std_logic;
+ EQPATB : out std_logic;
+ OVER : out std_logic;
+ UNDER : out std_logic;
+ OVERUNDER : out std_logic;
+ SIGNEDR : out std_logic );
+end component;
+
+component ALU24B is
generic (
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- reg_opcode_0_clk : string := "NONE";
- reg_opcode_0_ce : string := "CE0";
- reg_opcode_0_rst : string := "RST0";
- reg_opcode_1_clk : string := "NONE";
- reg_opcode_1_ce : string := "CE0";
- reg_opcode_1_rst : string := "RST0";
- reg_inputcfb_clk : string := "NONE";
- reg_inputcfb_ce : string := "CE0";
- reg_inputcfb_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- gsr : string := "ENABLED";
- resetmode : string := "SYNC" );
- port (
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- signedia : in std_logic;
- signedib : in std_logic;
- ma17 : in std_logic;
- ma16 : in std_logic;
- ma15 : in std_logic;
- ma14 : in std_logic;
- ma13 : in std_logic;
- ma12 : in std_logic;
- ma11 : in std_logic;
- ma10 : in std_logic;
- ma9 : in std_logic;
- ma8 : in std_logic;
- ma7 : in std_logic;
- ma6 : in std_logic;
- ma5 : in std_logic;
- ma4 : in std_logic;
- ma3 : in std_logic;
- ma2 : in std_logic;
- ma1 : in std_logic;
- ma0 : in std_logic;
- mb17 : in std_logic;
- mb16 : in std_logic;
- mb15 : in std_logic;
- mb14 : in std_logic;
- mb13 : in std_logic;
- mb12 : in std_logic;
- mb11 : in std_logic;
- mb10 : in std_logic;
- mb9 : in std_logic;
- mb8 : in std_logic;
- mb7 : in std_logic;
- mb6 : in std_logic;
- mb5 : in std_logic;
- mb4 : in std_logic;
- mb3 : in std_logic;
- mb2 : in std_logic;
- mb1 : in std_logic;
- mb0 : in std_logic;
- cfb23 : in std_logic;
- cfb22 : in std_logic;
- cfb21 : in std_logic;
- cfb20 : in std_logic;
- cfb19 : in std_logic;
- cfb18 : in std_logic;
- cfb17 : in std_logic;
- cfb16 : in std_logic;
- cfb15 : in std_logic;
- cfb14 : in std_logic;
- cfb13 : in std_logic;
- cfb12 : in std_logic;
- cfb11 : in std_logic;
- cfb10 : in std_logic;
- cfb9 : in std_logic;
- cfb8 : in std_logic;
- cfb7 : in std_logic;
- cfb6 : in std_logic;
- cfb5 : in std_logic;
- cfb4 : in std_logic;
- cfb3 : in std_logic;
- cfb2 : in std_logic;
- cfb1 : in std_logic;
- cfb0 : in std_logic;
- cin23 : in std_logic;
- cin22 : in std_logic;
- cin21 : in std_logic;
- cin20 : in std_logic;
- cin19 : in std_logic;
- cin18 : in std_logic;
- cin17 : in std_logic;
- cin16 : in std_logic;
- cin15 : in std_logic;
- cin14 : in std_logic;
- cin13 : in std_logic;
- cin12 : in std_logic;
- cin11 : in std_logic;
- cin10 : in std_logic;
- cin9 : in std_logic;
- cin8 : in std_logic;
- cin7 : in std_logic;
- cin6 : in std_logic;
- cin5 : in std_logic;
- cin4 : in std_logic;
- cin3 : in std_logic;
- cin2 : in std_logic;
- cin1 : in std_logic;
- cin0 : in std_logic;
- opaddnsub : in std_logic;
- opcinsel : in std_logic;
- r23 : out std_logic;
- r22 : out std_logic;
- r21 : out std_logic;
- r20 : out std_logic;
- r19 : out std_logic;
- r18 : out std_logic;
- r17 : out std_logic;
- r16 : out std_logic;
- r15 : out std_logic;
- r14 : out std_logic;
- r13 : out std_logic;
- r12 : out std_logic;
- r11 : out std_logic;
- r10 : out std_logic;
- r9 : out std_logic;
- r8 : out std_logic;
- r7 : out std_logic;
- r6 : out std_logic;
- r5 : out std_logic;
- r4 : out std_logic;
- r3 : out std_logic;
- r2 : out std_logic;
- r1 : out std_logic;
- r0 : out std_logic;
- co23 : out std_logic;
- co22 : out std_logic;
- co21 : out std_logic;
- co20 : out std_logic;
- co19 : out std_logic;
- co18 : out std_logic;
- co17 : out std_logic;
- co16 : out std_logic;
- co15 : out std_logic;
- co14 : out std_logic;
- co13 : out std_logic;
- co12 : out std_logic;
- co11 : out std_logic;
- co10 : out std_logic;
- co9 : out std_logic;
- co8 : out std_logic;
- co7 : out std_logic;
- co6 : out std_logic;
- co5 : out std_logic;
- co4 : out std_logic;
- co3 : out std_logic;
- co2 : out std_logic;
- co1 : out std_logic;
- co0 : out std_logic );
-end component;
-
-component alu54b is
+ REG_OUTPUT_CLK : string := "NONE";
+ REG_OUTPUT_CE : string := "CE0";
+ REG_OUTPUT_RST : string := "RST0";
+ REG_OPCODE_0_CLK : string := "NONE";
+ REG_OPCODE_0_CE : string := "CE0";
+ REG_OPCODE_0_RST : string := "RST0";
+ REG_OPCODE_1_CLK : string := "NONE";
+ REG_OPCODE_1_CE : string := "CE0";
+ REG_OPCODE_1_RST : string := "RST0";
+ REG_INPUTCFB_CLK : string := "NONE";
+ REG_INPUTCFB_CE : string := "CE0";
+ REG_INPUTCFB_RST : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ GSR : string := "ENABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SIGNEDIA : in std_logic;
+ SIGNEDIB : in std_logic;
+ MA17 : in std_logic;
+ MA16 : in std_logic;
+ MA15 : in std_logic;
+ MA14 : in std_logic;
+ MA13 : in std_logic;
+ MA12 : in std_logic;
+ MA11 : in std_logic;
+ MA10 : in std_logic;
+ MA9 : in std_logic;
+ MA8 : in std_logic;
+ MA7 : in std_logic;
+ MA6 : in std_logic;
+ MA5 : in std_logic;
+ MA4 : in std_logic;
+ MA3 : in std_logic;
+ MA2 : in std_logic;
+ MA1 : in std_logic;
+ MA0 : in std_logic;
+ MB17 : in std_logic;
+ MB16 : in std_logic;
+ MB15 : in std_logic;
+ MB14 : in std_logic;
+ MB13 : in std_logic;
+ MB12 : in std_logic;
+ MB11 : in std_logic;
+ MB10 : in std_logic;
+ MB9 : in std_logic;
+ MB8 : in std_logic;
+ MB7 : in std_logic;
+ MB6 : in std_logic;
+ MB5 : in std_logic;
+ MB4 : in std_logic;
+ MB3 : in std_logic;
+ MB2 : in std_logic;
+ MB1 : in std_logic;
+ MB0 : in std_logic;
+ CFB23 : in std_logic;
+ CFB22 : in std_logic;
+ CFB21 : in std_logic;
+ CFB20 : in std_logic;
+ CFB19 : in std_logic;
+ CFB18 : in std_logic;
+ CFB17 : in std_logic;
+ CFB16 : in std_logic;
+ CFB15 : in std_logic;
+ CFB14 : in std_logic;
+ CFB13 : in std_logic;
+ CFB12 : in std_logic;
+ CFB11 : in std_logic;
+ CFB10 : in std_logic;
+ CFB9 : in std_logic;
+ CFB8 : in std_logic;
+ CFB7 : in std_logic;
+ CFB6 : in std_logic;
+ CFB5 : in std_logic;
+ CFB4 : in std_logic;
+ CFB3 : in std_logic;
+ CFB2 : in std_logic;
+ CFB1 : in std_logic;
+ CFB0 : in std_logic;
+ CIN23 : in std_logic;
+ CIN22 : in std_logic;
+ CIN21 : in std_logic;
+ CIN20 : in std_logic;
+ CIN19 : in std_logic;
+ CIN18 : in std_logic;
+ CIN17 : in std_logic;
+ CIN16 : in std_logic;
+ CIN15 : in std_logic;
+ CIN14 : in std_logic;
+ CIN13 : in std_logic;
+ CIN12 : in std_logic;
+ CIN11 : in std_logic;
+ CIN10 : in std_logic;
+ CIN9 : in std_logic;
+ CIN8 : in std_logic;
+ CIN7 : in std_logic;
+ CIN6 : in std_logic;
+ CIN5 : in std_logic;
+ CIN4 : in std_logic;
+ CIN3 : in std_logic;
+ CIN2 : in std_logic;
+ CIN1 : in std_logic;
+ CIN0 : in std_logic;
+ OPADDNSUB : in std_logic;
+ OPCINSEL : in std_logic;
+ R23 : out std_logic;
+ R22 : out std_logic;
+ R21 : out std_logic;
+ R20 : out std_logic;
+ R19 : out std_logic;
+ R18 : out std_logic;
+ R17 : out std_logic;
+ R16 : out std_logic;
+ R15 : out std_logic;
+ R14 : out std_logic;
+ R13 : out std_logic;
+ R12 : out std_logic;
+ R11 : out std_logic;
+ R10 : out std_logic;
+ R9 : out std_logic;
+ R8 : out std_logic;
+ R7 : out std_logic;
+ R6 : out std_logic;
+ R5 : out std_logic;
+ R4 : out std_logic;
+ R3 : out std_logic;
+ R2 : out std_logic;
+ R1 : out std_logic;
+ R0 : out std_logic;
+ CO23 : out std_logic;
+ CO22 : out std_logic;
+ CO21 : out std_logic;
+ CO20 : out std_logic;
+ CO19 : out std_logic;
+ CO18 : out std_logic;
+ CO17 : out std_logic;
+ CO16 : out std_logic;
+ CO15 : out std_logic;
+ CO14 : out std_logic;
+ CO13 : out std_logic;
+ CO12 : out std_logic;
+ CO11 : out std_logic;
+ CO10 : out std_logic;
+ CO9 : out std_logic;
+ CO8 : out std_logic;
+ CO7 : out std_logic;
+ CO6 : out std_logic;
+ CO5 : out std_logic;
+ CO4 : out std_logic;
+ CO3 : out std_logic;
+ CO2 : out std_logic;
+ CO1 : out std_logic;
+ CO0 : out std_logic );
+end component;
+
+component ALU54B is
generic (
- reg_inputc0_clk : string := "NONE";
- reg_inputc0_ce : string := "CE0";
- reg_inputc0_rst : string := "RST0";
- reg_inputc1_clk : string := "NONE";
- reg_inputc1_ce : string := "CE0";
- reg_inputc1_rst : string := "RST0";
- reg_opcodeop0_0_clk : string := "NONE";
- reg_opcodeop0_0_ce : string := "CE0";
- reg_opcodeop0_0_rst : string := "RST0";
- reg_opcodeop1_0_clk : string := "NONE";
- reg_opcodeop0_1_clk : string := "NONE";
- reg_opcodeop0_1_ce : string := "CE0";
- reg_opcodeop0_1_rst : string := "RST0";
- reg_opcodeop1_1_clk : string := "NONE";
- reg_opcodein_0_clk : string := "NONE";
- reg_opcodein_0_ce : string := "CE0";
- reg_opcodein_0_rst : string := "RST0";
- reg_opcodein_1_clk : string := "NONE";
- reg_opcodein_1_ce : string := "CE0";
- reg_opcodein_1_rst : string := "RST0";
- reg_output0_clk : string := "NONE";
- reg_output0_ce : string := "CE0";
- reg_output0_rst : string := "RST0";
- reg_output1_clk : string := "NONE";
- reg_output1_ce : string := "CE0";
- reg_output1_rst : string := "RST0";
- reg_flag_clk : string := "NONE";
- reg_flag_ce : string := "CE0";
- reg_flag_rst : string := "RST0";
- mcpat_source : string := "STATIC";
- maskpat_source : string := "STATIC";
- mask01 : string := "0x00000000000000";
- reg_inputcfb_clk : string := "NONE";
- reg_inputcfb_ce : string := "CE0";
- reg_inputcfb_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- mcpat : string := "0x00000000000000";
- maskpat : string := "0x00000000000000";
- rndpat : string := "0x00000000000000";
- gsr : string := "ENABLED";
- resetmode : string := "SYNC";
- mult9_mode : string := "DISABLED";
- legacy : string := "DISABLED" );
- port (
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- signedia : in std_logic;
- signedib : in std_logic;
- signedcin : in std_logic;
- a35 : in std_logic;
- a34 : in std_logic;
- a33 : in std_logic;
- a32 : in std_logic;
- a31 : in std_logic;
- a30 : in std_logic;
- a29 : in std_logic;
- a28 : in std_logic;
- a27 : in std_logic;
- a26 : in std_logic;
- a25 : in std_logic;
- a24 : in std_logic;
- a23 : in std_logic;
- a22 : in std_logic;
- a21 : in std_logic;
- a20 : in std_logic;
- a19 : in std_logic;
- a18 : in std_logic;
- a17 : in std_logic;
- a16 : in std_logic;
- a15 : in std_logic;
- a14 : in std_logic;
- a13 : in std_logic;
- a12 : in std_logic;
- a11 : in std_logic;
- a10 : in std_logic;
- a9 : in std_logic;
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b35 : in std_logic;
- b34 : in std_logic;
- b33 : in std_logic;
- b32 : in std_logic;
- b31 : in std_logic;
- b30 : in std_logic;
- b29 : in std_logic;
- b28 : in std_logic;
- b27 : in std_logic;
- b26 : in std_logic;
- b25 : in std_logic;
- b24 : in std_logic;
- b23 : in std_logic;
- b22 : in std_logic;
- b21 : in std_logic;
- b20 : in std_logic;
- b19 : in std_logic;
- b18 : in std_logic;
- b17 : in std_logic;
- b16 : in std_logic;
- b15 : in std_logic;
- b14 : in std_logic;
- b13 : in std_logic;
- b12 : in std_logic;
- b11 : in std_logic;
- b10 : in std_logic;
- b9 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- c53 : in std_logic;
- c52 : in std_logic;
- c51 : in std_logic;
- c50 : in std_logic;
- c49 : in std_logic;
- c48 : in std_logic;
- c47 : in std_logic;
- c46 : in std_logic;
- c45 : in std_logic;
- c44 : in std_logic;
- c43 : in std_logic;
- c42 : in std_logic;
- c41 : in std_logic;
- c40 : in std_logic;
- c39 : in std_logic;
- c38 : in std_logic;
- c37 : in std_logic;
- c36 : in std_logic;
- c35 : in std_logic;
- c34 : in std_logic;
- c33 : in std_logic;
- c32 : in std_logic;
- c31 : in std_logic;
- c30 : in std_logic;
- c29 : in std_logic;
- c28 : in std_logic;
- c27 : in std_logic;
- c26 : in std_logic;
- c25 : in std_logic;
- c24 : in std_logic;
- c23 : in std_logic;
- c22 : in std_logic;
- c21 : in std_logic;
- c20 : in std_logic;
- c19 : in std_logic;
- c18 : in std_logic;
- c17 : in std_logic;
- c16 : in std_logic;
- c15 : in std_logic;
- c14 : in std_logic;
- c13 : in std_logic;
- c12 : in std_logic;
- c11 : in std_logic;
- c10 : in std_logic;
- c9 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- cfb53 : in std_logic;
- cfb52 : in std_logic;
- cfb51 : in std_logic;
- cfb50 : in std_logic;
- cfb49 : in std_logic;
- cfb48 : in std_logic;
- cfb47 : in std_logic;
- cfb46 : in std_logic;
- cfb45 : in std_logic;
- cfb44 : in std_logic;
- cfb43 : in std_logic;
- cfb42 : in std_logic;
- cfb41 : in std_logic;
- cfb40 : in std_logic;
- cfb39 : in std_logic;
- cfb38 : in std_logic;
- cfb37 : in std_logic;
- cfb36 : in std_logic;
- cfb35 : in std_logic;
- cfb34 : in std_logic;
- cfb33 : in std_logic;
- cfb32 : in std_logic;
- cfb31 : in std_logic;
- cfb30 : in std_logic;
- cfb29 : in std_logic;
- cfb28 : in std_logic;
- cfb27 : in std_logic;
- cfb26 : in std_logic;
- cfb25 : in std_logic;
- cfb24 : in std_logic;
- cfb23 : in std_logic;
- cfb22 : in std_logic;
- cfb21 : in std_logic;
- cfb20 : in std_logic;
- cfb19 : in std_logic;
- cfb18 : in std_logic;
- cfb17 : in std_logic;
- cfb16 : in std_logic;
- cfb15 : in std_logic;
- cfb14 : in std_logic;
- cfb13 : in std_logic;
- cfb12 : in std_logic;
- cfb11 : in std_logic;
- cfb10 : in std_logic;
- cfb9 : in std_logic;
- cfb8 : in std_logic;
- cfb7 : in std_logic;
- cfb6 : in std_logic;
- cfb5 : in std_logic;
- cfb4 : in std_logic;
- cfb3 : in std_logic;
- cfb2 : in std_logic;
- cfb1 : in std_logic;
- cfb0 : in std_logic;
- ma35 : in std_logic;
- ma34 : in std_logic;
- ma33 : in std_logic;
- ma32 : in std_logic;
- ma31 : in std_logic;
- ma30 : in std_logic;
- ma29 : in std_logic;
- ma28 : in std_logic;
- ma27 : in std_logic;
- ma26 : in std_logic;
- ma25 : in std_logic;
- ma24 : in std_logic;
- ma23 : in std_logic;
- ma22 : in std_logic;
- ma21 : in std_logic;
- ma20 : in std_logic;
- ma19 : in std_logic;
- ma18 : in std_logic;
- ma17 : in std_logic;
- ma16 : in std_logic;
- ma15 : in std_logic;
- ma14 : in std_logic;
- ma13 : in std_logic;
- ma12 : in std_logic;
- ma11 : in std_logic;
- ma10 : in std_logic;
- ma9 : in std_logic;
- ma8 : in std_logic;
- ma7 : in std_logic;
- ma6 : in std_logic;
- ma5 : in std_logic;
- ma4 : in std_logic;
- ma3 : in std_logic;
- ma2 : in std_logic;
- ma1 : in std_logic;
- ma0 : in std_logic;
- mb35 : in std_logic;
- mb34 : in std_logic;
- mb33 : in std_logic;
- mb32 : in std_logic;
- mb31 : in std_logic;
- mb30 : in std_logic;
- mb29 : in std_logic;
- mb28 : in std_logic;
- mb27 : in std_logic;
- mb26 : in std_logic;
- mb25 : in std_logic;
- mb24 : in std_logic;
- mb23 : in std_logic;
- mb22 : in std_logic;
- mb21 : in std_logic;
- mb20 : in std_logic;
- mb19 : in std_logic;
- mb18 : in std_logic;
- mb17 : in std_logic;
- mb16 : in std_logic;
- mb15 : in std_logic;
- mb14 : in std_logic;
- mb13 : in std_logic;
- mb12 : in std_logic;
- mb11 : in std_logic;
- mb10 : in std_logic;
- mb9 : in std_logic;
- mb8 : in std_logic;
- mb7 : in std_logic;
- mb6 : in std_logic;
- mb5 : in std_logic;
- mb4 : in std_logic;
- mb3 : in std_logic;
- mb2 : in std_logic;
- mb1 : in std_logic;
- mb0 : in std_logic;
- cin53 : in std_logic;
- cin52 : in std_logic;
- cin51 : in std_logic;
- cin50 : in std_logic;
- cin49 : in std_logic;
- cin48 : in std_logic;
- cin47 : in std_logic;
- cin46 : in std_logic;
- cin45 : in std_logic;
- cin44 : in std_logic;
- cin43 : in std_logic;
- cin42 : in std_logic;
- cin41 : in std_logic;
- cin40 : in std_logic;
- cin39 : in std_logic;
- cin38 : in std_logic;
- cin37 : in std_logic;
- cin36 : in std_logic;
- cin35 : in std_logic;
- cin34 : in std_logic;
- cin33 : in std_logic;
- cin32 : in std_logic;
- cin31 : in std_logic;
- cin30 : in std_logic;
- cin29 : in std_logic;
- cin28 : in std_logic;
- cin27 : in std_logic;
- cin26 : in std_logic;
- cin25 : in std_logic;
- cin24 : in std_logic;
- cin23 : in std_logic;
- cin22 : in std_logic;
- cin21 : in std_logic;
- cin20 : in std_logic;
- cin19 : in std_logic;
- cin18 : in std_logic;
- cin17 : in std_logic;
- cin16 : in std_logic;
- cin15 : in std_logic;
- cin14 : in std_logic;
- cin13 : in std_logic;
- cin12 : in std_logic;
- cin11 : in std_logic;
- cin10 : in std_logic;
- cin9 : in std_logic;
- cin8 : in std_logic;
- cin7 : in std_logic;
- cin6 : in std_logic;
- cin5 : in std_logic;
- cin4 : in std_logic;
- cin3 : in std_logic;
- cin2 : in std_logic;
- cin1 : in std_logic;
- cin0 : in std_logic;
- op10 : in std_logic;
- op9 : in std_logic;
- op8 : in std_logic;
- op7 : in std_logic;
- op6 : in std_logic;
- op5 : in std_logic;
- op4 : in std_logic;
- op3 : in std_logic;
- op2 : in std_logic;
- op1 : in std_logic;
- op0 : in std_logic;
- r53 : out std_logic;
- r52 : out std_logic;
- r51 : out std_logic;
- r50 : out std_logic;
- r49 : out std_logic;
- r48 : out std_logic;
- r47 : out std_logic;
- r46 : out std_logic;
- r45 : out std_logic;
- r44 : out std_logic;
- r43 : out std_logic;
- r42 : out std_logic;
- r41 : out std_logic;
- r40 : out std_logic;
- r39 : out std_logic;
- r38 : out std_logic;
- r37 : out std_logic;
- r36 : out std_logic;
- r35 : out std_logic;
- r34 : out std_logic;
- r33 : out std_logic;
- r32 : out std_logic;
- r31 : out std_logic;
- r30 : out std_logic;
- r29 : out std_logic;
- r28 : out std_logic;
- r27 : out std_logic;
- r26 : out std_logic;
- r25 : out std_logic;
- r24 : out std_logic;
- r23 : out std_logic;
- r22 : out std_logic;
- r21 : out std_logic;
- r20 : out std_logic;
- r19 : out std_logic;
- r18 : out std_logic;
- r17 : out std_logic;
- r16 : out std_logic;
- r15 : out std_logic;
- r14 : out std_logic;
- r13 : out std_logic;
- r12 : out std_logic;
- r11 : out std_logic;
- r10 : out std_logic;
- r9 : out std_logic;
- r8 : out std_logic;
- r7 : out std_logic;
- r6 : out std_logic;
- r5 : out std_logic;
- r4 : out std_logic;
- r3 : out std_logic;
- r2 : out std_logic;
- r1 : out std_logic;
- r0 : out std_logic;
- co53 : out std_logic;
- co52 : out std_logic;
- co51 : out std_logic;
- co50 : out std_logic;
- co49 : out std_logic;
- co48 : out std_logic;
- co47 : out std_logic;
- co46 : out std_logic;
- co45 : out std_logic;
- co44 : out std_logic;
- co43 : out std_logic;
- co42 : out std_logic;
- co41 : out std_logic;
- co40 : out std_logic;
- co39 : out std_logic;
- co38 : out std_logic;
- co37 : out std_logic;
- co36 : out std_logic;
- co35 : out std_logic;
- co34 : out std_logic;
- co33 : out std_logic;
- co32 : out std_logic;
- co31 : out std_logic;
- co30 : out std_logic;
- co29 : out std_logic;
- co28 : out std_logic;
- co27 : out std_logic;
- co26 : out std_logic;
- co25 : out std_logic;
- co24 : out std_logic;
- co23 : out std_logic;
- co22 : out std_logic;
- co21 : out std_logic;
- co20 : out std_logic;
- co19 : out std_logic;
- co18 : out std_logic;
- co17 : out std_logic;
- co16 : out std_logic;
- co15 : out std_logic;
- co14 : out std_logic;
- co13 : out std_logic;
- co12 : out std_logic;
- co11 : out std_logic;
- co10 : out std_logic;
- co9 : out std_logic;
- co8 : out std_logic;
- co7 : out std_logic;
- co6 : out std_logic;
- co5 : out std_logic;
- co4 : out std_logic;
- co3 : out std_logic;
- co2 : out std_logic;
- co1 : out std_logic;
- co0 : out std_logic;
- eqz : out std_logic;
- eqzm : out std_logic;
- eqom : out std_logic;
- eqpat : out std_logic;
- eqpatb : out std_logic;
- over : out std_logic;
- under : out std_logic;
- overunder : out std_logic;
- signedr : out std_logic );
-end component;
-
-component pradd9a is
+ REG_INPUTC0_CLK : string := "NONE";
+ REG_INPUTC0_CE : string := "CE0";
+ REG_INPUTC0_RST : string := "RST0";
+ REG_INPUTC1_CLK : string := "NONE";
+ REG_INPUTC1_CE : string := "CE0";
+ REG_INPUTC1_RST : string := "RST0";
+ REG_OPCODEOP0_0_CLK : string := "NONE";
+ REG_OPCODEOP0_0_CE : string := "CE0";
+ REG_OPCODEOP0_0_RST : string := "RST0";
+ REG_OPCODEOP1_0_CLK : string := "NONE";
+ REG_OPCODEOP0_1_CLK : string := "NONE";
+ REG_OPCODEOP0_1_CE : string := "CE0";
+ REG_OPCODEOP0_1_RST : string := "RST0";
+ REG_OPCODEOP1_1_CLK : string := "NONE";
+ REG_OPCODEIN_0_CLK : string := "NONE";
+ REG_OPCODEIN_0_CE : string := "CE0";
+ REG_OPCODEIN_0_RST : string := "RST0";
+ REG_OPCODEIN_1_CLK : string := "NONE";
+ REG_OPCODEIN_1_CE : string := "CE0";
+ REG_OPCODEIN_1_RST : string := "RST0";
+ REG_OUTPUT0_CLK : string := "NONE";
+ REG_OUTPUT0_CE : string := "CE0";
+ REG_OUTPUT0_RST : string := "RST0";
+ REG_OUTPUT1_CLK : string := "NONE";
+ REG_OUTPUT1_CE : string := "CE0";
+ REG_OUTPUT1_RST : string := "RST0";
+ REG_FLAG_CLK : string := "NONE";
+ REG_FLAG_CE : string := "CE0";
+ REG_FLAG_RST : string := "RST0";
+ MCPAT_SOURCE : string := "STATIC";
+ MASKPAT_SOURCE : string := "STATIC";
+ MASK01 : string := "0x00000000000000";
+ REG_INPUTCFB_CLK : string := "NONE";
+ REG_INPUTCFB_CE : string := "CE0";
+ REG_INPUTCFB_RST : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ MCPAT : string := "0x00000000000000";
+ MASKPAT : string := "0x00000000000000";
+ RNDPAT : string := "0x00000000000000";
+ GSR : string := "ENABLED";
+ RESETMODE : string := "SYNC";
+ MULT9_MODE : string := "DISABLED";
+ LEGACY : string := "DISABLED" );
+ port (
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SIGNEDIA : in std_logic;
+ SIGNEDIB : in std_logic;
+ SIGNEDCIN : in std_logic;
+ A35 : in std_logic;
+ A34 : in std_logic;
+ A33 : in std_logic;
+ A32 : in std_logic;
+ A31 : in std_logic;
+ A30 : in std_logic;
+ A29 : in std_logic;
+ A28 : in std_logic;
+ A27 : in std_logic;
+ A26 : in std_logic;
+ A25 : in std_logic;
+ A24 : in std_logic;
+ A23 : in std_logic;
+ A22 : in std_logic;
+ A21 : in std_logic;
+ A20 : in std_logic;
+ A19 : in std_logic;
+ A18 : in std_logic;
+ A17 : in std_logic;
+ A16 : in std_logic;
+ A15 : in std_logic;
+ A14 : in std_logic;
+ A13 : in std_logic;
+ A12 : in std_logic;
+ A11 : in std_logic;
+ A10 : in std_logic;
+ A9 : in std_logic;
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B35 : in std_logic;
+ B34 : in std_logic;
+ B33 : in std_logic;
+ B32 : in std_logic;
+ B31 : in std_logic;
+ B30 : in std_logic;
+ B29 : in std_logic;
+ B28 : in std_logic;
+ B27 : in std_logic;
+ B26 : in std_logic;
+ B25 : in std_logic;
+ B24 : in std_logic;
+ B23 : in std_logic;
+ B22 : in std_logic;
+ B21 : in std_logic;
+ B20 : in std_logic;
+ B19 : in std_logic;
+ B18 : in std_logic;
+ B17 : in std_logic;
+ B16 : in std_logic;
+ B15 : in std_logic;
+ B14 : in std_logic;
+ B13 : in std_logic;
+ B12 : in std_logic;
+ B11 : in std_logic;
+ B10 : in std_logic;
+ B9 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ C53 : in std_logic;
+ C52 : in std_logic;
+ C51 : in std_logic;
+ C50 : in std_logic;
+ C49 : in std_logic;
+ C48 : in std_logic;
+ C47 : in std_logic;
+ C46 : in std_logic;
+ C45 : in std_logic;
+ C44 : in std_logic;
+ C43 : in std_logic;
+ C42 : in std_logic;
+ C41 : in std_logic;
+ C40 : in std_logic;
+ C39 : in std_logic;
+ C38 : in std_logic;
+ C37 : in std_logic;
+ C36 : in std_logic;
+ C35 : in std_logic;
+ C34 : in std_logic;
+ C33 : in std_logic;
+ C32 : in std_logic;
+ C31 : in std_logic;
+ C30 : in std_logic;
+ C29 : in std_logic;
+ C28 : in std_logic;
+ C27 : in std_logic;
+ C26 : in std_logic;
+ C25 : in std_logic;
+ C24 : in std_logic;
+ C23 : in std_logic;
+ C22 : in std_logic;
+ C21 : in std_logic;
+ C20 : in std_logic;
+ C19 : in std_logic;
+ C18 : in std_logic;
+ C17 : in std_logic;
+ C16 : in std_logic;
+ C15 : in std_logic;
+ C14 : in std_logic;
+ C13 : in std_logic;
+ C12 : in std_logic;
+ C11 : in std_logic;
+ C10 : in std_logic;
+ C9 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ CFB53 : in std_logic;
+ CFB52 : in std_logic;
+ CFB51 : in std_logic;
+ CFB50 : in std_logic;
+ CFB49 : in std_logic;
+ CFB48 : in std_logic;
+ CFB47 : in std_logic;
+ CFB46 : in std_logic;
+ CFB45 : in std_logic;
+ CFB44 : in std_logic;
+ CFB43 : in std_logic;
+ CFB42 : in std_logic;
+ CFB41 : in std_logic;
+ CFB40 : in std_logic;
+ CFB39 : in std_logic;
+ CFB38 : in std_logic;
+ CFB37 : in std_logic;
+ CFB36 : in std_logic;
+ CFB35 : in std_logic;
+ CFB34 : in std_logic;
+ CFB33 : in std_logic;
+ CFB32 : in std_logic;
+ CFB31 : in std_logic;
+ CFB30 : in std_logic;
+ CFB29 : in std_logic;
+ CFB28 : in std_logic;
+ CFB27 : in std_logic;
+ CFB26 : in std_logic;
+ CFB25 : in std_logic;
+ CFB24 : in std_logic;
+ CFB23 : in std_logic;
+ CFB22 : in std_logic;
+ CFB21 : in std_logic;
+ CFB20 : in std_logic;
+ CFB19 : in std_logic;
+ CFB18 : in std_logic;
+ CFB17 : in std_logic;
+ CFB16 : in std_logic;
+ CFB15 : in std_logic;
+ CFB14 : in std_logic;
+ CFB13 : in std_logic;
+ CFB12 : in std_logic;
+ CFB11 : in std_logic;
+ CFB10 : in std_logic;
+ CFB9 : in std_logic;
+ CFB8 : in std_logic;
+ CFB7 : in std_logic;
+ CFB6 : in std_logic;
+ CFB5 : in std_logic;
+ CFB4 : in std_logic;
+ CFB3 : in std_logic;
+ CFB2 : in std_logic;
+ CFB1 : in std_logic;
+ CFB0 : in std_logic;
+ MA35 : in std_logic;
+ MA34 : in std_logic;
+ MA33 : in std_logic;
+ MA32 : in std_logic;
+ MA31 : in std_logic;
+ MA30 : in std_logic;
+ MA29 : in std_logic;
+ MA28 : in std_logic;
+ MA27 : in std_logic;
+ MA26 : in std_logic;
+ MA25 : in std_logic;
+ MA24 : in std_logic;
+ MA23 : in std_logic;
+ MA22 : in std_logic;
+ MA21 : in std_logic;
+ MA20 : in std_logic;
+ MA19 : in std_logic;
+ MA18 : in std_logic;
+ MA17 : in std_logic;
+ MA16 : in std_logic;
+ MA15 : in std_logic;
+ MA14 : in std_logic;
+ MA13 : in std_logic;
+ MA12 : in std_logic;
+ MA11 : in std_logic;
+ MA10 : in std_logic;
+ MA9 : in std_logic;
+ MA8 : in std_logic;
+ MA7 : in std_logic;
+ MA6 : in std_logic;
+ MA5 : in std_logic;
+ MA4 : in std_logic;
+ MA3 : in std_logic;
+ MA2 : in std_logic;
+ MA1 : in std_logic;
+ MA0 : in std_logic;
+ MB35 : in std_logic;
+ MB34 : in std_logic;
+ MB33 : in std_logic;
+ MB32 : in std_logic;
+ MB31 : in std_logic;
+ MB30 : in std_logic;
+ MB29 : in std_logic;
+ MB28 : in std_logic;
+ MB27 : in std_logic;
+ MB26 : in std_logic;
+ MB25 : in std_logic;
+ MB24 : in std_logic;
+ MB23 : in std_logic;
+ MB22 : in std_logic;
+ MB21 : in std_logic;
+ MB20 : in std_logic;
+ MB19 : in std_logic;
+ MB18 : in std_logic;
+ MB17 : in std_logic;
+ MB16 : in std_logic;
+ MB15 : in std_logic;
+ MB14 : in std_logic;
+ MB13 : in std_logic;
+ MB12 : in std_logic;
+ MB11 : in std_logic;
+ MB10 : in std_logic;
+ MB9 : in std_logic;
+ MB8 : in std_logic;
+ MB7 : in std_logic;
+ MB6 : in std_logic;
+ MB5 : in std_logic;
+ MB4 : in std_logic;
+ MB3 : in std_logic;
+ MB2 : in std_logic;
+ MB1 : in std_logic;
+ MB0 : in std_logic;
+ CIN53 : in std_logic;
+ CIN52 : in std_logic;
+ CIN51 : in std_logic;
+ CIN50 : in std_logic;
+ CIN49 : in std_logic;
+ CIN48 : in std_logic;
+ CIN47 : in std_logic;
+ CIN46 : in std_logic;
+ CIN45 : in std_logic;
+ CIN44 : in std_logic;
+ CIN43 : in std_logic;
+ CIN42 : in std_logic;
+ CIN41 : in std_logic;
+ CIN40 : in std_logic;
+ CIN39 : in std_logic;
+ CIN38 : in std_logic;
+ CIN37 : in std_logic;
+ CIN36 : in std_logic;
+ CIN35 : in std_logic;
+ CIN34 : in std_logic;
+ CIN33 : in std_logic;
+ CIN32 : in std_logic;
+ CIN31 : in std_logic;
+ CIN30 : in std_logic;
+ CIN29 : in std_logic;
+ CIN28 : in std_logic;
+ CIN27 : in std_logic;
+ CIN26 : in std_logic;
+ CIN25 : in std_logic;
+ CIN24 : in std_logic;
+ CIN23 : in std_logic;
+ CIN22 : in std_logic;
+ CIN21 : in std_logic;
+ CIN20 : in std_logic;
+ CIN19 : in std_logic;
+ CIN18 : in std_logic;
+ CIN17 : in std_logic;
+ CIN16 : in std_logic;
+ CIN15 : in std_logic;
+ CIN14 : in std_logic;
+ CIN13 : in std_logic;
+ CIN12 : in std_logic;
+ CIN11 : in std_logic;
+ CIN10 : in std_logic;
+ CIN9 : in std_logic;
+ CIN8 : in std_logic;
+ CIN7 : in std_logic;
+ CIN6 : in std_logic;
+ CIN5 : in std_logic;
+ CIN4 : in std_logic;
+ CIN3 : in std_logic;
+ CIN2 : in std_logic;
+ CIN1 : in std_logic;
+ CIN0 : in std_logic;
+ OP10 : in std_logic;
+ OP9 : in std_logic;
+ OP8 : in std_logic;
+ OP7 : in std_logic;
+ OP6 : in std_logic;
+ OP5 : in std_logic;
+ OP4 : in std_logic;
+ OP3 : in std_logic;
+ OP2 : in std_logic;
+ OP1 : in std_logic;
+ OP0 : in std_logic;
+ R53 : out std_logic;
+ R52 : out std_logic;
+ R51 : out std_logic;
+ R50 : out std_logic;
+ R49 : out std_logic;
+ R48 : out std_logic;
+ R47 : out std_logic;
+ R46 : out std_logic;
+ R45 : out std_logic;
+ R44 : out std_logic;
+ R43 : out std_logic;
+ R42 : out std_logic;
+ R41 : out std_logic;
+ R40 : out std_logic;
+ R39 : out std_logic;
+ R38 : out std_logic;
+ R37 : out std_logic;
+ R36 : out std_logic;
+ R35 : out std_logic;
+ R34 : out std_logic;
+ R33 : out std_logic;
+ R32 : out std_logic;
+ R31 : out std_logic;
+ R30 : out std_logic;
+ R29 : out std_logic;
+ R28 : out std_logic;
+ R27 : out std_logic;
+ R26 : out std_logic;
+ R25 : out std_logic;
+ R24 : out std_logic;
+ R23 : out std_logic;
+ R22 : out std_logic;
+ R21 : out std_logic;
+ R20 : out std_logic;
+ R19 : out std_logic;
+ R18 : out std_logic;
+ R17 : out std_logic;
+ R16 : out std_logic;
+ R15 : out std_logic;
+ R14 : out std_logic;
+ R13 : out std_logic;
+ R12 : out std_logic;
+ R11 : out std_logic;
+ R10 : out std_logic;
+ R9 : out std_logic;
+ R8 : out std_logic;
+ R7 : out std_logic;
+ R6 : out std_logic;
+ R5 : out std_logic;
+ R4 : out std_logic;
+ R3 : out std_logic;
+ R2 : out std_logic;
+ R1 : out std_logic;
+ R0 : out std_logic;
+ CO53 : out std_logic;
+ CO52 : out std_logic;
+ CO51 : out std_logic;
+ CO50 : out std_logic;
+ CO49 : out std_logic;
+ CO48 : out std_logic;
+ CO47 : out std_logic;
+ CO46 : out std_logic;
+ CO45 : out std_logic;
+ CO44 : out std_logic;
+ CO43 : out std_logic;
+ CO42 : out std_logic;
+ CO41 : out std_logic;
+ CO40 : out std_logic;
+ CO39 : out std_logic;
+ CO38 : out std_logic;
+ CO37 : out std_logic;
+ CO36 : out std_logic;
+ CO35 : out std_logic;
+ CO34 : out std_logic;
+ CO33 : out std_logic;
+ CO32 : out std_logic;
+ CO31 : out std_logic;
+ CO30 : out std_logic;
+ CO29 : out std_logic;
+ CO28 : out std_logic;
+ CO27 : out std_logic;
+ CO26 : out std_logic;
+ CO25 : out std_logic;
+ CO24 : out std_logic;
+ CO23 : out std_logic;
+ CO22 : out std_logic;
+ CO21 : out std_logic;
+ CO20 : out std_logic;
+ CO19 : out std_logic;
+ CO18 : out std_logic;
+ CO17 : out std_logic;
+ CO16 : out std_logic;
+ CO15 : out std_logic;
+ CO14 : out std_logic;
+ CO13 : out std_logic;
+ CO12 : out std_logic;
+ CO11 : out std_logic;
+ CO10 : out std_logic;
+ CO9 : out std_logic;
+ CO8 : out std_logic;
+ CO7 : out std_logic;
+ CO6 : out std_logic;
+ CO5 : out std_logic;
+ CO4 : out std_logic;
+ CO3 : out std_logic;
+ CO2 : out std_logic;
+ CO1 : out std_logic;
+ CO0 : out std_logic;
+ EQZ : out std_logic;
+ EQZM : out std_logic;
+ EQOM : out std_logic;
+ EQPAT : out std_logic;
+ EQPATB : out std_logic;
+ OVER : out std_logic;
+ UNDER : out std_logic;
+ OVERUNDER : out std_logic;
+ SIGNEDR : out std_logic );
+end component;
+
+component PRADD9A is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_inputc_clk : string := "NONE";
- reg_inputc_ce : string := "CE0";
- reg_inputc_rst : string := "RST0";
- reg_oppre_clk : string := "NONE";
- reg_oppre_ce : string := "CE0";
- reg_oppre_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- highspeed_clk : string := "NONE";
- gsr : string := "ENABLED";
- cas_match_reg : string := "FALSE";
- sourcea_mode : string := "A_SHIFT";
- sourceb_mode : string := "SHIFT";
- fb_mux : string := "SHIFT";
- resetmode : string := "SYNC";
- symmetry_mode : string := "DIRECT" );
- port (
- pa8 : in std_logic;
- pa7 : in std_logic;
- pa6 : in std_logic;
- pa5 : in std_logic;
- pa4 : in std_logic;
- pa3 : in std_logic;
- pa2 : in std_logic;
- pa1 : in std_logic;
- pa0 : in std_logic;
- pb8 : in std_logic;
- pb7 : in std_logic;
- pb6 : in std_logic;
- pb5 : in std_logic;
- pb4 : in std_logic;
- pb3 : in std_logic;
- pb2 : in std_logic;
- pb1 : in std_logic;
- pb0 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- sourcea : in std_logic;
- oppre : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- po8 : out std_logic;
- po7 : out std_logic;
- po6 : out std_logic;
- po5 : out std_logic;
- po4 : out std_logic;
- po3 : out std_logic;
- po2 : out std_logic;
- po1 : out std_logic;
- po0 : out std_logic );
-end component;
-
-component pradd18a is
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_INPUTC_CLK : string := "NONE";
+ REG_INPUTC_CE : string := "CE0";
+ REG_INPUTC_RST : string := "RST0";
+ REG_OPPRE_CLK : string := "NONE";
+ REG_OPPRE_CE : string := "CE0";
+ REG_OPPRE_RST : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ HIGHSPEED_CLK : string := "NONE";
+ GSR : string := "ENABLED";
+ CAS_MATCH_REG : string := "FALSE";
+ SOURCEA_MODE : string := "A_SHIFT";
+ SOURCEB_MODE : string := "SHIFT";
+ FB_MUX : string := "SHIFT";
+ RESETMODE : string := "SYNC";
+ SYMMETRY_MODE : string := "DIRECT" );
+ port (
+ PA8 : in std_logic;
+ PA7 : in std_logic;
+ PA6 : in std_logic;
+ PA5 : in std_logic;
+ PA4 : in std_logic;
+ PA3 : in std_logic;
+ PA2 : in std_logic;
+ PA1 : in std_logic;
+ PA0 : in std_logic;
+ PB8 : in std_logic;
+ PB7 : in std_logic;
+ PB6 : in std_logic;
+ PB5 : in std_logic;
+ PB4 : in std_logic;
+ PB3 : in std_logic;
+ PB2 : in std_logic;
+ PB1 : in std_logic;
+ PB0 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ SOURCEA : in std_logic;
+ OPPRE : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ PO8 : out std_logic;
+ PO7 : out std_logic;
+ PO6 : out std_logic;
+ PO5 : out std_logic;
+ PO4 : out std_logic;
+ PO3 : out std_logic;
+ PO2 : out std_logic;
+ PO1 : out std_logic;
+ PO0 : out std_logic );
+end component;
+
+component PRADD18A is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_inputc_clk : string := "NONE";
- reg_inputc_ce : string := "CE0";
- reg_inputc_rst : string := "RST0";
- reg_oppre_clk : string := "NONE";
- reg_oppre_ce : string := "CE0";
- reg_oppre_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- highspeed_clk : string := "NONE";
- gsr : string := "ENABLED";
- cas_match_reg : string := "FALSE";
- sourcea_mode : string := "A_SHIFT";
- sourceb_mode : string := "SHIFT";
- fb_mux : string := "SHIFT";
- resetmode : string := "SYNC";
- symmetry_mode : string := "DIRECT" );
- port (
- pa17 : in std_logic;
- pa16 : in std_logic;
- pa15 : in std_logic;
- pa14 : in std_logic;
- pa13 : in std_logic;
- pa12 : in std_logic;
- pa11 : in std_logic;
- pa10 : in std_logic;
- pa9 : in std_logic;
- pa8 : in std_logic;
- pa7 : in std_logic;
- pa6 : in std_logic;
- pa5 : in std_logic;
- pa4 : in std_logic;
- pa3 : in std_logic;
- pa2 : in std_logic;
- pa1 : in std_logic;
- pa0 : in std_logic;
- pb17 : in std_logic;
- pb16 : in std_logic;
- pb15 : in std_logic;
- pb14 : in std_logic;
- pb13 : in std_logic;
- pb12 : in std_logic;
- pb11 : in std_logic;
- pb10 : in std_logic;
- pb9 : in std_logic;
- pb8 : in std_logic;
- pb7 : in std_logic;
- pb6 : in std_logic;
- pb5 : in std_logic;
- pb4 : in std_logic;
- pb3 : in std_logic;
- pb2 : in std_logic;
- pb1 : in std_logic;
- pb0 : in std_logic;
- sria17 : in std_logic;
- sria16 : in std_logic;
- sria15 : in std_logic;
- sria14 : in std_logic;
- sria13 : in std_logic;
- sria12 : in std_logic;
- sria11 : in std_logic;
- sria10 : in std_logic;
- sria9 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib17 : in std_logic;
- srib16 : in std_logic;
- srib15 : in std_logic;
- srib14 : in std_logic;
- srib13 : in std_logic;
- srib12 : in std_logic;
- srib11 : in std_logic;
- srib10 : in std_logic;
- srib9 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- c17 : in std_logic;
- c16 : in std_logic;
- c15 : in std_logic;
- c14 : in std_logic;
- c13 : in std_logic;
- c12 : in std_logic;
- c11 : in std_logic;
- c10 : in std_logic;
- c9 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- sourcea : in std_logic;
- oppre : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sroa17 : out std_logic;
- sroa16 : out std_logic;
- sroa15 : out std_logic;
- sroa14 : out std_logic;
- sroa13 : out std_logic;
- sroa12 : out std_logic;
- sroa11 : out std_logic;
- sroa10 : out std_logic;
- sroa9 : out std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob17 : out std_logic;
- srob16 : out std_logic;
- srob15 : out std_logic;
- srob14 : out std_logic;
- srob13 : out std_logic;
- srob12 : out std_logic;
- srob11 : out std_logic;
- srob10 : out std_logic;
- srob9 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- po17 : out std_logic;
- po16 : out std_logic;
- po15 : out std_logic;
- po14 : out std_logic;
- po13 : out std_logic;
- po12 : out std_logic;
- po11 : out std_logic;
- po10 : out std_logic;
- po9 : out std_logic;
- po8 : out std_logic;
- po7 : out std_logic;
- po6 : out std_logic;
- po5 : out std_logic;
- po4 : out std_logic;
- po3 : out std_logic;
- po2 : out std_logic;
- po1 : out std_logic;
- po0 : out std_logic );
-end component;
-
-component dp16kd is
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_INPUTC_CLK : string := "NONE";
+ REG_INPUTC_CE : string := "CE0";
+ REG_INPUTC_RST : string := "RST0";
+ REG_OPPRE_CLK : string := "NONE";
+ REG_OPPRE_CE : string := "CE0";
+ REG_OPPRE_RST : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ HIGHSPEED_CLK : string := "NONE";
+ GSR : string := "ENABLED";
+ CAS_MATCH_REG : string := "FALSE";
+ SOURCEA_MODE : string := "A_SHIFT";
+ SOURCEB_MODE : string := "SHIFT";
+ FB_MUX : string := "SHIFT";
+ RESETMODE : string := "SYNC";
+ SYMMETRY_MODE : string := "DIRECT" );
+ port (
+ PA17 : in std_logic;
+ PA16 : in std_logic;
+ PA15 : in std_logic;
+ PA14 : in std_logic;
+ PA13 : in std_logic;
+ PA12 : in std_logic;
+ PA11 : in std_logic;
+ PA10 : in std_logic;
+ PA9 : in std_logic;
+ PA8 : in std_logic;
+ PA7 : in std_logic;
+ PA6 : in std_logic;
+ PA5 : in std_logic;
+ PA4 : in std_logic;
+ PA3 : in std_logic;
+ PA2 : in std_logic;
+ PA1 : in std_logic;
+ PA0 : in std_logic;
+ PB17 : in std_logic;
+ PB16 : in std_logic;
+ PB15 : in std_logic;
+ PB14 : in std_logic;
+ PB13 : in std_logic;
+ PB12 : in std_logic;
+ PB11 : in std_logic;
+ PB10 : in std_logic;
+ PB9 : in std_logic;
+ PB8 : in std_logic;
+ PB7 : in std_logic;
+ PB6 : in std_logic;
+ PB5 : in std_logic;
+ PB4 : in std_logic;
+ PB3 : in std_logic;
+ PB2 : in std_logic;
+ PB1 : in std_logic;
+ PB0 : in std_logic;
+ SRIA17 : in std_logic;
+ SRIA16 : in std_logic;
+ SRIA15 : in std_logic;
+ SRIA14 : in std_logic;
+ SRIA13 : in std_logic;
+ SRIA12 : in std_logic;
+ SRIA11 : in std_logic;
+ SRIA10 : in std_logic;
+ SRIA9 : in std_logic;
+ SRIA8 : in std_logic;
+ SRIA7 : in std_logic;
+ SRIA6 : in std_logic;
+ SRIA5 : in std_logic;
+ SRIA4 : in std_logic;
+ SRIA3 : in std_logic;
+ SRIA2 : in std_logic;
+ SRIA1 : in std_logic;
+ SRIA0 : in std_logic;
+ SRIB17 : in std_logic;
+ SRIB16 : in std_logic;
+ SRIB15 : in std_logic;
+ SRIB14 : in std_logic;
+ SRIB13 : in std_logic;
+ SRIB12 : in std_logic;
+ SRIB11 : in std_logic;
+ SRIB10 : in std_logic;
+ SRIB9 : in std_logic;
+ SRIB8 : in std_logic;
+ SRIB7 : in std_logic;
+ SRIB6 : in std_logic;
+ SRIB5 : in std_logic;
+ SRIB4 : in std_logic;
+ SRIB3 : in std_logic;
+ SRIB2 : in std_logic;
+ SRIB1 : in std_logic;
+ SRIB0 : in std_logic;
+ C17 : in std_logic;
+ C16 : in std_logic;
+ C15 : in std_logic;
+ C14 : in std_logic;
+ C13 : in std_logic;
+ C12 : in std_logic;
+ C11 : in std_logic;
+ C10 : in std_logic;
+ C9 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ SOURCEA : in std_logic;
+ OPPRE : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ SROA17 : out std_logic;
+ SROA16 : out std_logic;
+ SROA15 : out std_logic;
+ SROA14 : out std_logic;
+ SROA13 : out std_logic;
+ SROA12 : out std_logic;
+ SROA11 : out std_logic;
+ SROA10 : out std_logic;
+ SROA9 : out std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB17 : out std_logic;
+ SROB16 : out std_logic;
+ SROB15 : out std_logic;
+ SROB14 : out std_logic;
+ SROB13 : out std_logic;
+ SROB12 : out std_logic;
+ SROB11 : out std_logic;
+ SROB10 : out std_logic;
+ SROB9 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ PO17 : out std_logic;
+ PO16 : out std_logic;
+ PO15 : out std_logic;
+ PO14 : out std_logic;
+ PO13 : out std_logic;
+ PO12 : out std_logic;
+ PO11 : out std_logic;
+ PO10 : out std_logic;
+ PO9 : out std_logic;
+ PO8 : out std_logic;
+ PO7 : out std_logic;
+ PO6 : out std_logic;
+ PO5 : out std_logic;
+ PO4 : out std_logic;
+ PO3 : out std_logic;
+ PO2 : out std_logic;
+ PO1 : out std_logic;
+ PO0 : out std_logic );
+end component;
+
+component DP16KD is
generic (
- data_width_a : integer := 18;
- data_width_b : integer := 18;
- regmode_a : string := "NOREG";
- regmode_b : string := "NOREG";
- resetmode : string := "SYNC";
- async_reset_release : string := "SYNC";
- writemode_a : string := "NORMAL";
- writemode_b : string := "NORMAL";
- csdecode_a : string := "0b000";
- csdecode_b : string := "0b000";
- gsr : string := "ENABLED";
- initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- init_data : string := "STATIC" );
- port (
- dia17 : in std_logic;
- dia16 : in std_logic;
- dia15 : in std_logic;
- dia14 : in std_logic;
- dia13 : in std_logic;
- dia12 : in std_logic;
- dia11 : in std_logic;
- dia10 : in std_logic;
- dia9 : in std_logic;
- dia8 : in std_logic;
- dia7 : in std_logic;
- dia6 : in std_logic;
- dia5 : in std_logic;
- dia4 : in std_logic;
- dia3 : in std_logic;
- dia2 : in std_logic;
- dia1 : in std_logic;
- dia0 : in std_logic;
- ada13 : in std_logic;
- ada12 : in std_logic;
- ada11 : in std_logic;
- ada10 : in std_logic;
- ada9 : in std_logic;
- ada8 : in std_logic;
- ada7 : in std_logic;
- ada6 : in std_logic;
- ada5 : in std_logic;
- ada4 : in std_logic;
- ada3 : in std_logic;
- ada2 : in std_logic;
- ada1 : in std_logic;
- ada0 : in std_logic;
- cea : in std_logic;
- ocea : in std_logic;
- clka : in std_logic;
- wea : in std_logic;
- csa2 : in std_logic;
- csa1 : in std_logic;
- csa0 : in std_logic;
- rsta : in std_logic;
- dib17 : in std_logic;
- dib16 : in std_logic;
- dib15 : in std_logic;
- dib14 : in std_logic;
- dib13 : in std_logic;
- dib12 : in std_logic;
- dib11 : in std_logic;
- dib10 : in std_logic;
- dib9 : in std_logic;
- dib8 : in std_logic;
- dib7 : in std_logic;
- dib6 : in std_logic;
- dib5 : in std_logic;
- dib4 : in std_logic;
- dib3 : in std_logic;
- dib2 : in std_logic;
- dib1 : in std_logic;
- dib0 : in std_logic;
- adb13 : in std_logic;
- adb12 : in std_logic;
- adb11 : in std_logic;
- adb10 : in std_logic;
- adb9 : in std_logic;
- adb8 : in std_logic;
- adb7 : in std_logic;
- adb6 : in std_logic;
- adb5 : in std_logic;
- adb4 : in std_logic;
- adb3 : in std_logic;
- adb2 : in std_logic;
- adb1 : in std_logic;
- adb0 : in std_logic;
- ceb : in std_logic;
- oceb : in std_logic;
- clkb : in std_logic;
- web : in std_logic;
- csb2 : in std_logic;
- csb1 : in std_logic;
- csb0 : in std_logic;
- rstb : in std_logic;
- doa17 : out std_logic;
- doa16 : out std_logic;
- doa15 : out std_logic;
- doa14 : out std_logic;
- doa13 : out std_logic;
- doa12 : out std_logic;
- doa11 : out std_logic;
- doa10 : out std_logic;
- doa9 : out std_logic;
- doa8 : out std_logic;
- doa7 : out std_logic;
- doa6 : out std_logic;
- doa5 : out std_logic;
- doa4 : out std_logic;
- doa3 : out std_logic;
- doa2 : out std_logic;
- doa1 : out std_logic;
- doa0 : out std_logic;
- dob17 : out std_logic;
- dob16 : out std_logic;
- dob15 : out std_logic;
- dob14 : out std_logic;
- dob13 : out std_logic;
- dob12 : out std_logic;
- dob11 : out std_logic;
- dob10 : out std_logic;
- dob9 : out std_logic;
- dob8 : out std_logic;
- dob7 : out std_logic;
- dob6 : out std_logic;
- dob5 : out std_logic;
- dob4 : out std_logic;
- dob3 : out std_logic;
- dob2 : out std_logic;
- dob1 : out std_logic;
- dob0 : out std_logic );
-end component;
-
-component pdpw16kd is
+ DATA_WIDTH_A : integer := 18;
+ DATA_WIDTH_B : integer := 18;
+ REGMODE_A : string := "NOREG";
+ REGMODE_B : string := "NOREG";
+ RESETMODE : string := "SYNC";
+ ASYNC_RESET_RELEASE : string := "SYNC";
+ WRITEMODE_A : string := "NORMAL";
+ WRITEMODE_B : string := "NORMAL";
+ CSDECODE_A : string := "0b000";
+ CSDECODE_B : string := "0b000";
+ GSR : string := "ENABLED";
+ INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INIT_DATA : string := "STATIC" );
+ port (
+ DIA17 : in std_logic;
+ DIA16 : in std_logic;
+ DIA15 : in std_logic;
+ DIA14 : in std_logic;
+ DIA13 : in std_logic;
+ DIA12 : in std_logic;
+ DIA11 : in std_logic;
+ DIA10 : in std_logic;
+ DIA9 : in std_logic;
+ DIA8 : in std_logic;
+ DIA7 : in std_logic;
+ DIA6 : in std_logic;
+ DIA5 : in std_logic;
+ DIA4 : in std_logic;
+ DIA3 : in std_logic;
+ DIA2 : in std_logic;
+ DIA1 : in std_logic;
+ DIA0 : in std_logic;
+ ADA13 : in std_logic;
+ ADA12 : in std_logic;
+ ADA11 : in std_logic;
+ ADA10 : in std_logic;
+ ADA9 : in std_logic;
+ ADA8 : in std_logic;
+ ADA7 : in std_logic;
+ ADA6 : in std_logic;
+ ADA5 : in std_logic;
+ ADA4 : in std_logic;
+ ADA3 : in std_logic;
+ ADA2 : in std_logic;
+ ADA1 : in std_logic;
+ ADA0 : in std_logic;
+ CEA : in std_logic;
+ OCEA : in std_logic;
+ CLKA : in std_logic;
+ WEA : in std_logic;
+ CSA2 : in std_logic;
+ CSA1 : in std_logic;
+ CSA0 : in std_logic;
+ RSTA : in std_logic;
+ DIB17 : in std_logic;
+ DIB16 : in std_logic;
+ DIB15 : in std_logic;
+ DIB14 : in std_logic;
+ DIB13 : in std_logic;
+ DIB12 : in std_logic;
+ DIB11 : in std_logic;
+ DIB10 : in std_logic;
+ DIB9 : in std_logic;
+ DIB8 : in std_logic;
+ DIB7 : in std_logic;
+ DIB6 : in std_logic;
+ DIB5 : in std_logic;
+ DIB4 : in std_logic;
+ DIB3 : in std_logic;
+ DIB2 : in std_logic;
+ DIB1 : in std_logic;
+ DIB0 : in std_logic;
+ ADB13 : in std_logic;
+ ADB12 : in std_logic;
+ ADB11 : in std_logic;
+ ADB10 : in std_logic;
+ ADB9 : in std_logic;
+ ADB8 : in std_logic;
+ ADB7 : in std_logic;
+ ADB6 : in std_logic;
+ ADB5 : in std_logic;
+ ADB4 : in std_logic;
+ ADB3 : in std_logic;
+ ADB2 : in std_logic;
+ ADB1 : in std_logic;
+ ADB0 : in std_logic;
+ CEB : in std_logic;
+ OCEB : in std_logic;
+ CLKB : in std_logic;
+ WEB : in std_logic;
+ CSB2 : in std_logic;
+ CSB1 : in std_logic;
+ CSB0 : in std_logic;
+ RSTB : in std_logic;
+ DOA17 : out std_logic;
+ DOA16 : out std_logic;
+ DOA15 : out std_logic;
+ DOA14 : out std_logic;
+ DOA13 : out std_logic;
+ DOA12 : out std_logic;
+ DOA11 : out std_logic;
+ DOA10 : out std_logic;
+ DOA9 : out std_logic;
+ DOA8 : out std_logic;
+ DOA7 : out std_logic;
+ DOA6 : out std_logic;
+ DOA5 : out std_logic;
+ DOA4 : out std_logic;
+ DOA3 : out std_logic;
+ DOA2 : out std_logic;
+ DOA1 : out std_logic;
+ DOA0 : out std_logic;
+ DOB17 : out std_logic;
+ DOB16 : out std_logic;
+ DOB15 : out std_logic;
+ DOB14 : out std_logic;
+ DOB13 : out std_logic;
+ DOB12 : out std_logic;
+ DOB11 : out std_logic;
+ DOB10 : out std_logic;
+ DOB9 : out std_logic;
+ DOB8 : out std_logic;
+ DOB7 : out std_logic;
+ DOB6 : out std_logic;
+ DOB5 : out std_logic;
+ DOB4 : out std_logic;
+ DOB3 : out std_logic;
+ DOB2 : out std_logic;
+ DOB1 : out std_logic;
+ DOB0 : out std_logic );
+end component;
+
+component PDPW16KD is
generic (
- data_width_w : integer := 36;
- data_width_r : integer := 36;
- gsr : string := "ENABLED";
- regmode : string := "NOREG";
- resetmode : string := "SYNC";
- async_reset_release : string := "SYNC";
- csdecode_w : string := "0b000";
- csdecode_r : string := "0b000";
- initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_2f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- initval_3f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- init_data : string := "STATIC" );
- port (
- di35 : in std_logic;
- di34 : in std_logic;
- di33 : in std_logic;
- di32 : in std_logic;
- di31 : in std_logic;
- di30 : in std_logic;
- di29 : in std_logic;
- di28 : in std_logic;
- di27 : in std_logic;
- di26 : in std_logic;
- di25 : in std_logic;
- di24 : in std_logic;
- di23 : in std_logic;
- di22 : in std_logic;
- di21 : in std_logic;
- di20 : in std_logic;
- di19 : in std_logic;
- di18 : in std_logic;
- di17 : in std_logic;
- di16 : in std_logic;
- di15 : in std_logic;
- di14 : in std_logic;
- di13 : in std_logic;
- di12 : in std_logic;
- di11 : in std_logic;
- di10 : in std_logic;
- di9 : in std_logic;
- di8 : in std_logic;
- di7 : in std_logic;
- di6 : in std_logic;
- di5 : in std_logic;
- di4 : in std_logic;
- di3 : in std_logic;
- di2 : in std_logic;
- di1 : in std_logic;
- di0 : in std_logic;
- adw8 : in std_logic;
- adw7 : in std_logic;
- adw6 : in std_logic;
- adw5 : in std_logic;
- adw4 : in std_logic;
- adw3 : in std_logic;
- adw2 : in std_logic;
- adw1 : in std_logic;
- adw0 : in std_logic;
- be3 : in std_logic;
- be2 : in std_logic;
- be1 : in std_logic;
- be0 : in std_logic;
- cew : in std_logic;
- clkw : in std_logic;
- csw2 : in std_logic;
- csw1 : in std_logic;
- csw0 : in std_logic;
- adr13 : in std_logic;
- adr12 : in std_logic;
- adr11 : in std_logic;
- adr10 : in std_logic;
- adr9 : in std_logic;
- adr8 : in std_logic;
- adr7 : in std_logic;
- adr6 : in std_logic;
- adr5 : in std_logic;
- adr4 : in std_logic;
- adr3 : in std_logic;
- adr2 : in std_logic;
- adr1 : in std_logic;
- adr0 : in std_logic;
- cer : in std_logic;
- ocer : in std_logic;
- clkr : in std_logic;
- csr2 : in std_logic;
- csr1 : in std_logic;
- csr0 : in std_logic;
- rst : in std_logic;
- do35 : out std_logic;
- do34 : out std_logic;
- do33 : out std_logic;
- do32 : out std_logic;
- do31 : out std_logic;
- do30 : out std_logic;
- do29 : out std_logic;
- do28 : out std_logic;
- do27 : out std_logic;
- do26 : out std_logic;
- do25 : out std_logic;
- do24 : out std_logic;
- do23 : out std_logic;
- do22 : out std_logic;
- do21 : out std_logic;
- do20 : out std_logic;
- do19 : out std_logic;
- do18 : out std_logic;
- do17 : out std_logic;
- do16 : out std_logic;
- do15 : out std_logic;
- do14 : out std_logic;
- do13 : out std_logic;
- do12 : out std_logic;
- do11 : out std_logic;
- do10 : out std_logic;
- do9 : out std_logic;
- do8 : out std_logic;
- do7 : out std_logic;
- do6 : out std_logic;
- do5 : out std_logic;
- do4 : out std_logic;
- do3 : out std_logic;
- do2 : out std_logic;
- do1 : out std_logic;
- do0 : out std_logic );
-end component;
-
-component dpr16x4c is
+ DATA_WIDTH_W : integer := 36;
+ DATA_WIDTH_R : integer := 36;
+ GSR : string := "ENABLED";
+ REGMODE : string := "NOREG";
+ RESETMODE : string := "SYNC";
+ ASYNC_RESET_RELEASE : string := "SYNC";
+ CSDECODE_W : string := "0b000";
+ CSDECODE_R : string := "0b000";
+ INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ INIT_DATA : string := "STATIC" );
+ port (
+ DI35 : in std_logic;
+ DI34 : in std_logic;
+ DI33 : in std_logic;
+ DI32 : in std_logic;
+ DI31 : in std_logic;
+ DI30 : in std_logic;
+ DI29 : in std_logic;
+ DI28 : in std_logic;
+ DI27 : in std_logic;
+ DI26 : in std_logic;
+ DI25 : in std_logic;
+ DI24 : in std_logic;
+ DI23 : in std_logic;
+ DI22 : in std_logic;
+ DI21 : in std_logic;
+ DI20 : in std_logic;
+ DI19 : in std_logic;
+ DI18 : in std_logic;
+ DI17 : in std_logic;
+ DI16 : in std_logic;
+ DI15 : in std_logic;
+ DI14 : in std_logic;
+ DI13 : in std_logic;
+ DI12 : in std_logic;
+ DI11 : in std_logic;
+ DI10 : in std_logic;
+ DI9 : in std_logic;
+ DI8 : in std_logic;
+ DI7 : in std_logic;
+ DI6 : in std_logic;
+ DI5 : in std_logic;
+ DI4 : in std_logic;
+ DI3 : in std_logic;
+ DI2 : in std_logic;
+ DI1 : in std_logic;
+ DI0 : in std_logic;
+ ADW8 : in std_logic;
+ ADW7 : in std_logic;
+ ADW6 : in std_logic;
+ ADW5 : in std_logic;
+ ADW4 : in std_logic;
+ ADW3 : in std_logic;
+ ADW2 : in std_logic;
+ ADW1 : in std_logic;
+ ADW0 : in std_logic;
+ BE3 : in std_logic;
+ BE2 : in std_logic;
+ BE1 : in std_logic;
+ BE0 : in std_logic;
+ CEW : in std_logic;
+ CLKW : in std_logic;
+ CSW2 : in std_logic;
+ CSW1 : in std_logic;
+ CSW0 : in std_logic;
+ ADR13 : in std_logic;
+ ADR12 : in std_logic;
+ ADR11 : in std_logic;
+ ADR10 : in std_logic;
+ ADR9 : in std_logic;
+ ADR8 : in std_logic;
+ ADR7 : in std_logic;
+ ADR6 : in std_logic;
+ ADR5 : in std_logic;
+ ADR4 : in std_logic;
+ ADR3 : in std_logic;
+ ADR2 : in std_logic;
+ ADR1 : in std_logic;
+ ADR0 : in std_logic;
+ CER : in std_logic;
+ OCER : in std_logic;
+ CLKR : in std_logic;
+ CSR2 : in std_logic;
+ CSR1 : in std_logic;
+ CSR0 : in std_logic;
+ RST : in std_logic;
+ DO35 : out std_logic;
+ DO34 : out std_logic;
+ DO33 : out std_logic;
+ DO32 : out std_logic;
+ DO31 : out std_logic;
+ DO30 : out std_logic;
+ DO29 : out std_logic;
+ DO28 : out std_logic;
+ DO27 : out std_logic;
+ DO26 : out std_logic;
+ DO25 : out std_logic;
+ DO24 : out std_logic;
+ DO23 : out std_logic;
+ DO22 : out std_logic;
+ DO21 : out std_logic;
+ DO20 : out std_logic;
+ DO19 : out std_logic;
+ DO18 : out std_logic;
+ DO17 : out std_logic;
+ DO16 : out std_logic;
+ DO15 : out std_logic;
+ DO14 : out std_logic;
+ DO13 : out std_logic;
+ DO12 : out std_logic;
+ DO11 : out std_logic;
+ DO10 : out std_logic;
+ DO9 : out std_logic;
+ DO8 : out std_logic;
+ DO7 : out std_logic;
+ DO6 : out std_logic;
+ DO5 : out std_logic;
+ DO4 : out std_logic;
+ DO3 : out std_logic;
+ DO2 : out std_logic;
+ DO1 : out std_logic;
+ DO0 : out std_logic );
+end component;
+
+component DPR16X4C is
generic (
- initval : string := "0x0000000000000000" );
- port (
- di3 : in std_logic;
- di2 : in std_logic;
- di1 : in std_logic;
- di0 : in std_logic;
- wad3 : in std_logic;
- wad2 : in std_logic;
- wad1 : in std_logic;
- wad0 : in std_logic;
- wck : in std_logic;
- wre : in std_logic;
- rad3 : in std_logic;
- rad2 : in std_logic;
- rad1 : in std_logic;
- rad0 : in std_logic;
- do3 : out std_logic;
- do2 : out std_logic;
- do1 : out std_logic;
- do0 : out std_logic );
-end component;
-
-component spr16x4c is
+ INITVAL : string := "0x0000000000000000" );
+ port (
+ DI3 : in std_logic;
+ DI2 : in std_logic;
+ DI1 : in std_logic;
+ DI0 : in std_logic;
+ WAD3 : in std_logic;
+ WAD2 : in std_logic;
+ WAD1 : in std_logic;
+ WAD0 : in std_logic;
+ WCK : in std_logic;
+ WRE : in std_logic;
+ RAD3 : in std_logic;
+ RAD2 : in std_logic;
+ RAD1 : in std_logic;
+ RAD0 : in std_logic;
+ DO3 : out std_logic;
+ DO2 : out std_logic;
+ DO1 : out std_logic;
+ DO0 : out std_logic );
+end component;
+
+component SPR16X4C is
generic (
- initval : string := "0x0000000000000000" );
- port (
- di3 : in std_logic;
- di2 : in std_logic;
- di1 : in std_logic;
- di0 : in std_logic;
- ad3 : in std_logic;
- ad2 : in std_logic;
- ad1 : in std_logic;
- ad0 : in std_logic;
- ck : in std_logic;
- wre : in std_logic;
- do3 : out std_logic;
- do2 : out std_logic;
- do1 : out std_logic;
- do0 : out std_logic );
-end component;
-
-component dtr is
+ INITVAL : string := "0x0000000000000000" );
+ port (
+ DI3 : in std_logic;
+ DI2 : in std_logic;
+ DI1 : in std_logic;
+ DI0 : in std_logic;
+ AD3 : in std_logic;
+ AD2 : in std_logic;
+ AD1 : in std_logic;
+ AD0 : in std_logic;
+ CK : in std_logic;
+ WRE : in std_logic;
+ DO3 : out std_logic;
+ DO2 : out std_logic;
+ DO1 : out std_logic;
+ DO0 : out std_logic );
+end component;
+
+component DTR is
generic (
- dtr_temp : integer := 25 );
+ DTR_TEMP : integer := 25 );
port (
- startpulse : in std_logic;
- dtrout7 : out std_logic;
- dtrout6 : out std_logic;
- dtrout5 : out std_logic;
- dtrout4 : out std_logic;
- dtrout3 : out std_logic;
- dtrout2 : out std_logic;
- dtrout1 : out std_logic;
- dtrout0 : out std_logic );
+ STARTPULSE : in std_logic;
+ DTROUT7 : out std_logic;
+ DTROUT6 : out std_logic;
+ DTROUT5 : out std_logic;
+ DTROUT4 : out std_logic;
+ DTROUT3 : out std_logic;
+ DTROUT2 : out std_logic;
+ DTROUT1 : out std_logic;
+ DTROUT0 : out std_logic );
end component;
-component clkdivf is
+component CLKDIVF is
generic (
- gsr : string := "DISABLED";
- div : string := "2.0" );
+ GSR : string := "DISABLED";
+ DIV : string := "2.0" );
port (
- clki : in std_logic;
- rst : in std_logic;
- alignwd : in std_logic;
- cdivx : out std_logic );
+ CLKI : in std_logic;
+ RST : in std_logic;
+ ALIGNWD : in std_logic;
+ CDIVX : out std_logic );
end component;
-component pcsclkdiv is
+component PCSCLKDIV is
generic (
- gsr : string := "DISABLED" );
+ GSR : string := "DISABLED" );
port (
- clki : in std_logic;
- rst : in std_logic;
- sel2 : in std_logic;
- sel1 : in std_logic;
- sel0 : in std_logic;
- cdiv1 : out std_logic;
- cdivx : out std_logic );
+ CLKI : in std_logic;
+ RST : in std_logic;
+ SEL2 : in std_logic;
+ SEL1 : in std_logic;
+ SEL0 : in std_logic;
+ CDIV1 : out std_logic;
+ CDIVX : out std_logic );
end component;
-component dcsc is
+component DCSC is
generic (
- dcsmode : string := "POS" );
+ DCSMODE : string := "POS" );
port (
- clk1 : in std_logic;
- clk0 : in std_logic;
- sel1 : in std_logic;
- sel0 : in std_logic;
- modesel : in std_logic;
- dcsout : out std_logic );
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ SEL1 : in std_logic;
+ SEL0 : in std_logic;
+ MODESEL : in std_logic;
+ DCSOUT : out std_logic );
end component;
-component eclksyncb is
+component ECLKSYNCB is
port (
- eclki : in std_logic;
- stop : in std_logic;
- eclko : out std_logic );
+ ECLKI : in std_logic;
+ STOP : in std_logic;
+ ECLKO : out std_logic );
end component;
-component eclkbridgecs is
+component ECLKBRIDGECS is
port (
- clk0 : in std_logic;
- clk1 : in std_logic;
- sel : in std_logic;
- ecsout : out std_logic );
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ SEL : in std_logic;
+ ECSOUT : out std_logic );
end component;
-component dcca is
+component DCCA is
port (
- clki : in std_logic;
- ce : in std_logic;
- clko : out std_logic );
+ CLKI : in std_logic;
+ CE : in std_logic;
+ CLKO : out std_logic );
end component;
-component oscg is
+component OSCG is
generic (
- div : integer := 128 );
+ DIV : integer := 128 );
port (
- osc : out std_logic );
+ OSC : out std_logic );
end component;
component EHXPLLL is
@@ -3796,1172 +3796,1172 @@ component EHXPLLL is
CLKINTFB : out std_logic );
end component;
-component pllrefcs is
+component PLLREFCS is
port (
- clk0 : in std_logic;
- clk1 : in std_logic;
- sel : in std_logic;
- pllcsout : out std_logic );
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ SEL : in std_logic;
+ PLLCSOUT : out std_logic );
end component;
-component bcinrd is
+component BCINRD is
generic (
- bankid : integer := 2 );
+ BANKID : integer := 2 );
port (
- inrdeni : in std_logic );
+ INRDENI : in std_logic );
end component;
-component bclvdsob is
+component BCLVDSOB is
generic (
- bankid : integer := 2 );
+ BANKID : integer := 2 );
port (
- lvdseni : in std_logic );
+ LVDSENI : in std_logic );
end component;
-component inrdb is
+component INRDB is
port (
- d : in std_logic;
- e : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ E : in std_logic;
+ Q : out std_logic );
end component;
-component lvdsob is
+component LVDSOB is
port (
- d : in std_logic;
- e : in std_logic;
- q : out std_logic );
+ D : in std_logic;
+ E : in std_logic;
+ Q : out std_logic );
end component;
-component start is
+component START is
port (
- startclk : in std_logic );
+ STARTCLK : in std_logic );
end component;
-component usrmclk is
+component USRMCLK is
port (
- usrmclki : in std_logic;
- usrmclkts : in std_logic );
+ USRMCLKI : in std_logic;
+ USRMCLKTS : in std_logic );
end component;
-component delayf is
+component DELAYF is
generic (
- del_mode : string := "USER_DEFINED";
- del_value : integer := 0 );
+ DEL_MODE : string := "USER_DEFINED";
+ DEL_VALUE : integer := 0 );
port (
- a : in std_logic;
- loadn : in std_logic;
- move : in std_logic;
- direction : in std_logic;
- z : out std_logic;
- cflag : out std_logic );
+ A : in std_logic;
+ LOADN : in std_logic;
+ MOVE : in std_logic;
+ DIRECTION : in std_logic;
+ Z : out std_logic;
+ CFLAG : out std_logic );
end component;
-component delayg is
+component DELAYG is
generic (
- del_mode : string := "USER_DEFINED";
- del_value : integer := 0 );
+ DEL_MODE : string := "USER_DEFINED";
+ DEL_VALUE : integer := 0 );
port (
- a : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ Z : out std_logic );
end component;
-component dqsbufm is
+component DQSBUFM is
generic (
- dqs_li_del_val : integer := 4;
- dqs_li_del_adj : string := "FACTORYONLY";
- dqs_lo_del_val : integer := 0;
- dqs_lo_del_adj : string := "FACTORYONLY";
- gsr : string := "ENABLED" );
- port (
- dqsi : in std_logic;
- read1 : in std_logic;
- read0 : in std_logic;
- readclksel2 : in std_logic;
- readclksel1 : in std_logic;
- readclksel0 : in std_logic;
- ddrdel : in std_logic;
- eclk : in std_logic;
- sclk : in std_logic;
- rst : in std_logic;
- dyndelay7 : in std_logic;
- dyndelay6 : in std_logic;
- dyndelay5 : in std_logic;
- dyndelay4 : in std_logic;
- dyndelay3 : in std_logic;
- dyndelay2 : in std_logic;
- dyndelay1 : in std_logic;
- dyndelay0 : in std_logic;
- pause : in std_logic;
- rdloadn : in std_logic;
- rdmove : in std_logic;
- rddirection : in std_logic;
- wrloadn : in std_logic;
- wrmove : in std_logic;
- wrdirection : in std_logic;
- dqsr90 : out std_logic;
- dqsw : out std_logic;
- dqsw270 : out std_logic;
- rdpntr2 : out std_logic;
- rdpntr1 : out std_logic;
- rdpntr0 : out std_logic;
- wrpntr2 : out std_logic;
- wrpntr1 : out std_logic;
- wrpntr0 : out std_logic;
- datavalid : out std_logic;
- burstdet : out std_logic;
- rdcflag : out std_logic;
- wrcflag : out std_logic );
-end component;
-
-component ddrdlla is
+ DQS_LI_DEL_VAL : integer := 4;
+ DQS_LI_DEL_ADJ : string := "FACTORYONLY";
+ DQS_LO_DEL_VAL : integer := 0;
+ DQS_LO_DEL_ADJ : string := "FACTORYONLY";
+ GSR : string := "ENABLED" );
+ port (
+ DQSI : in std_logic;
+ READ1 : in std_logic;
+ READ0 : in std_logic;
+ READCLKSEL2 : in std_logic;
+ READCLKSEL1 : in std_logic;
+ READCLKSEL0 : in std_logic;
+ DDRDEL : in std_logic;
+ ECLK : in std_logic;
+ SCLK : in std_logic;
+ RST : in std_logic;
+ DYNDELAY7 : in std_logic;
+ DYNDELAY6 : in std_logic;
+ DYNDELAY5 : in std_logic;
+ DYNDELAY4 : in std_logic;
+ DYNDELAY3 : in std_logic;
+ DYNDELAY2 : in std_logic;
+ DYNDELAY1 : in std_logic;
+ DYNDELAY0 : in std_logic;
+ PAUSE : in std_logic;
+ RDLOADN : in std_logic;
+ RDMOVE : in std_logic;
+ RDDIRECTION : in std_logic;
+ WRLOADN : in std_logic;
+ WRMOVE : in std_logic;
+ WRDIRECTION : in std_logic;
+ DQSR90 : out std_logic;
+ DQSW : out std_logic;
+ DQSW270 : out std_logic;
+ RDPNTR2 : out std_logic;
+ RDPNTR1 : out std_logic;
+ RDPNTR0 : out std_logic;
+ WRPNTR2 : out std_logic;
+ WRPNTR1 : out std_logic;
+ WRPNTR0 : out std_logic;
+ DATAVALID : out std_logic;
+ BURSTDET : out std_logic;
+ RDCFLAG : out std_logic;
+ WRCFLAG : out std_logic );
+end component;
+
+component DDRDLLA is
generic (
- force_max_delay : string := "NO";
- lock_cyc : integer := 200;
- gsr : string := "ENABLED" );
- port (
- clk : in std_logic;
- rst : in std_logic;
- uddcntln : in std_logic;
- freeze : in std_logic;
- ddrdel : out std_logic;
- lock : out std_logic;
- dcntl7 : out std_logic;
- dcntl6 : out std_logic;
- dcntl5 : out std_logic;
- dcntl4 : out std_logic;
- dcntl3 : out std_logic;
- dcntl2 : out std_logic;
- dcntl1 : out std_logic;
- dcntl0 : out std_logic );
-end component;
-
-component dlldeld is
- port (
- a : in std_logic;
- ddrdel : in std_logic;
- loadn : in std_logic;
- move : in std_logic;
- direction : in std_logic;
- z : out std_logic;
- cflag : out std_logic );
-end component;
-
-component iddrx1f is
+ FORCE_MAX_DELAY : string := "NO";
+ LOCK_CYC : integer := 200;
+ GSR : string := "ENABLED" );
+ port (
+ CLK : in std_logic;
+ RST : in std_logic;
+ UDDCNTLN : in std_logic;
+ FREEZE : in std_logic;
+ DDRDEL : out std_logic;
+ LOCK : out std_logic;
+ DCNTL7 : out std_logic;
+ DCNTL6 : out std_logic;
+ DCNTL5 : out std_logic;
+ DCNTL4 : out std_logic;
+ DCNTL3 : out std_logic;
+ DCNTL2 : out std_logic;
+ DCNTL1 : out std_logic;
+ DCNTL0 : out std_logic );
+end component;
+
+component DLLDELD is
+ port (
+ A : in std_logic;
+ DDRDEL : in std_logic;
+ LOADN : in std_logic;
+ MOVE : in std_logic;
+ DIRECTION : in std_logic;
+ Z : out std_logic;
+ CFLAG : out std_logic );
+end component;
+
+component IDDRX1F is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sclk : in std_logic;
- rst : in std_logic;
- q0 : out std_logic;
- q1 : out std_logic );
+ D : in std_logic;
+ SCLK : in std_logic;
+ RST : in std_logic;
+ Q0 : out std_logic;
+ Q1 : out std_logic );
end component;
-component iddrx2f is
+component IDDRX2F is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- alignwd : in std_logic;
- q3 : out std_logic;
- q2 : out std_logic;
- q1 : out std_logic;
- q0 : out std_logic );
+ D : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ ALIGNWD : in std_logic;
+ Q3 : out std_logic;
+ Q2 : out std_logic;
+ Q1 : out std_logic;
+ Q0 : out std_logic );
end component;
-component iddr71b is
+component IDDR71B is
generic (
- gsr : string := "ENABLED" );
- port (
- d : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- alignwd : in std_logic;
- q6 : out std_logic;
- q5 : out std_logic;
- q4 : out std_logic;
- q3 : out std_logic;
- q2 : out std_logic;
- q1 : out std_logic;
- q0 : out std_logic );
-end component;
-
-component oddrx1f is
+ GSR : string := "ENABLED" );
+ port (
+ D : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ ALIGNWD : in std_logic;
+ Q6 : out std_logic;
+ Q5 : out std_logic;
+ Q4 : out std_logic;
+ Q3 : out std_logic;
+ Q2 : out std_logic;
+ Q1 : out std_logic;
+ Q0 : out std_logic );
+end component;
+
+component ODDRX1F is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- sclk : in std_logic;
- rst : in std_logic;
- d0 : in std_logic;
- d1 : in std_logic;
- q : out std_logic );
+ SCLK : in std_logic;
+ RST : in std_logic;
+ D0 : in std_logic;
+ D1 : in std_logic;
+ Q : out std_logic );
end component;
-component oddrx2f is
+component ODDRX2F is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- d3 : in std_logic;
- d2 : in std_logic;
- d1 : in std_logic;
- d0 : in std_logic;
- q : out std_logic );
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ D3 : in std_logic;
+ D2 : in std_logic;
+ D1 : in std_logic;
+ D0 : in std_logic;
+ Q : out std_logic );
end component;
-component oddr71b is
+component ODDR71B is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- d6 : in std_logic;
- d5 : in std_logic;
- d4 : in std_logic;
- d3 : in std_logic;
- d2 : in std_logic;
- d1 : in std_logic;
- d0 : in std_logic;
- q : out std_logic );
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ D6 : in std_logic;
+ D5 : in std_logic;
+ D4 : in std_logic;
+ D3 : in std_logic;
+ D2 : in std_logic;
+ D1 : in std_logic;
+ D0 : in std_logic;
+ Q : out std_logic );
end component;
-component imipi is
+component IMIPI is
port (
- a : in std_logic;
- an : in std_logic;
- hssel : in std_logic;
- ohsols1 : out std_logic;
- ols0 : out std_logic );
+ A : in std_logic;
+ AN : in std_logic;
+ HSSEL : in std_logic;
+ OHSOLS1 : out std_logic;
+ OLS0 : out std_logic );
end component;
-component iddrx2dqa is
+component IDDRX2DQA is
generic (
- gsr : string := "ENABLED" );
- port (
- sclk : in std_logic;
- eclk : in std_logic;
- dqsr90 : in std_logic;
- d : in std_logic;
- rst : in std_logic;
- rdpntr2 : in std_logic;
- rdpntr1 : in std_logic;
- rdpntr0 : in std_logic;
- wrpntr2 : in std_logic;
- wrpntr1 : in std_logic;
- wrpntr0 : in std_logic;
- q3 : out std_logic;
- q2 : out std_logic;
- q1 : out std_logic;
- q0 : out std_logic;
- qwl : out std_logic );
-end component;
-
-component oddrx2dqa is
- generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d3 : in std_logic;
- d2 : in std_logic;
- d1 : in std_logic;
- d0 : in std_logic;
- dqsw270 : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- q : out std_logic );
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ DQSR90 : in std_logic;
+ D : in std_logic;
+ RST : in std_logic;
+ RDPNTR2 : in std_logic;
+ RDPNTR1 : in std_logic;
+ RDPNTR0 : in std_logic;
+ WRPNTR2 : in std_logic;
+ WRPNTR1 : in std_logic;
+ WRPNTR0 : in std_logic;
+ Q3 : out std_logic;
+ Q2 : out std_logic;
+ Q1 : out std_logic;
+ Q0 : out std_logic;
+ QWL : out std_logic );
+end component;
+
+component ODDRX2DQA is
+ generic (
+ GSR : string := "ENABLED" );
+ port (
+ D3 : in std_logic;
+ D2 : in std_logic;
+ D1 : in std_logic;
+ D0 : in std_logic;
+ DQSW270 : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ Q : out std_logic );
end component;
-component oddrx2dqsb is
+component ODDRX2DQSB is
generic (
- gsr : string := "ENABLED" );
- port (
- d3 : in std_logic;
- d2 : in std_logic;
- d1 : in std_logic;
- d0 : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- dqsw : in std_logic;
- rst : in std_logic;
- q : out std_logic );
+ GSR : string := "ENABLED" );
+ port (
+ D3 : in std_logic;
+ D2 : in std_logic;
+ D1 : in std_logic;
+ D0 : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ DQSW : in std_logic;
+ RST : in std_logic;
+ Q : out std_logic );
end component;
-component tshx2dqa is
+component TSHX2DQA is
generic (
- gsr : string := "ENABLED";
- regset : string := "SET" );
+ GSR : string := "ENABLED";
+ REGSET : string := "SET" );
port (
- t1 : in std_logic;
- t0 : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- dqsw270 : in std_logic;
- rst : in std_logic;
- q : out std_logic );
+ T1 : in std_logic;
+ T0 : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ DQSW270 : in std_logic;
+ RST : in std_logic;
+ Q : out std_logic );
end component;
-component tshx2dqsa is
+component TSHX2DQSA is
generic (
- gsr : string := "ENABLED";
- regset : string := "SET" );
+ GSR : string := "ENABLED";
+ REGSET : string := "SET" );
port (
- t1 : in std_logic;
- t0 : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- dqsw : in std_logic;
- rst : in std_logic;
- q : out std_logic );
+ T1 : in std_logic;
+ T0 : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ DQSW : in std_logic;
+ RST : in std_logic;
+ Q : out std_logic );
end component;
-component oshx2a is
+component OSHX2A is
generic (
- gsr : string := "ENABLED" );
+ GSR : string := "ENABLED" );
port (
- d1 : in std_logic;
- d0 : in std_logic;
- sclk : in std_logic;
- eclk : in std_logic;
- rst : in std_logic;
- q : out std_logic );
+ D1 : in std_logic;
+ D0 : in std_logic;
+ SCLK : in std_logic;
+ ECLK : in std_logic;
+ RST : in std_logic;
+ Q : out std_logic );
end component;
-component jtagg is
+component JTAGG is
generic (
- er1 : string := "ENABLED";
- er2 : string := "ENABLED" );
- port (
- tck : in std_logic;
- tms : in std_logic;
- tdi : in std_logic;
- jtdo2 : in std_logic;
- jtdo1 : in std_logic;
- tdo : out std_logic;
- jtdi : out std_logic;
- jtck : out std_logic;
- jrti2 : out std_logic;
- jrti1 : out std_logic;
- jshift : out std_logic;
- jupdate : out std_logic;
- jrstn : out std_logic;
- jce2 : out std_logic;
- jce1 : out std_logic );
-end component;
-
-component sedga is
+ ER1 : string := "ENABLED";
+ ER2 : string := "ENABLED" );
+ port (
+ TCK : in std_logic;
+ TMS : in std_logic;
+ TDI : in std_logic;
+ JTDO2 : in std_logic;
+ JTDO1 : in std_logic;
+ TDO : out std_logic;
+ JTDI : out std_logic;
+ JTCK : out std_logic;
+ JRTI2 : out std_logic;
+ JRTI1 : out std_logic;
+ JSHIFT : out std_logic;
+ JUPDATE : out std_logic;
+ JRSTN : out std_logic;
+ JCE2 : out std_logic;
+ JCE1 : out std_logic );
+end component;
+
+component SEDGA is
generic (
- sed_clk_freq : string := "2.4";
- checkalways : string := "DISABLED";
- dev_density : string := "85KUM" );
+ SED_CLK_FREQ : string := "2.4";
+ CHECKALWAYS : string := "DISABLED";
+ DEV_DENSITY : string := "85KUM" );
port (
- sedenable : in std_logic;
- sedstart : in std_logic;
- sedfrcerr : in std_logic;
- sederr : out std_logic;
- seddone : out std_logic;
- sedinprog : out std_logic;
- sedclkout : out std_logic );
+ SEDENABLE : in std_logic;
+ SEDSTART : in std_logic;
+ SEDFRCERR : in std_logic;
+ SEDERR : out std_logic;
+ SEDDONE : out std_logic;
+ SEDINPROG : out std_logic;
+ SEDCLKOUT : out std_logic );
end component;
-component extrefb is
+component EXTREFB is
generic (
- refck_pwdnb : string := "DONTCARE";
- refck_rterm : string := "DONTCARE";
- refck_dcbias_en : string := "DONTCARE" );
+ REFCK_PWDNB : string := "DONTCARE";
+ REFCK_RTERM : string := "DONTCARE";
+ REFCK_DCBIAS_EN : string := "DONTCARE" );
port (
- refclkp : in std_logic;
- refclkn : in std_logic;
- refclko : out std_logic );
+ REFCLKP : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKO : out std_logic );
end component;
-component pur is
+component PUR is
generic (
- rst_pulse : integer := 1 );
+ RST_PULSE : integer := 1 );
port (
- pur : in std_logic );
+ PUR : in std_logic );
end component;
-component bufba is
+component BUFBA is
port (
- a : in std_logic;
- z : out std_logic );
+ A : in std_logic;
+ Z : out std_logic );
end component;
-component obzpd is
+component OBZPD is
port (
- i : in std_logic;
- t : in std_logic;
- o : out std_logic );
+ I : in std_logic;
+ T : in std_logic;
+ O : out std_logic );
end component;
-component slogicb is
+component SLOGICB is
generic (
- timingcheckson : boolean := true;
- xon : boolean := false;
- msgon : boolean := true;
- instancepath : string := "SLOGICB";
- gsr : string := "ENABLED";
- srmode : string := "LSR_OVER_CE";
- m1mux : string := "VLO";
- m0mux : string := "VLO";
- lsrmux : string := "VLO";
- cemux : string := "VLO";
- clkmux : string := "VLO";
- reg1_sd : string := "VLO";
- reg0_sd : string := "VLO";
- lut1_initval : bit_vector := "0000000000000000";
- lut0_initval : bit_vector := "0000000000000000";
- reg1_regset : string := "RESET";
- reg0_regset : string := "RESET";
- lsronmux : string := "LSRMUX";
- check_m1 : boolean := false;
- check_di1 : boolean := false;
- check_di0 : boolean := false;
- check_m0 : boolean := false;
- check_ce : boolean := false;
- check_lsr : boolean := false );
- port (
- m1 : in std_ulogic;
- fxa : in std_ulogic;
- fxb : in std_ulogic;
- a1 : in std_ulogic;
- b1 : in std_ulogic;
- c1 : in std_ulogic;
- d1 : in std_ulogic;
- di1 : in std_ulogic;
- di0 : in std_ulogic;
- a0 : in std_ulogic;
- b0 : in std_ulogic;
- c0 : in std_ulogic;
- d0 : in std_ulogic;
- m0 : in std_ulogic;
- ce : in std_ulogic;
- clk : in std_ulogic;
- lsr : in std_ulogic;
- ofx1 : out std_ulogic;
- f1 : out std_ulogic;
- q1 : out std_ulogic;
- ofx0 : out std_ulogic;
- f0 : out std_ulogic;
- q0 : out std_ulogic );
-end component;
-
-component sccu2c is
+ TIMINGCHECKSON : boolean := true;
+ XON : boolean := false;
+ MSGON : boolean := true;
+ INSTANCEPATH : string := "SLOGICB";
+ GSR : string := "ENABLED";
+ SRMODE : string := "LSR_OVER_CE";
+ M1MUX : string := "VLO";
+ M0MUX : string := "VLO";
+ LSRMUX : string := "VLO";
+ CEMUX : string := "VLO";
+ CLKMUX : string := "VLO";
+ REG1_SD : string := "VLO";
+ REG0_SD : string := "VLO";
+ LUT1_INITVAL : bit_vector := "0000000000000000";
+ LUT0_INITVAL : bit_vector := "0000000000000000";
+ REG1_REGSET : string := "RESET";
+ REG0_REGSET : string := "RESET";
+ LSRONMUX : string := "LSRMUX";
+ CHECK_M1 : boolean := false;
+ CHECK_DI1 : boolean := false;
+ CHECK_DI0 : boolean := false;
+ CHECK_M0 : boolean := false;
+ CHECK_CE : boolean := false;
+ CHECK_LSR : boolean := false );
+ port (
+ M1 : in std_ulogic;
+ FXA : in std_ulogic;
+ FXB : in std_ulogic;
+ A1 : in std_ulogic;
+ B1 : in std_ulogic;
+ C1 : in std_ulogic;
+ D1 : in std_ulogic;
+ DI1 : in std_ulogic;
+ DI0 : in std_ulogic;
+ A0 : in std_ulogic;
+ B0 : in std_ulogic;
+ C0 : in std_ulogic;
+ D0 : in std_ulogic;
+ M0 : in std_ulogic;
+ CE : in std_ulogic;
+ CLK : in std_ulogic;
+ LSR : in std_ulogic;
+ OFX1 : out std_ulogic;
+ F1 : out std_ulogic;
+ Q1 : out std_ulogic;
+ OFX0 : out std_ulogic;
+ F0 : out std_ulogic;
+ Q0 : out std_ulogic );
+end component;
+
+component SCCU2C is
generic (
- timingcheckson : boolean := true;
- xon : boolean := false;
- msgon : boolean := true;
- instancepath : string := "SCCU2C";
- gsr : string := "ENABLED";
- srmode : string := "LSR_OVER_CE";
- m1mux : string := "VLO";
- m0mux : string := "VLO";
- lsrmux : string := "VLO";
- cemux : string := "VLO";
- clkmux : string := "VLO";
- reg1_sd : string := "VLO";
- reg0_sd : string := "VLO";
- reg1_regset : string := "RESET";
- reg0_regset : string := "RESET";
- lsronmux : string := "LSRMUX";
- ccu2_inject1_0 : string := "YES";
- ccu2_inject1_1 : string := "YES";
- init0_initval : std_logic_vector := "0000000000000000";
- init1_initval : std_logic_vector := "0000000000000000";
- check_m1 : boolean := false;
- check_di1 : boolean := false;
- check_di0 : boolean := false;
- check_m0 : boolean := false;
- check_ce : boolean := false;
- check_lsr : boolean := false );
- port (
- m1 : in std_ulogic;
- a1 : in std_ulogic;
- b1 : in std_ulogic;
- c1 : in std_ulogic;
- d1 : in std_ulogic;
- di1 : in std_ulogic;
- di0 : in std_ulogic;
- a0 : in std_ulogic;
- b0 : in std_ulogic;
- c0 : in std_ulogic;
- d0 : in std_ulogic;
- fci : in std_ulogic;
- m0 : in std_ulogic;
- ce : in std_ulogic;
- clk : in std_ulogic;
- lsr : in std_ulogic;
- fco : out std_ulogic;
- f1 : out std_ulogic;
- q1 : out std_ulogic;
- f0 : out std_ulogic;
- q0 : out std_ulogic );
-end component;
-
-component sramwb is
+ TIMINGCHECKSON : boolean := true;
+ XON : boolean := false;
+ MSGON : boolean := true;
+ INSTANCEPATH : string := "SCCU2C";
+ GSR : string := "ENABLED";
+ SRMODE : string := "LSR_OVER_CE";
+ M1MUX : string := "VLO";
+ M0MUX : string := "VLO";
+ LSRMUX : string := "VLO";
+ CEMUX : string := "VLO";
+ CLKMUX : string := "VLO";
+ REG1_SD : string := "VLO";
+ REG0_SD : string := "VLO";
+ REG1_REGSET : string := "RESET";
+ REG0_REGSET : string := "RESET";
+ LSRONMUX : string := "LSRMUX";
+ CCU2_INJECT1_0 : string := "YES";
+ CCU2_INJECT1_1 : string := "YES";
+ INIT0_INITVAL : std_logic_vector := "0000000000000000";
+ INIT1_INITVAL : std_logic_vector := "0000000000000000";
+ CHECK_M1 : boolean := false;
+ CHECK_DI1 : boolean := false;
+ CHECK_DI0 : boolean := false;
+ CHECK_M0 : boolean := false;
+ CHECK_CE : boolean := false;
+ CHECK_LSR : boolean := false );
+ port (
+ M1 : in std_ulogic;
+ A1 : in std_ulogic;
+ B1 : in std_ulogic;
+ C1 : in std_ulogic;
+ D1 : in std_ulogic;
+ DI1 : in std_ulogic;
+ DI0 : in std_ulogic;
+ A0 : in std_ulogic;
+ B0 : in std_ulogic;
+ C0 : in std_ulogic;
+ D0 : in std_ulogic;
+ FCI : in std_ulogic;
+ M0 : in std_ulogic;
+ CE : in std_ulogic;
+ CLK : in std_ulogic;
+ LSR : in std_ulogic;
+ FCO : out std_ulogic;
+ F1 : out std_ulogic;
+ Q1 : out std_ulogic;
+ F0 : out std_ulogic;
+ Q0 : out std_ulogic );
+end component;
+
+component SRAMWB is
generic (
- timingcheckson : boolean := true;
- xon : boolean := false;
- msgon : boolean := true;
- instancepath : string := "SRAMWB";
- wd0mux : string := "VLO";
- wd1mux : string := "VLO";
- wd2mux : string := "VLO";
- wd3mux : string := "VLO";
- wad0mux : string := "VLO";
- wad1mux : string := "VLO";
- wad2mux : string := "VLO";
- wad3mux : string := "VLO" );
- port (
- a1 : in std_ulogic;
- b1 : in std_ulogic;
- c1 : in std_ulogic;
- d1 : in std_ulogic;
- a0 : in std_ulogic;
- b0 : in std_ulogic;
- c0 : in std_ulogic;
- d0 : in std_ulogic;
- wdo0 : out std_ulogic;
- wdo1 : out std_ulogic;
- wdo2 : out std_ulogic;
- wdo3 : out std_ulogic;
- wado0 : out std_ulogic;
- wado1 : out std_ulogic;
- wado2 : out std_ulogic;
- wado3 : out std_ulogic );
-end component;
-
-component sdprame is
+ TIMINGCHECKSON : boolean := true;
+ XON : boolean := false;
+ MSGON : boolean := true;
+ INSTANCEPATH : string := "SRAMWB";
+ WD0MUX : string := "VLO";
+ WD1MUX : string := "VLO";
+ WD2MUX : string := "VLO";
+ WD3MUX : string := "VLO";
+ WAD0MUX : string := "VLO";
+ WAD1MUX : string := "VLO";
+ WAD2MUX : string := "VLO";
+ WAD3MUX : string := "VLO" );
+ port (
+ A1 : in std_ulogic;
+ B1 : in std_ulogic;
+ C1 : in std_ulogic;
+ D1 : in std_ulogic;
+ A0 : in std_ulogic;
+ B0 : in std_ulogic;
+ C0 : in std_ulogic;
+ D0 : in std_ulogic;
+ WDO0 : out std_ulogic;
+ WDO1 : out std_ulogic;
+ WDO2 : out std_ulogic;
+ WDO3 : out std_ulogic;
+ WADO0 : out std_ulogic;
+ WADO1 : out std_ulogic;
+ WADO2 : out std_ulogic;
+ WADO3 : out std_ulogic );
+end component;
+
+component SDPRAME is
generic (
- timingcheckson : boolean := true;
- xon : boolean := false;
- msgon : boolean := true;
- instancepath : string := "SDPRAME";
- gsr : string := "ENABLED";
- srmode : string := "LSR_OVER_CE";
- m1mux : string := "VLO";
- m0mux : string := "VLO";
- lsrmux : string := "VLO";
- cemux : string := "VLO";
- clkmux : string := "VLO";
- wremux : string := "VLO";
- wckmux : string := "VLO";
- reg1_sd : string := "VLO";
- reg0_sd : string := "VLO";
- reg1_regset : string := "RESET";
- reg0_regset : string := "RESET";
- lsronmux : string := "LSRMUX";
- initval : string := "0x0000000000000000";
- dpram_rad0 : string := "SIG";
- dpram_rad1 : string := "SIG";
- dpram_rad2 : string := "SIG";
- dpram_rad3 : string := "SIG";
- check_wd1 : boolean := false;
- check_wd0 : boolean := false;
- check_wad0 : boolean := false;
- check_wad1 : boolean := false;
- check_wad2 : boolean := false;
- check_wad3 : boolean := false;
- check_wre : boolean := false;
- check_m0 : boolean := false;
- check_m1 : boolean := false;
- check_ce : boolean := false;
- check_lsr : boolean := false;
- check_di1 : boolean := false;
- check_di0 : boolean := false );
- port (
- m1 : in std_ulogic;
- rad0 : in std_ulogic;
- rad1 : in std_ulogic;
- rad2 : in std_ulogic;
- rad3 : in std_ulogic;
- wd1 : in std_ulogic;
- wd0 : in std_ulogic;
- wad0 : in std_ulogic;
- wad1 : in std_ulogic;
- wad2 : in std_ulogic;
- wad3 : in std_ulogic;
- wre : in std_ulogic;
- wck : in std_ulogic;
- m0 : in std_ulogic;
- ce : in std_ulogic;
- clk : in std_ulogic;
- lsr : in std_ulogic;
- di1 : in std_ulogic;
- di0 : in std_ulogic;
- f0 : out std_ulogic;
- q0 : out std_ulogic;
- f1 : out std_ulogic;
- q1 : out std_ulogic );
-end component;
-
-component dcua is
+ TIMINGCHECKSON : boolean := true;
+ XON : boolean := false;
+ MSGON : boolean := true;
+ INSTANCEPATH : string := "SDPRAME";
+ GSR : string := "ENABLED";
+ SRMODE : string := "LSR_OVER_CE";
+ M1MUX : string := "VLO";
+ M0MUX : string := "VLO";
+ LSRMUX : string := "VLO";
+ CEMUX : string := "VLO";
+ CLKMUX : string := "VLO";
+ WREMUX : string := "VLO";
+ WCKMUX : string := "VLO";
+ REG1_SD : string := "VLO";
+ REG0_SD : string := "VLO";
+ REG1_REGSET : string := "RESET";
+ REG0_REGSET : string := "RESET";
+ LSRONMUX : string := "LSRMUX";
+ INITVAL : string := "0x0000000000000000";
+ DPRAM_RAD0 : string := "SIG";
+ DPRAM_RAD1 : string := "SIG";
+ DPRAM_RAD2 : string := "SIG";
+ DPRAM_RAD3 : string := "SIG";
+ CHECK_WD1 : boolean := false;
+ CHECK_WD0 : boolean := false;
+ CHECK_WAD0 : boolean := false;
+ CHECK_WAD1 : boolean := false;
+ CHECK_WAD2 : boolean := false;
+ CHECK_WAD3 : boolean := false;
+ CHECK_WRE : boolean := false;
+ CHECK_M0 : boolean := false;
+ CHECK_M1 : boolean := false;
+ CHECK_CE : boolean := false;
+ CHECK_LSR : boolean := false;
+ CHECK_DI1 : boolean := false;
+ CHECK_DI0 : boolean := false );
+ port (
+ M1 : in std_ulogic;
+ RAD0 : in std_ulogic;
+ RAD1 : in std_ulogic;
+ RAD2 : in std_ulogic;
+ RAD3 : in std_ulogic;
+ WD1 : in std_ulogic;
+ WD0 : in std_ulogic;
+ WAD0 : in std_ulogic;
+ WAD1 : in std_ulogic;
+ WAD2 : in std_ulogic;
+ WAD3 : in std_ulogic;
+ WRE : in std_ulogic;
+ WCK : in std_ulogic;
+ M0 : in std_ulogic;
+ CE : in std_ulogic;
+ CLK : in std_ulogic;
+ LSR : in std_ulogic;
+ DI1 : in std_ulogic;
+ DI0 : in std_ulogic;
+ F0 : out std_ulogic;
+ Q0 : out std_ulogic;
+ F1 : out std_ulogic;
+ Q1 : out std_ulogic );
+end component;
+
+component DCUA is
generic (
- d_macropdb : string := "DONTCARE";
- d_ib_pwdnb : string := "DONTCARE";
- d_xge_mode : string := "DONTCARE";
- d_low_mark : string := "DONTCARE";
- d_high_mark : string := "DONTCARE";
- d_bus8bit_sel : string := "DONTCARE";
- d_cdr_lol_set : string := "DONTCARE";
- d_bitclk_local_en : string := "DONTCARE";
- d_bitclk_nd_en : string := "DONTCARE";
- d_bitclk_from_nd_en : string := "DONTCARE";
- d_sync_local_en : string := "DONTCARE";
- d_sync_nd_en : string := "DONTCARE";
- ch0_uc_mode : string := "DONTCARE";
- ch1_uc_mode : string := "DONTCARE";
- ch0_pcie_mode : string := "DONTCARE";
- ch1_pcie_mode : string := "DONTCARE";
- ch0_rio_mode : string := "DONTCARE";
- ch1_rio_mode : string := "DONTCARE";
- ch0_wa_mode : string := "DONTCARE";
- ch1_wa_mode : string := "DONTCARE";
- ch0_invert_rx : string := "DONTCARE";
- ch1_invert_rx : string := "DONTCARE";
- ch0_invert_tx : string := "DONTCARE";
- ch1_invert_tx : string := "DONTCARE";
- ch0_prbs_selection : string := "DONTCARE";
- ch1_prbs_selection : string := "DONTCARE";
- ch0_ge_an_enable : string := "DONTCARE";
- ch1_ge_an_enable : string := "DONTCARE";
- ch0_prbs_lock : string := "DONTCARE";
- ch1_prbs_lock : string := "DONTCARE";
- ch0_prbs_enable : string := "DONTCARE";
- ch1_prbs_enable : string := "DONTCARE";
- ch0_enable_cg_align : string := "DONTCARE";
- ch1_enable_cg_align : string := "DONTCARE";
- ch0_tx_gear_mode : string := "DONTCARE";
- ch1_tx_gear_mode : string := "DONTCARE";
- ch0_rx_gear_mode : string := "DONTCARE";
- ch1_rx_gear_mode : string := "DONTCARE";
- ch0_pcs_det_time_sel : string := "DONTCARE";
- ch1_pcs_det_time_sel : string := "DONTCARE";
- ch0_pcie_ei_en : string := "DONTCARE";
- ch1_pcie_ei_en : string := "DONTCARE";
- ch0_tx_gear_bypass : string := "DONTCARE";
- ch1_tx_gear_bypass : string := "DONTCARE";
- ch0_enc_bypass : string := "DONTCARE";
- ch1_enc_bypass : string := "DONTCARE";
- ch0_sb_bypass : string := "DONTCARE";
- ch1_sb_bypass : string := "DONTCARE";
- ch0_rx_sb_bypass : string := "DONTCARE";
- ch1_rx_sb_bypass : string := "DONTCARE";
- ch0_wa_bypass : string := "DONTCARE";
- ch1_wa_bypass : string := "DONTCARE";
- ch0_dec_bypass : string := "DONTCARE";
- ch1_dec_bypass : string := "DONTCARE";
- ch0_ctc_bypass : string := "DONTCARE";
- ch1_ctc_bypass : string := "DONTCARE";
- ch0_rx_gear_bypass : string := "DONTCARE";
- ch1_rx_gear_bypass : string := "DONTCARE";
- ch0_lsm_disable : string := "DONTCARE";
- ch1_lsm_disable : string := "DONTCARE";
- ch0_match_2_enable : string := "DONTCARE";
- ch1_match_2_enable : string := "DONTCARE";
- ch0_match_4_enable : string := "DONTCARE";
- ch1_match_4_enable : string := "DONTCARE";
- ch0_min_ipg_cnt : string := "DONTCARE";
- ch1_min_ipg_cnt : string := "DONTCARE";
- ch0_cc_match_1 : string := "DONTCARE";
- ch1_cc_match_1 : string := "DONTCARE";
- ch0_cc_match_2 : string := "DONTCARE";
- ch1_cc_match_2 : string := "DONTCARE";
- ch0_cc_match_3 : string := "DONTCARE";
- ch1_cc_match_3 : string := "DONTCARE";
- ch0_cc_match_4 : string := "DONTCARE";
- ch1_cc_match_4 : string := "DONTCARE";
- ch0_udf_comma_mask : string := "DONTCARE";
- ch1_udf_comma_mask : string := "DONTCARE";
- ch0_udf_comma_a : string := "DONTCARE";
- ch1_udf_comma_a : string := "DONTCARE";
- ch0_udf_comma_b : string := "DONTCARE";
- ch1_udf_comma_b : string := "DONTCARE";
- ch0_rx_dco_ck_div : string := "DONTCARE";
- ch1_rx_dco_ck_div : string := "DONTCARE";
- ch0_rcv_dcc_en : string := "DONTCARE";
- ch1_rcv_dcc_en : string := "DONTCARE";
- ch0_req_lvl_set : string := "DONTCARE";
- ch1_req_lvl_set : string := "DONTCARE";
- ch0_req_en : string := "DONTCARE";
- ch1_req_en : string := "DONTCARE";
- ch0_rterm_rx : string := "DONTCARE";
- ch1_rterm_rx : string := "DONTCARE";
- ch0_pden_sel : string := "DONTCARE";
- ch1_pden_sel : string := "DONTCARE";
- ch0_ldr_rx2core_sel : string := "DONTCARE";
- ch1_ldr_rx2core_sel : string := "DONTCARE";
- ch0_ldr_core2tx_sel : string := "DONTCARE";
- ch1_ldr_core2tx_sel : string := "DONTCARE";
- ch0_tpwdnb : string := "DONTCARE";
- ch1_tpwdnb : string := "DONTCARE";
- ch0_rate_mode_tx : string := "DONTCARE";
- ch1_rate_mode_tx : string := "DONTCARE";
- ch0_rterm_tx : string := "DONTCARE";
- ch1_rterm_tx : string := "DONTCARE";
- ch0_tx_cm_sel : string := "DONTCARE";
- ch1_tx_cm_sel : string := "DONTCARE";
- ch0_tdrv_pre_en : string := "DONTCARE";
- ch1_tdrv_pre_en : string := "DONTCARE";
- ch0_tdrv_slice0_sel : string := "DONTCARE";
- ch1_tdrv_slice0_sel : string := "DONTCARE";
- ch0_tdrv_slice1_sel : string := "DONTCARE";
- ch1_tdrv_slice1_sel : string := "DONTCARE";
- ch0_tdrv_slice2_sel : string := "DONTCARE";
- ch1_tdrv_slice2_sel : string := "DONTCARE";
- ch0_tdrv_slice3_sel : string := "DONTCARE";
- ch1_tdrv_slice3_sel : string := "DONTCARE";
- ch0_tdrv_slice4_sel : string := "DONTCARE";
- ch1_tdrv_slice4_sel : string := "DONTCARE";
- ch0_tdrv_slice5_sel : string := "DONTCARE";
- ch1_tdrv_slice5_sel : string := "DONTCARE";
- ch0_tdrv_slice0_cur : string := "DONTCARE";
- ch1_tdrv_slice0_cur : string := "DONTCARE";
- ch0_tdrv_slice1_cur : string := "DONTCARE";
- ch1_tdrv_slice1_cur : string := "DONTCARE";
- ch0_tdrv_slice2_cur : string := "DONTCARE";
- ch1_tdrv_slice2_cur : string := "DONTCARE";
- ch0_tdrv_slice3_cur : string := "DONTCARE";
- ch1_tdrv_slice3_cur : string := "DONTCARE";
- ch0_tdrv_slice4_cur : string := "DONTCARE";
- ch1_tdrv_slice4_cur : string := "DONTCARE";
- ch0_tdrv_slice5_cur : string := "DONTCARE";
- ch1_tdrv_slice5_cur : string := "DONTCARE";
- ch0_tdrv_dat_sel : string := "DONTCARE";
- ch1_tdrv_dat_sel : string := "DONTCARE";
- ch0_tx_div11_sel : string := "DONTCARE";
- ch1_tx_div11_sel : string := "DONTCARE";
- ch0_rpwdnb : string := "DONTCARE";
- ch1_rpwdnb : string := "DONTCARE";
- ch0_rate_mode_rx : string := "DONTCARE";
- ch1_rate_mode_rx : string := "DONTCARE";
- ch0_rlos_sel : string := "DONTCARE";
- ch1_rlos_sel : string := "DONTCARE";
- ch0_rx_los_lvl : string := "DONTCARE";
- ch1_rx_los_lvl : string := "DONTCARE";
- ch0_rx_los_ceq : string := "DONTCARE";
- ch1_rx_los_ceq : string := "DONTCARE";
- ch0_rx_los_hyst_en : string := "DONTCARE";
- ch1_rx_los_hyst_en : string := "DONTCARE";
- ch0_rx_los_en : string := "DONTCARE";
- ch1_rx_los_en : string := "DONTCARE";
- ch0_rx_div11_sel : string := "DONTCARE";
- ch1_rx_div11_sel : string := "DONTCARE";
- ch0_sel_sd_rx_clk : string := "DONTCARE";
- ch1_sel_sd_rx_clk : string := "DONTCARE";
- ch0_ff_rx_h_clk_en : string := "DONTCARE";
- ch1_ff_rx_h_clk_en : string := "DONTCARE";
- ch0_ff_rx_f_clk_dis : string := "DONTCARE";
- ch1_ff_rx_f_clk_dis : string := "DONTCARE";
- ch0_ff_tx_h_clk_en : string := "DONTCARE";
- ch1_ff_tx_h_clk_en : string := "DONTCARE";
- ch0_ff_tx_f_clk_dis : string := "DONTCARE";
- ch1_ff_tx_f_clk_dis : string := "DONTCARE";
- ch0_rx_rate_sel : string := "DONTCARE";
- ch1_rx_rate_sel : string := "DONTCARE";
- ch0_tdrv_post_en : string := "DONTCARE";
- ch1_tdrv_post_en : string := "DONTCARE";
- ch0_tx_post_sign : string := "DONTCARE";
- ch1_tx_post_sign : string := "DONTCARE";
- ch0_tx_pre_sign : string := "DONTCARE";
- ch1_tx_pre_sign : string := "DONTCARE";
- ch0_rxterm_cm : string := "DONTCARE";
- ch1_rxterm_cm : string := "DONTCARE";
- ch0_rxin_cm : string := "DONTCARE";
- ch1_rxin_cm : string := "DONTCARE";
- ch0_leq_offset_sel : string := "DONTCARE";
- ch1_leq_offset_sel : string := "DONTCARE";
- ch0_leq_offset_trim : string := "DONTCARE";
- ch1_leq_offset_trim : string := "DONTCARE";
- d_tx_max_rate : string := "DONTCARE";
- ch0_cdr_max_rate : string := "DONTCARE";
- ch1_cdr_max_rate : string := "DONTCARE";
- ch0_txamplitude : string := "DONTCARE";
- ch1_txamplitude : string := "DONTCARE";
- ch0_txdepre : string := "DONTCARE";
- ch1_txdepre : string := "DONTCARE";
- ch0_txdepost : string := "DONTCARE";
- ch1_txdepost : string := "DONTCARE";
- ch0_protocol : string := "DONTCARE";
- ch1_protocol : string := "DONTCARE";
- d_isetlos : string := "DONTCARE";
- d_setirpoly_aux : string := "DONTCARE";
- d_seticonst_aux : string := "DONTCARE";
- d_setirpoly_ch : string := "DONTCARE";
- d_seticonst_ch : string := "DONTCARE";
- d_req_iset : string := "DONTCARE";
- d_pd_iset : string := "DONTCARE";
- d_dco_calib_time_sel : string := "DONTCARE";
- ch0_dcoctlgi : string := "DONTCARE";
- ch1_dcoctlgi : string := "DONTCARE";
- ch0_dcoatddly : string := "DONTCARE";
- ch1_dcoatddly : string := "DONTCARE";
- ch0_dcoatdcfg : string := "DONTCARE";
- ch1_dcoatdcfg : string := "DONTCARE";
- ch0_dcobypsatd : string := "DONTCARE";
- ch1_dcobypsatd : string := "DONTCARE";
- ch0_dcoscalei : string := "DONTCARE";
- ch1_dcoscalei : string := "DONTCARE";
- ch0_dcoitune4lsb : string := "DONTCARE";
- ch1_dcoitune4lsb : string := "DONTCARE";
- ch0_dcoiostune : string := "DONTCARE";
- ch1_dcoiostune : string := "DONTCARE";
- ch0_dcodisbdavoid : string := "DONTCARE";
- ch1_dcodisbdavoid : string := "DONTCARE";
- ch0_dcocaldiv : string := "DONTCARE";
- ch1_dcocaldiv : string := "DONTCARE";
- ch0_dconuoflsb : string := "DONTCARE";
- ch1_dconuoflsb : string := "DONTCARE";
- ch0_dcoiupdnx2 : string := "DONTCARE";
- ch1_dcoiupdnx2 : string := "DONTCARE";
- ch0_dcostep : string := "DONTCARE";
- ch1_dcostep : string := "DONTCARE";
- ch0_dcostartval : string := "DONTCARE";
- ch1_dcostartval : string := "DONTCARE";
- ch0_dcofltdac : string := "DONTCARE";
- ch1_dcofltdac : string := "DONTCARE";
- ch0_dcoitune : string := "DONTCARE";
- ch1_dcoitune : string := "DONTCARE";
- ch0_dcoftnrg : string := "DONTCARE";
- ch1_dcoftnrg : string := "DONTCARE";
- ch0_cdr_cnt4sel : string := "DONTCARE";
- ch1_cdr_cnt4sel : string := "DONTCARE";
- ch0_cdr_cnt8sel : string := "DONTCARE";
- ch1_cdr_cnt8sel : string := "DONTCARE";
- ch0_band_threshold : string := "DONTCARE";
- ch1_band_threshold : string := "DONTCARE";
- ch0_auto_facq_en : string := "DONTCARE";
- ch1_auto_facq_en : string := "DONTCARE";
- ch0_auto_calib_en : string := "DONTCARE";
- ch1_auto_calib_en : string := "DONTCARE";
- ch0_calib_ck_mode : string := "DONTCARE";
- ch1_calib_ck_mode : string := "DONTCARE";
- ch0_reg_band_offset : string := "DONTCARE";
- ch1_reg_band_offset : string := "DONTCARE";
- ch0_reg_band_sel : string := "DONTCARE";
- ch1_reg_band_sel : string := "DONTCARE";
- ch0_reg_idac_sel : string := "DONTCARE";
- ch1_reg_idac_sel : string := "DONTCARE";
- ch0_reg_idac_en : string := "DONTCARE";
- ch1_reg_idac_en : string := "DONTCARE";
- d_txpll_pwdnb : string := "DONTCARE";
- d_setpllrc : string := "DONTCARE";
- d_refck_mode : string := "DONTCARE";
- d_tx_vco_ck_div : string := "DONTCARE";
- d_pll_lol_set : string := "DONTCARE";
- d_rg_en : string := "DONTCARE";
- d_rg_set : string := "DONTCARE";
- d_cmusetiscl4vco : string := "DONTCARE";
- d_cmuseti4vco : string := "DONTCARE";
- d_cmusetinitvct : string := "DONTCARE";
- d_cmusetzgm : string := "DONTCARE";
- d_cmusetp2agm : string := "DONTCARE";
- d_cmusetp1gm : string := "DONTCARE";
- d_cmuseti4cpz : string := "DONTCARE";
- d_cmuseti4cpp : string := "DONTCARE";
- d_cmuseticp4z : string := "DONTCARE";
- d_cmuseticp4p : string := "DONTCARE";
- d_cmusetbiasi : string := "DONTCARE" );
- port (
- ch0_hdinp : in std_logic;
- ch1_hdinp : in std_logic;
- ch0_hdinn : in std_logic;
- ch1_hdinn : in std_logic;
- d_txbit_clkp_from_nd : in std_logic;
- d_txbit_clkn_from_nd : in std_logic;
- d_sync_nd : in std_logic;
- d_txpll_lol_from_nd : in std_logic;
- ch0_rx_refclk : in std_logic;
- ch1_rx_refclk : in std_logic;
- ch0_ff_rxi_clk : in std_logic;
- ch1_ff_rxi_clk : in std_logic;
- ch0_ff_txi_clk : in std_logic;
- ch1_ff_txi_clk : in std_logic;
- ch0_ff_ebrd_clk : in std_logic;
- ch1_ff_ebrd_clk : in std_logic;
- ch0_ff_tx_d_0 : in std_logic;
- ch1_ff_tx_d_0 : in std_logic;
- ch0_ff_tx_d_1 : in std_logic;
- ch1_ff_tx_d_1 : in std_logic;
- ch0_ff_tx_d_2 : in std_logic;
- ch1_ff_tx_d_2 : in std_logic;
- ch0_ff_tx_d_3 : in std_logic;
- ch1_ff_tx_d_3 : in std_logic;
- ch0_ff_tx_d_4 : in std_logic;
- ch1_ff_tx_d_4 : in std_logic;
- ch0_ff_tx_d_5 : in std_logic;
- ch1_ff_tx_d_5 : in std_logic;
- ch0_ff_tx_d_6 : in std_logic;
- ch1_ff_tx_d_6 : in std_logic;
- ch0_ff_tx_d_7 : in std_logic;
- ch1_ff_tx_d_7 : in std_logic;
- ch0_ff_tx_d_8 : in std_logic;
- ch1_ff_tx_d_8 : in std_logic;
- ch0_ff_tx_d_9 : in std_logic;
- ch1_ff_tx_d_9 : in std_logic;
- ch0_ff_tx_d_10 : in std_logic;
- ch1_ff_tx_d_10 : in std_logic;
- ch0_ff_tx_d_11 : in std_logic;
- ch1_ff_tx_d_11 : in std_logic;
- ch0_ff_tx_d_12 : in std_logic;
- ch1_ff_tx_d_12 : in std_logic;
- ch0_ff_tx_d_13 : in std_logic;
- ch1_ff_tx_d_13 : in std_logic;
- ch0_ff_tx_d_14 : in std_logic;
- ch1_ff_tx_d_14 : in std_logic;
- ch0_ff_tx_d_15 : in std_logic;
- ch1_ff_tx_d_15 : in std_logic;
- ch0_ff_tx_d_16 : in std_logic;
- ch1_ff_tx_d_16 : in std_logic;
- ch0_ff_tx_d_17 : in std_logic;
- ch1_ff_tx_d_17 : in std_logic;
- ch0_ff_tx_d_18 : in std_logic;
- ch1_ff_tx_d_18 : in std_logic;
- ch0_ff_tx_d_19 : in std_logic;
- ch1_ff_tx_d_19 : in std_logic;
- ch0_ff_tx_d_20 : in std_logic;
- ch1_ff_tx_d_20 : in std_logic;
- ch0_ff_tx_d_21 : in std_logic;
- ch1_ff_tx_d_21 : in std_logic;
- ch0_ff_tx_d_22 : in std_logic;
- ch1_ff_tx_d_22 : in std_logic;
- ch0_ff_tx_d_23 : in std_logic;
- ch1_ff_tx_d_23 : in std_logic;
- ch0_ffc_ei_en : in std_logic;
- ch1_ffc_ei_en : in std_logic;
- ch0_ffc_pcie_det_en : in std_logic;
- ch1_ffc_pcie_det_en : in std_logic;
- ch0_ffc_pcie_ct : in std_logic;
- ch1_ffc_pcie_ct : in std_logic;
- ch0_ffc_sb_inv_rx : in std_logic;
- ch1_ffc_sb_inv_rx : in std_logic;
- ch0_ffc_enable_cgalign : in std_logic;
- ch1_ffc_enable_cgalign : in std_logic;
- ch0_ffc_signal_detect : in std_logic;
- ch1_ffc_signal_detect : in std_logic;
- ch0_ffc_fb_loopback : in std_logic;
- ch1_ffc_fb_loopback : in std_logic;
- ch0_ffc_sb_pfifo_lp : in std_logic;
- ch1_ffc_sb_pfifo_lp : in std_logic;
- ch0_ffc_pfifo_clr : in std_logic;
- ch1_ffc_pfifo_clr : in std_logic;
- ch0_ffc_rate_mode_rx : in std_logic;
- ch1_ffc_rate_mode_rx : in std_logic;
- ch0_ffc_rate_mode_tx : in std_logic;
- ch1_ffc_rate_mode_tx : in std_logic;
- ch0_ffc_div11_mode_rx : in std_logic;
- ch1_ffc_div11_mode_rx : in std_logic;
- ch0_ffc_rx_gear_mode : in std_logic;
- ch1_ffc_rx_gear_mode : in std_logic;
- ch0_ffc_tx_gear_mode : in std_logic;
- ch1_ffc_tx_gear_mode : in std_logic;
- ch0_ffc_div11_mode_tx : in std_logic;
- ch1_ffc_div11_mode_tx : in std_logic;
- ch0_ffc_ldr_core2tx_en : in std_logic;
- ch1_ffc_ldr_core2tx_en : in std_logic;
- ch0_ffc_lane_tx_rst : in std_logic;
- ch1_ffc_lane_tx_rst : in std_logic;
- ch0_ffc_lane_rx_rst : in std_logic;
- ch1_ffc_lane_rx_rst : in std_logic;
- ch0_ffc_rrst : in std_logic;
- ch1_ffc_rrst : in std_logic;
- ch0_ffc_txpwdnb : in std_logic;
- ch1_ffc_txpwdnb : in std_logic;
- ch0_ffc_rxpwdnb : in std_logic;
- ch1_ffc_rxpwdnb : in std_logic;
- ch0_ldr_core2tx : in std_logic;
- ch1_ldr_core2tx : in std_logic;
- d_sciwdata0 : in std_logic;
- d_sciwdata1 : in std_logic;
- d_sciwdata2 : in std_logic;
- d_sciwdata3 : in std_logic;
- d_sciwdata4 : in std_logic;
- d_sciwdata5 : in std_logic;
- d_sciwdata6 : in std_logic;
- d_sciwdata7 : in std_logic;
- d_sciaddr0 : in std_logic;
- d_sciaddr1 : in std_logic;
- d_sciaddr2 : in std_logic;
- d_sciaddr3 : in std_logic;
- d_sciaddr4 : in std_logic;
- d_sciaddr5 : in std_logic;
- d_scienaux : in std_logic;
- d_sciselaux : in std_logic;
- ch0_scien : in std_logic;
- ch1_scien : in std_logic;
- ch0_scisel : in std_logic;
- ch1_scisel : in std_logic;
- d_scird : in std_logic;
- d_sciwstn : in std_logic;
- d_cyawstn : in std_logic;
- d_ffc_sync_toggle : in std_logic;
- d_ffc_dual_rst : in std_logic;
- d_ffc_macro_rst : in std_logic;
- d_ffc_macropdb : in std_logic;
- d_ffc_trst : in std_logic;
- ch0_ffc_cdr_en_bitslip : in std_logic;
- ch1_ffc_cdr_en_bitslip : in std_logic;
- d_scan_enable : in std_logic;
- d_scan_in_0 : in std_logic;
- d_scan_in_1 : in std_logic;
- d_scan_in_2 : in std_logic;
- d_scan_in_3 : in std_logic;
- d_scan_in_4 : in std_logic;
- d_scan_in_5 : in std_logic;
- d_scan_in_6 : in std_logic;
- d_scan_in_7 : in std_logic;
- d_scan_mode : in std_logic;
- d_scan_reset : in std_logic;
- d_cin0 : in std_logic;
- d_cin1 : in std_logic;
- d_cin2 : in std_logic;
- d_cin3 : in std_logic;
- d_cin4 : in std_logic;
- d_cin5 : in std_logic;
- d_cin6 : in std_logic;
- d_cin7 : in std_logic;
- d_cin8 : in std_logic;
- d_cin9 : in std_logic;
- d_cin10 : in std_logic;
- d_cin11 : in std_logic;
- ch0_hdoutp : out std_logic;
- ch1_hdoutp : out std_logic;
- ch0_hdoutn : out std_logic;
- ch1_hdoutn : out std_logic;
- d_txbit_clkp_to_nd : out std_logic;
- d_txbit_clkn_to_nd : out std_logic;
- d_sync_pulse2nd : out std_logic;
- d_txpll_lol_to_nd : out std_logic;
- ch0_ff_rx_f_clk : out std_logic;
- ch1_ff_rx_f_clk : out std_logic;
- ch0_ff_rx_h_clk : out std_logic;
- ch1_ff_rx_h_clk : out std_logic;
- ch0_ff_tx_f_clk : out std_logic;
- ch1_ff_tx_f_clk : out std_logic;
- ch0_ff_tx_h_clk : out std_logic;
- ch1_ff_tx_h_clk : out std_logic;
- ch0_ff_rx_pclk : out std_logic;
- ch1_ff_rx_pclk : out std_logic;
- ch0_ff_tx_pclk : out std_logic;
- ch1_ff_tx_pclk : out std_logic;
- ch0_ff_rx_d_0 : out std_logic;
- ch1_ff_rx_d_0 : out std_logic;
- ch0_ff_rx_d_1 : out std_logic;
- ch1_ff_rx_d_1 : out std_logic;
- ch0_ff_rx_d_2 : out std_logic;
- ch1_ff_rx_d_2 : out std_logic;
- ch0_ff_rx_d_3 : out std_logic;
- ch1_ff_rx_d_3 : out std_logic;
- ch0_ff_rx_d_4 : out std_logic;
- ch1_ff_rx_d_4 : out std_logic;
- ch0_ff_rx_d_5 : out std_logic;
- ch1_ff_rx_d_5 : out std_logic;
- ch0_ff_rx_d_6 : out std_logic;
- ch1_ff_rx_d_6 : out std_logic;
- ch0_ff_rx_d_7 : out std_logic;
- ch1_ff_rx_d_7 : out std_logic;
- ch0_ff_rx_d_8 : out std_logic;
- ch1_ff_rx_d_8 : out std_logic;
- ch0_ff_rx_d_9 : out std_logic;
- ch1_ff_rx_d_9 : out std_logic;
- ch0_ff_rx_d_10 : out std_logic;
- ch1_ff_rx_d_10 : out std_logic;
- ch0_ff_rx_d_11 : out std_logic;
- ch1_ff_rx_d_11 : out std_logic;
- ch0_ff_rx_d_12 : out std_logic;
- ch1_ff_rx_d_12 : out std_logic;
- ch0_ff_rx_d_13 : out std_logic;
- ch1_ff_rx_d_13 : out std_logic;
- ch0_ff_rx_d_14 : out std_logic;
- ch1_ff_rx_d_14 : out std_logic;
- ch0_ff_rx_d_15 : out std_logic;
- ch1_ff_rx_d_15 : out std_logic;
- ch0_ff_rx_d_16 : out std_logic;
- ch1_ff_rx_d_16 : out std_logic;
- ch0_ff_rx_d_17 : out std_logic;
- ch1_ff_rx_d_17 : out std_logic;
- ch0_ff_rx_d_18 : out std_logic;
- ch1_ff_rx_d_18 : out std_logic;
- ch0_ff_rx_d_19 : out std_logic;
- ch1_ff_rx_d_19 : out std_logic;
- ch0_ff_rx_d_20 : out std_logic;
- ch1_ff_rx_d_20 : out std_logic;
- ch0_ff_rx_d_21 : out std_logic;
- ch1_ff_rx_d_21 : out std_logic;
- ch0_ff_rx_d_22 : out std_logic;
- ch1_ff_rx_d_22 : out std_logic;
- ch0_ff_rx_d_23 : out std_logic;
- ch1_ff_rx_d_23 : out std_logic;
- ch0_ffs_pcie_done : out std_logic;
- ch1_ffs_pcie_done : out std_logic;
- ch0_ffs_pcie_con : out std_logic;
- ch1_ffs_pcie_con : out std_logic;
- ch0_ffs_rlos : out std_logic;
- ch1_ffs_rlos : out std_logic;
- ch0_ffs_ls_sync_status : out std_logic;
- ch1_ffs_ls_sync_status : out std_logic;
- ch0_ffs_cc_underrun : out std_logic;
- ch1_ffs_cc_underrun : out std_logic;
- ch0_ffs_cc_overrun : out std_logic;
- ch1_ffs_cc_overrun : out std_logic;
- ch0_ffs_rxfbfifo_error : out std_logic;
- ch1_ffs_rxfbfifo_error : out std_logic;
- ch0_ffs_txfbfifo_error : out std_logic;
- ch1_ffs_txfbfifo_error : out std_logic;
- ch0_ffs_rlol : out std_logic;
- ch1_ffs_rlol : out std_logic;
- ch0_ffs_skp_added : out std_logic;
- ch1_ffs_skp_added : out std_logic;
- ch0_ffs_skp_deleted : out std_logic;
- ch1_ffs_skp_deleted : out std_logic;
- ch0_ldr_rx2core : out std_logic;
- ch1_ldr_rx2core : out std_logic;
- d_scirdata0 : out std_logic;
- d_scirdata1 : out std_logic;
- d_scirdata2 : out std_logic;
- d_scirdata3 : out std_logic;
- d_scirdata4 : out std_logic;
- d_scirdata5 : out std_logic;
- d_scirdata6 : out std_logic;
- d_scirdata7 : out std_logic;
- d_sciint : out std_logic;
- d_scan_out_0 : out std_logic;
- d_scan_out_1 : out std_logic;
- d_scan_out_2 : out std_logic;
- d_scan_out_3 : out std_logic;
- d_scan_out_4 : out std_logic;
- d_scan_out_5 : out std_logic;
- d_scan_out_6 : out std_logic;
- d_scan_out_7 : out std_logic;
- d_cout0 : out std_logic;
- d_cout1 : out std_logic;
- d_cout2 : out std_logic;
- d_cout3 : out std_logic;
- d_cout4 : out std_logic;
- d_cout5 : out std_logic;
- d_cout6 : out std_logic;
- d_cout7 : out std_logic;
- d_cout8 : out std_logic;
- d_cout9 : out std_logic;
- d_cout10 : out std_logic;
- d_cout11 : out std_logic;
- d_cout12 : out std_logic;
- d_cout13 : out std_logic;
- d_cout14 : out std_logic;
- d_cout15 : out std_logic;
- d_cout16 : out std_logic;
- d_cout17 : out std_logic;
- d_cout18 : out std_logic;
- d_cout19 : out std_logic;
- d_refclki : in std_logic;
- d_ffs_plol : out std_logic );
+ D_MACROPDB : string := "DONTCARE";
+ D_IB_PWDNB : string := "DONTCARE";
+ D_XGE_MODE : string := "DONTCARE";
+ D_LOW_MARK : string := "DONTCARE";
+ D_HIGH_MARK : string := "DONTCARE";
+ D_BUS8BIT_SEL : string := "DONTCARE";
+ D_CDR_LOL_SET : string := "DONTCARE";
+ D_BITCLK_LOCAL_EN : string := "DONTCARE";
+ D_BITCLK_ND_EN : string := "DONTCARE";
+ D_BITCLK_FROM_ND_EN : string := "DONTCARE";
+ D_SYNC_LOCAL_EN : string := "DONTCARE";
+ D_SYNC_ND_EN : string := "DONTCARE";
+ CH0_UC_MODE : string := "DONTCARE";
+ CH1_UC_MODE : string := "DONTCARE";
+ CH0_PCIE_MODE : string := "DONTCARE";
+ CH1_PCIE_MODE : string := "DONTCARE";
+ CH0_RIO_MODE : string := "DONTCARE";
+ CH1_RIO_MODE : string := "DONTCARE";
+ CH0_WA_MODE : string := "DONTCARE";
+ CH1_WA_MODE : string := "DONTCARE";
+ CH0_INVERT_RX : string := "DONTCARE";
+ CH1_INVERT_RX : string := "DONTCARE";
+ CH0_INVERT_TX : string := "DONTCARE";
+ CH1_INVERT_TX : string := "DONTCARE";
+ CH0_PRBS_SELECTION : string := "DONTCARE";
+ CH1_PRBS_SELECTION : string := "DONTCARE";
+ CH0_GE_AN_ENABLE : string := "DONTCARE";
+ CH1_GE_AN_ENABLE : string := "DONTCARE";
+ CH0_PRBS_LOCK : string := "DONTCARE";
+ CH1_PRBS_LOCK : string := "DONTCARE";
+ CH0_PRBS_ENABLE : string := "DONTCARE";
+ CH1_PRBS_ENABLE : string := "DONTCARE";
+ CH0_ENABLE_CG_ALIGN : string := "DONTCARE";
+ CH1_ENABLE_CG_ALIGN : string := "DONTCARE";
+ CH0_TX_GEAR_MODE : string := "DONTCARE";
+ CH1_TX_GEAR_MODE : string := "DONTCARE";
+ CH0_RX_GEAR_MODE : string := "DONTCARE";
+ CH1_RX_GEAR_MODE : string := "DONTCARE";
+ CH0_PCS_DET_TIME_SEL : string := "DONTCARE";
+ CH1_PCS_DET_TIME_SEL : string := "DONTCARE";
+ CH0_PCIE_EI_EN : string := "DONTCARE";
+ CH1_PCIE_EI_EN : string := "DONTCARE";
+ CH0_TX_GEAR_BYPASS : string := "DONTCARE";
+ CH1_TX_GEAR_BYPASS : string := "DONTCARE";
+ CH0_ENC_BYPASS : string := "DONTCARE";
+ CH1_ENC_BYPASS : string := "DONTCARE";
+ CH0_SB_BYPASS : string := "DONTCARE";
+ CH1_SB_BYPASS : string := "DONTCARE";
+ CH0_RX_SB_BYPASS : string := "DONTCARE";
+ CH1_RX_SB_BYPASS : string := "DONTCARE";
+ CH0_WA_BYPASS : string := "DONTCARE";
+ CH1_WA_BYPASS : string := "DONTCARE";
+ CH0_DEC_BYPASS : string := "DONTCARE";
+ CH1_DEC_BYPASS : string := "DONTCARE";
+ CH0_CTC_BYPASS : string := "DONTCARE";
+ CH1_CTC_BYPASS : string := "DONTCARE";
+ CH0_RX_GEAR_BYPASS : string := "DONTCARE";
+ CH1_RX_GEAR_BYPASS : string := "DONTCARE";
+ CH0_LSM_DISABLE : string := "DONTCARE";
+ CH1_LSM_DISABLE : string := "DONTCARE";
+ CH0_MATCH_2_ENABLE : string := "DONTCARE";
+ CH1_MATCH_2_ENABLE : string := "DONTCARE";
+ CH0_MATCH_4_ENABLE : string := "DONTCARE";
+ CH1_MATCH_4_ENABLE : string := "DONTCARE";
+ CH0_MIN_IPG_CNT : string := "DONTCARE";
+ CH1_MIN_IPG_CNT : string := "DONTCARE";
+ CH0_CC_MATCH_1 : string := "DONTCARE";
+ CH1_CC_MATCH_1 : string := "DONTCARE";
+ CH0_CC_MATCH_2 : string := "DONTCARE";
+ CH1_CC_MATCH_2 : string := "DONTCARE";
+ CH0_CC_MATCH_3 : string := "DONTCARE";
+ CH1_CC_MATCH_3 : string := "DONTCARE";
+ CH0_CC_MATCH_4 : string := "DONTCARE";
+ CH1_CC_MATCH_4 : string := "DONTCARE";
+ CH0_UDF_COMMA_MASK : string := "DONTCARE";
+ CH1_UDF_COMMA_MASK : string := "DONTCARE";
+ CH0_UDF_COMMA_A : string := "DONTCARE";
+ CH1_UDF_COMMA_A : string := "DONTCARE";
+ CH0_UDF_COMMA_B : string := "DONTCARE";
+ CH1_UDF_COMMA_B : string := "DONTCARE";
+ CH0_RX_DCO_CK_DIV : string := "DONTCARE";
+ CH1_RX_DCO_CK_DIV : string := "DONTCARE";
+ CH0_RCV_DCC_EN : string := "DONTCARE";
+ CH1_RCV_DCC_EN : string := "DONTCARE";
+ CH0_REQ_LVL_SET : string := "DONTCARE";
+ CH1_REQ_LVL_SET : string := "DONTCARE";
+ CH0_REQ_EN : string := "DONTCARE";
+ CH1_REQ_EN : string := "DONTCARE";
+ CH0_RTERM_RX : string := "DONTCARE";
+ CH1_RTERM_RX : string := "DONTCARE";
+ CH0_PDEN_SEL : string := "DONTCARE";
+ CH1_PDEN_SEL : string := "DONTCARE";
+ CH0_LDR_RX2CORE_SEL : string := "DONTCARE";
+ CH1_LDR_RX2CORE_SEL : string := "DONTCARE";
+ CH0_LDR_CORE2TX_SEL : string := "DONTCARE";
+ CH1_LDR_CORE2TX_SEL : string := "DONTCARE";
+ CH0_TPWDNB : string := "DONTCARE";
+ CH1_TPWDNB : string := "DONTCARE";
+ CH0_RATE_MODE_TX : string := "DONTCARE";
+ CH1_RATE_MODE_TX : string := "DONTCARE";
+ CH0_RTERM_TX : string := "DONTCARE";
+ CH1_RTERM_TX : string := "DONTCARE";
+ CH0_TX_CM_SEL : string := "DONTCARE";
+ CH1_TX_CM_SEL : string := "DONTCARE";
+ CH0_TDRV_PRE_EN : string := "DONTCARE";
+ CH1_TDRV_PRE_EN : string := "DONTCARE";
+ CH0_TDRV_SLICE0_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE0_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE1_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE1_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE2_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE2_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE3_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE3_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE4_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE4_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE5_SEL : string := "DONTCARE";
+ CH1_TDRV_SLICE5_SEL : string := "DONTCARE";
+ CH0_TDRV_SLICE0_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE0_CUR : string := "DONTCARE";
+ CH0_TDRV_SLICE1_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE1_CUR : string := "DONTCARE";
+ CH0_TDRV_SLICE2_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE2_CUR : string := "DONTCARE";
+ CH0_TDRV_SLICE3_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE3_CUR : string := "DONTCARE";
+ CH0_TDRV_SLICE4_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE4_CUR : string := "DONTCARE";
+ CH0_TDRV_SLICE5_CUR : string := "DONTCARE";
+ CH1_TDRV_SLICE5_CUR : string := "DONTCARE";
+ CH0_TDRV_DAT_SEL : string := "DONTCARE";
+ CH1_TDRV_DAT_SEL : string := "DONTCARE";
+ CH0_TX_DIV11_SEL : string := "DONTCARE";
+ CH1_TX_DIV11_SEL : string := "DONTCARE";
+ CH0_RPWDNB : string := "DONTCARE";
+ CH1_RPWDNB : string := "DONTCARE";
+ CH0_RATE_MODE_RX : string := "DONTCARE";
+ CH1_RATE_MODE_RX : string := "DONTCARE";
+ CH0_RLOS_SEL : string := "DONTCARE";
+ CH1_RLOS_SEL : string := "DONTCARE";
+ CH0_RX_LOS_LVL : string := "DONTCARE";
+ CH1_RX_LOS_LVL : string := "DONTCARE";
+ CH0_RX_LOS_CEQ : string := "DONTCARE";
+ CH1_RX_LOS_CEQ : string := "DONTCARE";
+ CH0_RX_LOS_HYST_EN : string := "DONTCARE";
+ CH1_RX_LOS_HYST_EN : string := "DONTCARE";
+ CH0_RX_LOS_EN : string := "DONTCARE";
+ CH1_RX_LOS_EN : string := "DONTCARE";
+ CH0_RX_DIV11_SEL : string := "DONTCARE";
+ CH1_RX_DIV11_SEL : string := "DONTCARE";
+ CH0_SEL_SD_RX_CLK : string := "DONTCARE";
+ CH1_SEL_SD_RX_CLK : string := "DONTCARE";
+ CH0_FF_RX_H_CLK_EN : string := "DONTCARE";
+ CH1_FF_RX_H_CLK_EN : string := "DONTCARE";
+ CH0_FF_RX_F_CLK_DIS : string := "DONTCARE";
+ CH1_FF_RX_F_CLK_DIS : string := "DONTCARE";
+ CH0_FF_TX_H_CLK_EN : string := "DONTCARE";
+ CH1_FF_TX_H_CLK_EN : string := "DONTCARE";
+ CH0_FF_TX_F_CLK_DIS : string := "DONTCARE";
+ CH1_FF_TX_F_CLK_DIS : string := "DONTCARE";
+ CH0_RX_RATE_SEL : string := "DONTCARE";
+ CH1_RX_RATE_SEL : string := "DONTCARE";
+ CH0_TDRV_POST_EN : string := "DONTCARE";
+ CH1_TDRV_POST_EN : string := "DONTCARE";
+ CH0_TX_POST_SIGN : string := "DONTCARE";
+ CH1_TX_POST_SIGN : string := "DONTCARE";
+ CH0_TX_PRE_SIGN : string := "DONTCARE";
+ CH1_TX_PRE_SIGN : string := "DONTCARE";
+ CH0_RXTERM_CM : string := "DONTCARE";
+ CH1_RXTERM_CM : string := "DONTCARE";
+ CH0_RXIN_CM : string := "DONTCARE";
+ CH1_RXIN_CM : string := "DONTCARE";
+ CH0_LEQ_OFFSET_SEL : string := "DONTCARE";
+ CH1_LEQ_OFFSET_SEL : string := "DONTCARE";
+ CH0_LEQ_OFFSET_TRIM : string := "DONTCARE";
+ CH1_LEQ_OFFSET_TRIM : string := "DONTCARE";
+ D_TX_MAX_RATE : string := "DONTCARE";
+ CH0_CDR_MAX_RATE : string := "DONTCARE";
+ CH1_CDR_MAX_RATE : string := "DONTCARE";
+ CH0_TXAMPLITUDE : string := "DONTCARE";
+ CH1_TXAMPLITUDE : string := "DONTCARE";
+ CH0_TXDEPRE : string := "DONTCARE";
+ CH1_TXDEPRE : string := "DONTCARE";
+ CH0_TXDEPOST : string := "DONTCARE";
+ CH1_TXDEPOST : string := "DONTCARE";
+ CH0_PROTOCOL : string := "DONTCARE";
+ CH1_PROTOCOL : string := "DONTCARE";
+ D_ISETLOS : string := "DONTCARE";
+ D_SETIRPOLY_AUX : string := "DONTCARE";
+ D_SETICONST_AUX : string := "DONTCARE";
+ D_SETIRPOLY_CH : string := "DONTCARE";
+ D_SETICONST_CH : string := "DONTCARE";
+ D_REQ_ISET : string := "DONTCARE";
+ D_PD_ISET : string := "DONTCARE";
+ D_DCO_CALIB_TIME_SEL : string := "DONTCARE";
+ CH0_DCOCTLGI : string := "DONTCARE";
+ CH1_DCOCTLGI : string := "DONTCARE";
+ CH0_DCOATDDLY : string := "DONTCARE";
+ CH1_DCOATDDLY : string := "DONTCARE";
+ CH0_DCOATDCFG : string := "DONTCARE";
+ CH1_DCOATDCFG : string := "DONTCARE";
+ CH0_DCOBYPSATD : string := "DONTCARE";
+ CH1_DCOBYPSATD : string := "DONTCARE";
+ CH0_DCOSCALEI : string := "DONTCARE";
+ CH1_DCOSCALEI : string := "DONTCARE";
+ CH0_DCOITUNE4LSB : string := "DONTCARE";
+ CH1_DCOITUNE4LSB : string := "DONTCARE";
+ CH0_DCOIOSTUNE : string := "DONTCARE";
+ CH1_DCOIOSTUNE : string := "DONTCARE";
+ CH0_DCODISBDAVOID : string := "DONTCARE";
+ CH1_DCODISBDAVOID : string := "DONTCARE";
+ CH0_DCOCALDIV : string := "DONTCARE";
+ CH1_DCOCALDIV : string := "DONTCARE";
+ CH0_DCONUOFLSB : string := "DONTCARE";
+ CH1_DCONUOFLSB : string := "DONTCARE";
+ CH0_DCOIUPDNX2 : string := "DONTCARE";
+ CH1_DCOIUPDNX2 : string := "DONTCARE";
+ CH0_DCOSTEP : string := "DONTCARE";
+ CH1_DCOSTEP : string := "DONTCARE";
+ CH0_DCOSTARTVAL : string := "DONTCARE";
+ CH1_DCOSTARTVAL : string := "DONTCARE";
+ CH0_DCOFLTDAC : string := "DONTCARE";
+ CH1_DCOFLTDAC : string := "DONTCARE";
+ CH0_DCOITUNE : string := "DONTCARE";
+ CH1_DCOITUNE : string := "DONTCARE";
+ CH0_DCOFTNRG : string := "DONTCARE";
+ CH1_DCOFTNRG : string := "DONTCARE";
+ CH0_CDR_CNT4SEL : string := "DONTCARE";
+ CH1_CDR_CNT4SEL : string := "DONTCARE";
+ CH0_CDR_CNT8SEL : string := "DONTCARE";
+ CH1_CDR_CNT8SEL : string := "DONTCARE";
+ CH0_BAND_THRESHOLD : string := "DONTCARE";
+ CH1_BAND_THRESHOLD : string := "DONTCARE";
+ CH0_AUTO_FACQ_EN : string := "DONTCARE";
+ CH1_AUTO_FACQ_EN : string := "DONTCARE";
+ CH0_AUTO_CALIB_EN : string := "DONTCARE";
+ CH1_AUTO_CALIB_EN : string := "DONTCARE";
+ CH0_CALIB_CK_MODE : string := "DONTCARE";
+ CH1_CALIB_CK_MODE : string := "DONTCARE";
+ CH0_REG_BAND_OFFSET : string := "DONTCARE";
+ CH1_REG_BAND_OFFSET : string := "DONTCARE";
+ CH0_REG_BAND_SEL : string := "DONTCARE";
+ CH1_REG_BAND_SEL : string := "DONTCARE";
+ CH0_REG_IDAC_SEL : string := "DONTCARE";
+ CH1_REG_IDAC_SEL : string := "DONTCARE";
+ CH0_REG_IDAC_EN : string := "DONTCARE";
+ CH1_REG_IDAC_EN : string := "DONTCARE";
+ D_TXPLL_PWDNB : string := "DONTCARE";
+ D_SETPLLRC : string := "DONTCARE";
+ D_REFCK_MODE : string := "DONTCARE";
+ D_TX_VCO_CK_DIV : string := "DONTCARE";
+ D_PLL_LOL_SET : string := "DONTCARE";
+ D_RG_EN : string := "DONTCARE";
+ D_RG_SET : string := "DONTCARE";
+ D_CMUSETISCL4VCO : string := "DONTCARE";
+ D_CMUSETI4VCO : string := "DONTCARE";
+ D_CMUSETINITVCT : string := "DONTCARE";
+ D_CMUSETZGM : string := "DONTCARE";
+ D_CMUSETP2AGM : string := "DONTCARE";
+ D_CMUSETP1GM : string := "DONTCARE";
+ D_CMUSETI4CPZ : string := "DONTCARE";
+ D_CMUSETI4CPP : string := "DONTCARE";
+ D_CMUSETICP4Z : string := "DONTCARE";
+ D_CMUSETICP4P : string := "DONTCARE";
+ D_CMUSETBIASI : string := "DONTCARE" );
+ port (
+ CH0_HDINP : in std_logic;
+ CH1_HDINP : in std_logic;
+ CH0_HDINN : in std_logic;
+ CH1_HDINN : in std_logic;
+ D_TXBIT_CLKP_FROM_ND : in std_logic;
+ D_TXBIT_CLKN_FROM_ND : in std_logic;
+ D_SYNC_ND : in std_logic;
+ D_TXPLL_LOL_FROM_ND : in std_logic;
+ CH0_RX_REFCLK : in std_logic;
+ CH1_RX_REFCLK : in std_logic;
+ CH0_FF_RXI_CLK : in std_logic;
+ CH1_FF_RXI_CLK : in std_logic;
+ CH0_FF_TXI_CLK : in std_logic;
+ CH1_FF_TXI_CLK : in std_logic;
+ CH0_FF_EBRD_CLK : in std_logic;
+ CH1_FF_EBRD_CLK : in std_logic;
+ CH0_FF_TX_D_0 : in std_logic;
+ CH1_FF_TX_D_0 : in std_logic;
+ CH0_FF_TX_D_1 : in std_logic;
+ CH1_FF_TX_D_1 : in std_logic;
+ CH0_FF_TX_D_2 : in std_logic;
+ CH1_FF_TX_D_2 : in std_logic;
+ CH0_FF_TX_D_3 : in std_logic;
+ CH1_FF_TX_D_3 : in std_logic;
+ CH0_FF_TX_D_4 : in std_logic;
+ CH1_FF_TX_D_4 : in std_logic;
+ CH0_FF_TX_D_5 : in std_logic;
+ CH1_FF_TX_D_5 : in std_logic;
+ CH0_FF_TX_D_6 : in std_logic;
+ CH1_FF_TX_D_6 : in std_logic;
+ CH0_FF_TX_D_7 : in std_logic;
+ CH1_FF_TX_D_7 : in std_logic;
+ CH0_FF_TX_D_8 : in std_logic;
+ CH1_FF_TX_D_8 : in std_logic;
+ CH0_FF_TX_D_9 : in std_logic;
+ CH1_FF_TX_D_9 : in std_logic;
+ CH0_FF_TX_D_10 : in std_logic;
+ CH1_FF_TX_D_10 : in std_logic;
+ CH0_FF_TX_D_11 : in std_logic;
+ CH1_FF_TX_D_11 : in std_logic;
+ CH0_FF_TX_D_12 : in std_logic;
+ CH1_FF_TX_D_12 : in std_logic;
+ CH0_FF_TX_D_13 : in std_logic;
+ CH1_FF_TX_D_13 : in std_logic;
+ CH0_FF_TX_D_14 : in std_logic;
+ CH1_FF_TX_D_14 : in std_logic;
+ CH0_FF_TX_D_15 : in std_logic;
+ CH1_FF_TX_D_15 : in std_logic;
+ CH0_FF_TX_D_16 : in std_logic;
+ CH1_FF_TX_D_16 : in std_logic;
+ CH0_FF_TX_D_17 : in std_logic;
+ CH1_FF_TX_D_17 : in std_logic;
+ CH0_FF_TX_D_18 : in std_logic;
+ CH1_FF_TX_D_18 : in std_logic;
+ CH0_FF_TX_D_19 : in std_logic;
+ CH1_FF_TX_D_19 : in std_logic;
+ CH0_FF_TX_D_20 : in std_logic;
+ CH1_FF_TX_D_20 : in std_logic;
+ CH0_FF_TX_D_21 : in std_logic;
+ CH1_FF_TX_D_21 : in std_logic;
+ CH0_FF_TX_D_22 : in std_logic;
+ CH1_FF_TX_D_22 : in std_logic;
+ CH0_FF_TX_D_23 : in std_logic;
+ CH1_FF_TX_D_23 : in std_logic;
+ CH0_FFC_EI_EN : in std_logic;
+ CH1_FFC_EI_EN : in std_logic;
+ CH0_FFC_PCIE_DET_EN : in std_logic;
+ CH1_FFC_PCIE_DET_EN : in std_logic;
+ CH0_FFC_PCIE_CT : in std_logic;
+ CH1_FFC_PCIE_CT : in std_logic;
+ CH0_FFC_SB_INV_RX : in std_logic;
+ CH1_FFC_SB_INV_RX : in std_logic;
+ CH0_FFC_ENABLE_CGALIGN : in std_logic;
+ CH1_FFC_ENABLE_CGALIGN : in std_logic;
+ CH0_FFC_SIGNAL_DETECT : in std_logic;
+ CH1_FFC_SIGNAL_DETECT : in std_logic;
+ CH0_FFC_FB_LOOPBACK : in std_logic;
+ CH1_FFC_FB_LOOPBACK : in std_logic;
+ CH0_FFC_SB_PFIFO_LP : in std_logic;
+ CH1_FFC_SB_PFIFO_LP : in std_logic;
+ CH0_FFC_PFIFO_CLR : in std_logic;
+ CH1_FFC_PFIFO_CLR : in std_logic;
+ CH0_FFC_RATE_MODE_RX : in std_logic;
+ CH1_FFC_RATE_MODE_RX : in std_logic;
+ CH0_FFC_RATE_MODE_TX : in std_logic;
+ CH1_FFC_RATE_MODE_TX : in std_logic;
+ CH0_FFC_DIV11_MODE_RX : in std_logic;
+ CH1_FFC_DIV11_MODE_RX : in std_logic;
+ CH0_FFC_RX_GEAR_MODE : in std_logic;
+ CH1_FFC_RX_GEAR_MODE : in std_logic;
+ CH0_FFC_TX_GEAR_MODE : in std_logic;
+ CH1_FFC_TX_GEAR_MODE : in std_logic;
+ CH0_FFC_DIV11_MODE_TX : in std_logic;
+ CH1_FFC_DIV11_MODE_TX : in std_logic;
+ CH0_FFC_LDR_CORE2TX_EN : in std_logic;
+ CH1_FFC_LDR_CORE2TX_EN : in std_logic;
+ CH0_FFC_LANE_TX_RST : in std_logic;
+ CH1_FFC_LANE_TX_RST : in std_logic;
+ CH0_FFC_LANE_RX_RST : in std_logic;
+ CH1_FFC_LANE_RX_RST : in std_logic;
+ CH0_FFC_RRST : in std_logic;
+ CH1_FFC_RRST : in std_logic;
+ CH0_FFC_TXPWDNB : in std_logic;
+ CH1_FFC_TXPWDNB : in std_logic;
+ CH0_FFC_RXPWDNB : in std_logic;
+ CH1_FFC_RXPWDNB : in std_logic;
+ CH0_LDR_CORE2TX : in std_logic;
+ CH1_LDR_CORE2TX : in std_logic;
+ D_SCIWDATA0 : in std_logic;
+ D_SCIWDATA1 : in std_logic;
+ D_SCIWDATA2 : in std_logic;
+ D_SCIWDATA3 : in std_logic;
+ D_SCIWDATA4 : in std_logic;
+ D_SCIWDATA5 : in std_logic;
+ D_SCIWDATA6 : in std_logic;
+ D_SCIWDATA7 : in std_logic;
+ D_SCIADDR0 : in std_logic;
+ D_SCIADDR1 : in std_logic;
+ D_SCIADDR2 : in std_logic;
+ D_SCIADDR3 : in std_logic;
+ D_SCIADDR4 : in std_logic;
+ D_SCIADDR5 : in std_logic;
+ D_SCIENAUX : in std_logic;
+ D_SCISELAUX : in std_logic;
+ CH0_SCIEN : in std_logic;
+ CH1_SCIEN : in std_logic;
+ CH0_SCISEL : in std_logic;
+ CH1_SCISEL : in std_logic;
+ D_SCIRD : in std_logic;
+ D_SCIWSTN : in std_logic;
+ D_CYAWSTN : in std_logic;
+ D_FFC_SYNC_TOGGLE : in std_logic;
+ D_FFC_DUAL_RST : in std_logic;
+ D_FFC_MACRO_RST : in std_logic;
+ D_FFC_MACROPDB : in std_logic;
+ D_FFC_TRST : in std_logic;
+ CH0_FFC_CDR_EN_BITSLIP : in std_logic;
+ CH1_FFC_CDR_EN_BITSLIP : in std_logic;
+ D_SCAN_ENABLE : in std_logic;
+ D_SCAN_IN_0 : in std_logic;
+ D_SCAN_IN_1 : in std_logic;
+ D_SCAN_IN_2 : in std_logic;
+ D_SCAN_IN_3 : in std_logic;
+ D_SCAN_IN_4 : in std_logic;
+ D_SCAN_IN_5 : in std_logic;
+ D_SCAN_IN_6 : in std_logic;
+ D_SCAN_IN_7 : in std_logic;
+ D_SCAN_MODE : in std_logic;
+ D_SCAN_RESET : in std_logic;
+ D_CIN0 : in std_logic;
+ D_CIN1 : in std_logic;
+ D_CIN2 : in std_logic;
+ D_CIN3 : in std_logic;
+ D_CIN4 : in std_logic;
+ D_CIN5 : in std_logic;
+ D_CIN6 : in std_logic;
+ D_CIN7 : in std_logic;
+ D_CIN8 : in std_logic;
+ D_CIN9 : in std_logic;
+ D_CIN10 : in std_logic;
+ D_CIN11 : in std_logic;
+ CH0_HDOUTP : out std_logic;
+ CH1_HDOUTP : out std_logic;
+ CH0_HDOUTN : out std_logic;
+ CH1_HDOUTN : out std_logic;
+ D_TXBIT_CLKP_TO_ND : out std_logic;
+ D_TXBIT_CLKN_TO_ND : out std_logic;
+ D_SYNC_PULSE2ND : out std_logic;
+ D_TXPLL_LOL_TO_ND : out std_logic;
+ CH0_FF_RX_F_CLK : out std_logic;
+ CH1_FF_RX_F_CLK : out std_logic;
+ CH0_FF_RX_H_CLK : out std_logic;
+ CH1_FF_RX_H_CLK : out std_logic;
+ CH0_FF_TX_F_CLK : out std_logic;
+ CH1_FF_TX_F_CLK : out std_logic;
+ CH0_FF_TX_H_CLK : out std_logic;
+ CH1_FF_TX_H_CLK : out std_logic;
+ CH0_FF_RX_PCLK : out std_logic;
+ CH1_FF_RX_PCLK : out std_logic;
+ CH0_FF_TX_PCLK : out std_logic;
+ CH1_FF_TX_PCLK : out std_logic;
+ CH0_FF_RX_D_0 : out std_logic;
+ CH1_FF_RX_D_0 : out std_logic;
+ CH0_FF_RX_D_1 : out std_logic;
+ CH1_FF_RX_D_1 : out std_logic;
+ CH0_FF_RX_D_2 : out std_logic;
+ CH1_FF_RX_D_2 : out std_logic;
+ CH0_FF_RX_D_3 : out std_logic;
+ CH1_FF_RX_D_3 : out std_logic;
+ CH0_FF_RX_D_4 : out std_logic;
+ CH1_FF_RX_D_4 : out std_logic;
+ CH0_FF_RX_D_5 : out std_logic;
+ CH1_FF_RX_D_5 : out std_logic;
+ CH0_FF_RX_D_6 : out std_logic;
+ CH1_FF_RX_D_6 : out std_logic;
+ CH0_FF_RX_D_7 : out std_logic;
+ CH1_FF_RX_D_7 : out std_logic;
+ CH0_FF_RX_D_8 : out std_logic;
+ CH1_FF_RX_D_8 : out std_logic;
+ CH0_FF_RX_D_9 : out std_logic;
+ CH1_FF_RX_D_9 : out std_logic;
+ CH0_FF_RX_D_10 : out std_logic;
+ CH1_FF_RX_D_10 : out std_logic;
+ CH0_FF_RX_D_11 : out std_logic;
+ CH1_FF_RX_D_11 : out std_logic;
+ CH0_FF_RX_D_12 : out std_logic;
+ CH1_FF_RX_D_12 : out std_logic;
+ CH0_FF_RX_D_13 : out std_logic;
+ CH1_FF_RX_D_13 : out std_logic;
+ CH0_FF_RX_D_14 : out std_logic;
+ CH1_FF_RX_D_14 : out std_logic;
+ CH0_FF_RX_D_15 : out std_logic;
+ CH1_FF_RX_D_15 : out std_logic;
+ CH0_FF_RX_D_16 : out std_logic;
+ CH1_FF_RX_D_16 : out std_logic;
+ CH0_FF_RX_D_17 : out std_logic;
+ CH1_FF_RX_D_17 : out std_logic;
+ CH0_FF_RX_D_18 : out std_logic;
+ CH1_FF_RX_D_18 : out std_logic;
+ CH0_FF_RX_D_19 : out std_logic;
+ CH1_FF_RX_D_19 : out std_logic;
+ CH0_FF_RX_D_20 : out std_logic;
+ CH1_FF_RX_D_20 : out std_logic;
+ CH0_FF_RX_D_21 : out std_logic;
+ CH1_FF_RX_D_21 : out std_logic;
+ CH0_FF_RX_D_22 : out std_logic;
+ CH1_FF_RX_D_22 : out std_logic;
+ CH0_FF_RX_D_23 : out std_logic;
+ CH1_FF_RX_D_23 : out std_logic;
+ CH0_FFS_PCIE_DONE : out std_logic;
+ CH1_FFS_PCIE_DONE : out std_logic;
+ CH0_FFS_PCIE_CON : out std_logic;
+ CH1_FFS_PCIE_CON : out std_logic;
+ CH0_FFS_RLOS : out std_logic;
+ CH1_FFS_RLOS : out std_logic;
+ CH0_FFS_LS_SYNC_STATUS : out std_logic;
+ CH1_FFS_LS_SYNC_STATUS : out std_logic;
+ CH0_FFS_CC_UNDERRUN : out std_logic;
+ CH1_FFS_CC_UNDERRUN : out std_logic;
+ CH0_FFS_CC_OVERRUN : out std_logic;
+ CH1_FFS_CC_OVERRUN : out std_logic;
+ CH0_FFS_RXFBFIFO_ERROR : out std_logic;
+ CH1_FFS_RXFBFIFO_ERROR : out std_logic;
+ CH0_FFS_TXFBFIFO_ERROR : out std_logic;
+ CH1_FFS_TXFBFIFO_ERROR : out std_logic;
+ CH0_FFS_RLOL : out std_logic;
+ CH1_FFS_RLOL : out std_logic;
+ CH0_FFS_SKP_ADDED : out std_logic;
+ CH1_FFS_SKP_ADDED : out std_logic;
+ CH0_FFS_SKP_DELETED : out std_logic;
+ CH1_FFS_SKP_DELETED : out std_logic;
+ CH0_LDR_RX2CORE : out std_logic;
+ CH1_LDR_RX2CORE : out std_logic;
+ D_SCIRDATA0 : out std_logic;
+ D_SCIRDATA1 : out std_logic;
+ D_SCIRDATA2 : out std_logic;
+ D_SCIRDATA3 : out std_logic;
+ D_SCIRDATA4 : out std_logic;
+ D_SCIRDATA5 : out std_logic;
+ D_SCIRDATA6 : out std_logic;
+ D_SCIRDATA7 : out std_logic;
+ D_SCIINT : out std_logic;
+ D_SCAN_OUT_0 : out std_logic;
+ D_SCAN_OUT_1 : out std_logic;
+ D_SCAN_OUT_2 : out std_logic;
+ D_SCAN_OUT_3 : out std_logic;
+ D_SCAN_OUT_4 : out std_logic;
+ D_SCAN_OUT_5 : out std_logic;
+ D_SCAN_OUT_6 : out std_logic;
+ D_SCAN_OUT_7 : out std_logic;
+ D_COUT0 : out std_logic;
+ D_COUT1 : out std_logic;
+ D_COUT2 : out std_logic;
+ D_COUT3 : out std_logic;
+ D_COUT4 : out std_logic;
+ D_COUT5 : out std_logic;
+ D_COUT6 : out std_logic;
+ D_COUT7 : out std_logic;
+ D_COUT8 : out std_logic;
+ D_COUT9 : out std_logic;
+ D_COUT10 : out std_logic;
+ D_COUT11 : out std_logic;
+ D_COUT12 : out std_logic;
+ D_COUT13 : out std_logic;
+ D_COUT14 : out std_logic;
+ D_COUT15 : out std_logic;
+ D_COUT16 : out std_logic;
+ D_COUT17 : out std_logic;
+ D_COUT18 : out std_logic;
+ D_COUT19 : out std_logic;
+ D_REFCLKI : in std_logic;
+ D_FFS_PLOL : out std_logic );
end component;
end package;