testsuite: Add formal tests (#57)

* Add formal tests for shift operations

* ci: build ghdl/synth:formal and run test suites in it

* add testsuite/formal/testsuite.sh

* create testsuite/issues

* ci: remove a level of grouping

* testenv: fix SYMBIYOSYS

* refactor

* testsuite/formal/shifts: Add check for shifts > vector length

3 files changed, 0 insertions, 62 deletions

diff --git a/testsuite/issue7/ref.vhdl b/testsuite/issue7/ref.vhdl
deleted file mode 100644
index 63dc225..0000000
--- a/testsuite/issue7/ref.vhdl
+++ /dev/null
@@ -1,13 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity vector is
-  port (led0, led1, led2, led3, led4, led5, led6, led7: out std_logic);
-end vector;
-
-architecture ref of vector is
-  signal v : std_logic_vector(7 downto 0);
-begin
-  -- It works ok
-  (led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
-end;
diff --git a/testsuite/issue7/testsuite.sh b/testsuite/issue7/testsuite.sh
deleted file mode 100755
index bdafcca..0000000
--- a/testsuite/issue7/testsuite.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-. ../testenv.sh
-
-run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v"
-run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v"
-
-run_yosys -Q -p '
- read_verilog ref.v
- rename vector ref
-
- read_verilog vector.v
- equiv_make ref vector equiv
-
- hierarchy -top equiv
- equiv_simple
- equiv_status -assert'
-
-clean
-rm -f *.v
diff --git a/testsuite/issue7/vector.vhdl b/testsuite/issue7/vector.vhdl
deleted file mode 100644
index 3ab2e24..0000000
--- a/testsuite/issue7/vector.vhdl
+++ /dev/null
@@ -1,29 +0,0 @@
-architecture synth of vector is
-
-signal v : std_logic_vector(7 downto 0);
-
-begin
-
-  -- It works ok
-  --(led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
-
-  -- It is assigned in reverse order (led7 should be MSB, but it is assigned
-  -- the lsb. led0 should be the lsb, but is assigned as the MSB)
-  v <= std_logic_vector'("10101010");
-  led7 <= v(7);
-  led6 <= v(6);
-  led5 <= v(5);
-  led4 <= v(4);
-  led3 <= v(3);
-  led2 <= v(2);
-  led1 <= v(1);
-  led0 <= v(0);
-
-end synth;
-
-architecture ok of vector is
-  signal v : std_logic_vector(7 downto 0);
-begin
-  -- It works ok
-  (led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
-end ok;