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author | Tristan Gingold <tgingold@free.fr> | 2017-02-14 05:46:00 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-14 05:46:00 +0100 |
commit | e52d581c33248aefc47e7c97ce6978d6bda31bfe (patch) | |
tree | 42f61dabe4f2f8816725631eb30f4ddafd6fae6b /testsuite/issue4 | |
parent | 37f32aeba8adf5696f64b4d17298a7e3e5c4a38e (diff) | |
download | ghdl-yosys-plugin-e52d581c33248aefc47e7c97ce6978d6bda31bfe.tar.gz ghdl-yosys-plugin-e52d581c33248aefc47e7c97ce6978d6bda31bfe.tar.bz2 ghdl-yosys-plugin-e52d581c33248aefc47e7c97ce6978d6bda31bfe.zip |
Add tests for icezum
Diffstat (limited to 'testsuite/issue4')
-rw-r--r-- | testsuite/issue4/novector.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/issue4/novector.vhdl b/testsuite/issue4/novector.vhdl new file mode 100644 index 0000000..a3c2c46 --- /dev/null +++ b/testsuite/issue4/novector.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity no_vector is + port (led0: out std_logic); +end no_vector; + +architecture synth of no_vector is + +signal nv : std_logic; + +begin + nv <= '1'; + led0 <= nv; +end synth; |