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author | Tristan Gingold <tgingold@free.fr> | 2017-02-13 21:27:58 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-13 21:27:58 +0100 |
commit | 37f32aeba8adf5696f64b4d17298a7e3e5c4a38e (patch) | |
tree | e185c9e6bcbc41f11153e5c4dec717ca28ef2490 /testsuite/issue4/vector.vhdl | |
parent | d343b8fc2861db2dce9d860d517c6cc83acbdc75 (diff) | |
download | ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.tar.gz ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.tar.bz2 ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.zip |
Add reproducers for #4
Diffstat (limited to 'testsuite/issue4/vector.vhdl')
-rw-r--r-- | testsuite/issue4/vector.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/issue4/vector.vhdl b/testsuite/issue4/vector.vhdl new file mode 100644 index 0000000..de74ea9 --- /dev/null +++ b/testsuite/issue4/vector.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (led0: out std_logic); +end vector; + +architecture synth of vector is + +signal v : std_logic_vector(7 downto 0); + +begin + v <= std_logic_vector'("10101010"); + led0 <= v(0); +end synth; |