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author | Tristan Gingold <tgingold@free.fr> | 2017-02-26 15:45:38 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-26 15:45:38 +0100 |
commit | c49b0cfe4e8e1666fba3493dfe887a8e0744dafe (patch) | |
tree | 0de03d41c6130ae979ff57bc74c71880b76a03b4 /testsuite/issue11/test_nand.vhdl | |
parent | 3b0c85f2ffd9471a8abc5eef1b0f15699241d66a (diff) | |
download | ghdl-yosys-plugin-c49b0cfe4e8e1666fba3493dfe887a8e0744dafe.tar.gz ghdl-yosys-plugin-c49b0cfe4e8e1666fba3493dfe887a8e0744dafe.tar.bz2 ghdl-yosys-plugin-c49b0cfe4e8e1666fba3493dfe887a8e0744dafe.zip |
Add tests for nand, nor, xnor.
Diffstat (limited to 'testsuite/issue11/test_nand.vhdl')
-rw-r--r-- | testsuite/issue11/test_nand.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/issue11/test_nand.vhdl b/testsuite/issue11/test_nand.vhdl new file mode 100644 index 0000000..ae60966 --- /dev/null +++ b/testsuite/issue11/test_nand.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_nand is port ( + sel0, sel1: in std_logic; + c: out std_logic); +end test_nand; + +architecture synth of test_nand is +begin + + c <= sel1 nand sel0; + +end synth; |