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author | Tristan Gingold <tgingold@free.fr> | 2020-11-18 07:54:54 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-11-18 07:55:23 +0100 |
commit | 3676b888c5adf51788a1398384152e6a74406f6c (patch) | |
tree | cd45a9293e34ed1b988cef73b332a73d0019072a /testsuite/examples/blackbox/blackbox2.vhdl | |
parent | bc79e04df9302636045a507c466ed4995da0aadf (diff) | |
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Add a test for previous commit
Diffstat (limited to 'testsuite/examples/blackbox/blackbox2.vhdl')
-rw-r--r-- | testsuite/examples/blackbox/blackbox2.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/examples/blackbox/blackbox2.vhdl b/testsuite/examples/blackbox/blackbox2.vhdl new file mode 100644 index 0000000..656fe22 --- /dev/null +++ b/testsuite/examples/blackbox/blackbox2.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity blackbox2 is + port (a, b : std_logic; + o : out std_logic); +end; + +architecture behav of blackbox2 is + component my_blackbox is + port (a, b : std_logic; + \OUT\ : out std_logic); + end component; +begin + inst: my_blackbox + port map (a => a, b => b, \OUT\ => o); +end behav; + |