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| author | T. Meissner <programming@goodcleanfun.de> | 2019-10-06 20:12:26 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-06 20:12:26 +0200 |
| commit | bf8b41da7f0650d93b79447a2a62313b15afc9af (patch) | |
| tree | a407fa476537307d2af7c11cf5f5eaf1df4e11b1 /src/ghdl.cc | |
| parent | 14b5cbdad8da4e0957f02dd94e3ff94d49772f18 (diff) | |
| download | ghdl-yosys-plugin-bf8b41da7f0650d93b79447a2a62313b15afc9af.tar.gz ghdl-yosys-plugin-bf8b41da7f0650d93b79447a2a62313b15afc9af.tar.bz2 ghdl-yosys-plugin-bf8b41da7f0650d93b79447a2a62313b15afc9af.zip | |
Handle Id_Asr (#55)
Diffstat (limited to 'src/ghdl.cc')
| -rw-r--r-- | src/ghdl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index e44fa78..58c738e 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -299,6 +299,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: case Id_Lsr: case Id_Lsl: + case Id_Asr: case Id_Assert: // No output case Id_Assume: // No output case Id_Cover: // No output @@ -432,6 +433,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Lsr: module->addShr(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Asr: + module->addSshr(to_str(iname), IN(0), IN(1), OUT(0), true); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; |