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| author | Alastair M. Robinson <robinsonb5@gmail.com> | 2022-08-31 20:42:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-31 21:42:24 +0200 |
| commit | 7aed75ba30157e52de737b2e082d2e1b6f82435d (patch) | |
| tree | 0e006b1d82d599a86e9e0897fbeea1fd58e68764 /src/ghdl.cc | |
| parent | 90c54117cd27fcdc18ce18fb32a68062fa09e620 (diff) | |
| download | ghdl-yosys-plugin-7aed75ba30157e52de737b2e082d2e1b6f82435d.tar.gz ghdl-yosys-plugin-7aed75ba30157e52de737b2e082d2e1b6f82435d.tar.bz2 ghdl-yosys-plugin-7aed75ba30157e52de737b2e082d2e1b6f82435d.zip | |
Fix to block RAM handling as per https://github.com/YosysHQ/yosys/issues/3364#issuecomment-1148066807 (#171)
Diffstat (limited to 'src/ghdl.cc')
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index fb6cb8e..edc60cf 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -563,7 +563,7 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net vec.resize(nbr_wr); // Emitted write ports (ie j <= widx) don't have priority. for (int j = 0; j < nbr_wr; j++) - vec[j] = j <= widx ? RTLIL::State::S0 : RTLIL::State::S1; + vec[j] = j < widx ? RTLIL::State::S1 : RTLIL::State::S0; p->parameters[ID::PRIORITY_MASK] = Const(vec); break; default: |