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author | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
commit | bd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch) | |
tree | 194781d16b082ae259f17dd8dc12b84b04ec7105 /icestick/blink.vhdl | |
parent | fa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff) | |
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Add examples
Diffstat (limited to 'icestick/blink.vhdl')
-rw-r--r-- | icestick/blink.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/icestick/blink.vhdl b/icestick/blink.vhdl new file mode 100644 index 0000000..d7e6dd4 --- /dev/null +++ b/icestick/blink.vhdl @@ -0,0 +1,23 @@ +architecture blink of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= not clk_4hz; + else + counter := counter + 1; + end if; + end if; + end process; + + led1 <= clk_4hz; + led2 <= clk_4hz; + led3 <= clk_4hz; + led4 <= clk_4hz; + led5 <= clk_4hz; +end blink; |