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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-07-16 18:47:04 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-07-16 18:47:04 +0200 |
| commit | db6d9f374de1eb1c074c2b9828bc6d99055b3624 (patch) | |
| tree | b1ee7adb1b89121abab55ea226f8e989c1007671 /ghdl | |
| parent | 447d2627ea977d1577a70c7d0417b05764de0ad3 (diff) | |
| download | ghdl-yosys-plugin-db6d9f374de1eb1c074c2b9828bc6d99055b3624.tar.gz ghdl-yosys-plugin-db6d9f374de1eb1c074c2b9828bc6d99055b3624.tar.bz2 ghdl-yosys-plugin-db6d9f374de1eb1c074c2b9828bc6d99055b3624.zip | |
add comparison cells and adff (#23)
Diffstat (limited to 'ghdl')
| -rw-r--r-- | ghdl/ghdl.cc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index 617b4ad..f11eaca 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -210,9 +210,14 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Mux2: case Id_Mux4: case Id_Dff: + case Id_Adff: case Id_Idff: case Id_Eq: case Id_Ne: + case Id_Ult: + case Id_Ule: + case Id_Ugt: + case Id_Uge: case Id_Not: case Id_Red_Or: case Id_Red_And: @@ -299,6 +304,18 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Ne: module->addNe(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Ult: + module->addLt(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Ule: + module->addLe(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Ugt: + module->addGt(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Uge: + module->addGe(to_str(iname), IN(0), IN(1), OUT(0)); + break; case Id_Red_Or: module->addReduceOr(to_str(iname), IN(0), OUT(0)); break; @@ -317,6 +334,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) net_map[get_output(inst, 0).id]->attributes["\\init"] = IN(2).as_const(); } break; + case Id_Adff: + module->addAdff(to_str(iname), IN(0), IN(2), IN(1), OUT(0), IN(3).as_const()); + break; case Id_Mux4: { SigSpec Sel0 = IN(0).extract(0, 1); |