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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-27 05:32:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-27 05:32:09 +0200 |
| commit | 91278660dc9776892bde891ea7ad6097c4ea8428 (patch) | |
| tree | 5d527e86479d242989c34377df346678bd958421 | |
| parent | bb5ba54d5251555c693d2255877e8980e176209e (diff) | |
| download | ghdl-yosys-plugin-91278660dc9776892bde891ea7ad6097c4ea8428.tar.gz ghdl-yosys-plugin-91278660dc9776892bde891ea7ad6097c4ea8428.tar.bz2 ghdl-yosys-plugin-91278660dc9776892bde891ea7ad6097c4ea8428.zip | |
Handle isignal like signal.
| -rw-r--r-- | ghdl/ghdl.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index c0cfc40..e3da584 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -66,6 +66,7 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) switch(get_id(inst)) { #define IN(N) get_src(net_map, get_input_net(inst, (N))) case Id_Signal: + case Id_Isignal: case Id_Port: return IN(0); case Id_Uextend: @@ -254,6 +255,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } break; case Id_Signal: + case Id_Isignal: case Id_Output: case Id_Port: case Id_Const_UB32: @@ -387,6 +389,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) break; } case Id_Signal: + case Id_Isignal: { Net sig = get_input_net(inst, 0); if (is_set(net_map, sig)) { |