lib.rs « src « libflashrom-sys « rust « bindings - iCE40/flashrom - [no description]

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path: root/bindings/rust/libflashrom-sys/src/lib.rs

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#![allow(non_upper_case_globals)]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![allow(deref_nullptr)]
include!(concat!(env!("OUT_DIR"), "/bindings.rs"));

>is port ( O1: out std_logic; O2: out std_logic ); end entity child; architecture rtl of child is begin O1 <= '0'; O2 <= '1'; end architecture rtl; library ieee; use ieee.std_logic_1164.ALL; entity top is port ( O: out std_logic ); end entity top; architecture rtl of top is component child is port ( O1: out std_logic; O2: out std_logic ); end component child; begin inst : child port map(O1 => O); end architecture rtl;