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path: root/rayer_spi.c

	Commit message (Expand)	Author	Age	Files	Lines
*	bitbang_spi: Drop bitbang_spi_master_type	Nico Huber	2019-06-23	1	-1/+0
*	Remove trailing whitespace	Elyes HAOUAS	2019-03-04	1	-1/+1
*	Remove address from GPLv2 headers	Elyes HAOUAS	2018-04-24	1	-4/+0
*	rayer_spi: add support for SPI Tiny Tools-compatible hardware	Stefan Tauner	2016-02-28	1	-0/+8
*	Rename programmer registration functions	Carl-Daniel Hailfinger	2014-07-19	1	-1/+1
*	rayer_spi: Fix Xilinx DLC-5 cable	Kyösti Mälkki	2013-10-02	1	-0/+20
*	rayer_spi: Add pinout for Wiggler LPT	Maksim Kuleshov	2013-10-02	1	-0/+8
*	rayer_spi: Add pinout for Atmel STK200/300	Maksim Kuleshov	2013-10-02	1	-0/+28
*	rayer_spi: Add pinout for Altera ByteBlasterMV	Maksim Kuleshov	2013-10-02	1	-0/+26
*	rayer_spi: Improve support for different pinouts	Kyösti Mälkki	2013-10-02	1	-50/+64
*	Some ISO C fixes	Carl-Daniel Hailfinger	2012-08-27	1	-0/+1
*	Automatically release I/O permissions on shutdown	Carl-Daniel Hailfinger	2012-07-21	1	-1/+2
*	Hide hwaccess.h from public API	Patrick Georgi	2012-07-20	1	-0/+1
*	Have all programmer init functions register bus masters/programmers	Carl-Daniel Hailfinger	2011-12-20	1	-2/+2
*	Add a bunch of new/tested stuff and various small changes 8	Paul Menzel	2011-10-21	1	-1/+1
*	Add support for Xilinx parallel III (DLC5) programing cable	Carl-Daniel Hailfinger	2011-09-12	1	-17/+58
*	Kill central list of SPI programmers	Michael Karcher	2011-05-11	1	-3/+0
*	Speed up RayeR SPIPGM driver by a factor of 2	Carl-Daniel Hailfinger	2010-10-05	1	-34/+56
*	Split off programmer.h from flash.h	Carl-Daniel Hailfinger	2010-07-27	1	-0/+1
*	Add support for RayeR SPIPGM hardware as described in http://rayer.ic.cz/elek...	Carl-Daniel Hailfinger	2010-07-21	1	-0/+122

generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 12:30:51 +0000

/*
 * This file is part of the flashrom project.
 *
 * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang@amd.com>
 * Copyright (C) 2008 Joe Bao <Zheng.Bao@amd.com>
 * Copyright (C) 2008 Advanced Micro Devices, Inc.
 * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger
 * Copyright (C) 2013 Stefan Tauner
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#if defined(__i386__) || defined(__x86_64__)

#include <string.h>
#include <stdlib.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#include "spi.h"

/* This struct is unused, but helps visualize the SB600 SPI BAR layout.
 *struct sb600_spi_controller {
 *	unsigned int spi_cntrl0;	/ * 00h * /
 *	unsigned int restrictedcmd1;	/ * 04h * /
 *	unsigned int restrictedcmd2;	/ * 08h * /
 *	unsigned int spi_cntrl1;	/ * 0ch * /
 *	unsigned int spi_cmdvalue0;	/ * 10h * /
 *	unsigned int spi_cmdvalue1;	/ * 14h * /
 *	unsigned int spi_cmdvalue2;	/ * 18h * /
 *	unsigned int spi_fakeid;	/ * 1Ch * /
 *};
 */

static uint8_t *sb600_spibar = NULL;
enum amd_chipset {
	CHIPSET_AMD_UNKNOWN,
	CHIPSET_SB6XX,
	CHIPSET_SB7XX, /* SP5100 too */
	CHIPSET_SB89XX, /* Hudson-1 too */
	CHIPSET_HUDSON234,
	CHIPSET_BOLTON,
	CHIPSET_YANGTZE,
	CHIPSET_PROMONTORY,
};

#define FIFO_SIZE_OLD		8
#define FIFO_SIZE_YANGTZE	71

struct sb600spi_data {
	struct flashctx *flash;
};

static int find_smbus_dev_rev(uint16_t vendor, uint16_t device)
{
	struct pci_dev *smbus_dev = pci_dev_find(vendor, device);
	if (!smbus_dev) {
		msg_pdbg("No SMBus device with ID %04X:%04X found.\n", vendor, device);
		msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
		return -1;
	}
	return pci_read_byte(smbus_dev, PCI_REVISION_ID);
}

/* Determine the chipset's version and identify the respective SMBUS device. */
static enum amd_chipset determine_generation(struct pci_dev *dev)
{
	msg_pdbg2("Trying to determine the generation of the SPI interface... ");
	if (dev->device_id == 0x438d) {
		msg_pdbg("SB6xx detected.\n");
		return CHIPSET_SB6XX;
	} else if (dev->device_id == 0x439d) {
		int rev = find_smbus_dev_rev(0x1002, 0x4385);
		if (rev < 0)
			return CHIPSET_AMD_UNKNOWN;
		if (rev >= 0x39 && rev <= 0x3D) {
			msg_pdbg("SB7xx/SP5100 detected.\n");
			return CHIPSET_SB7XX;
		} else if (rev >= 0x40 && rev <= 0x42) {
			msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n");
			return CHIPSET_SB89XX;
		} else {
			msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n"
				  "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom@flashrom.org\n",
				   rev);
			return CHIPSET_SB89XX;
		}
	} else if (dev->device_id == 0x780e) {
		/* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash)
		 * although they use different SPI interfaces. */
		int rev = find_smbus_dev_rev(0x1022, 0x780B);
		if (rev < 0)
			return CHIPSET_AMD_UNKNOWN;
		if (rev >= 0x11 && rev <= 0x15) {
			msg_pdbg("Hudson-2/3/4 detected.\n");
			return CHIPSET_HUDSON234;
		} else if (rev == 0x16) {
			msg_pdbg("Bolton detected.\n");
			return CHIPSET_BOLTON;
		} else if ((rev >= 0x39 && rev <= 0x3A) || rev == 0x42) {
			msg_pdbg("Yangtze detected.\n");
			return CHIPSET_YANGTZE;
		} else {
			msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
				  "Please report this to flashrom@flashrom.org and include this log and\n"
				  "the output of lspci -nnvx, thanks!.\n", rev);
		}
	} else if (dev->device_id == 0x790e) {
		int rev = find_smbus_dev_rev(0x1022, 0x790B);
		if (rev < 0)
			return CHIPSET_AMD_UNKNOWN;
		if (rev == 0x4a) {
			msg_pdbg("Yangtze detected.\n");
			return CHIPSET_YANGTZE;
		/**
		 * FCH chipsets called 'Promontory' are one's with the
		 * so-called SPI100 ip core that uses memory mapping and
		 * not a ring buffer for transactions. Typically this is
		 * found on both Stoney Ridge and Zen platforms.
		 *
		 * The revisions I have found by searching various lspci
		 * outputs are as follows: 0x4b, 0x59 & 0x61.
		 */
		} else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) {
			msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
			return CHIPSET_PROMONTORY;
		} else {
			msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
				  "Please report this to flashrom@flashrom.org and include this log and\n"
				  "the output of lspci -nnvx, thanks!.\n", rev);
		}


	} else
		msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n"
			  "Please report this to flashrom@flashrom.org and include this log and\n"
			  "the output of lspci -nnvx, thanks!\n",
			  __func__, dev->vendor_id, dev->device_id);

	msg_perr("Could not determine chipset generation.");
	return CHIPSET_AMD_UNKNOWN;
}

static void reset_internal_fifo_pointer(void)
{
	mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);

	/* FIXME: This loop needs a timeout and a clearer message. */
	while (mmio_readb(sb600_spibar + 0xD) & 0x7)
		msg_pspew("reset\n");
}

static int compare_internal_fifo_pointer(uint8_t want)
{
	uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07;
	want %= FIFO_SIZE_OLD;
	if (have != want) {
		msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want);
		msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
			 "Please stop all applications and drivers and IPMI which access the flash chip.\n");
		return 1;
	} else {
		msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want);
		return 0;
	}
}

/* Check the number of bytes to be transmitted and extract opcode. */
static int check_readwritecnt(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt)
{
	unsigned int maxwritecnt = flash->mst->spi.max_data_write + 3;
	if (writecnt > maxwritecnt) {
		msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n",
			  __func__, writecnt, maxwritecnt);
		return SPI_INVALID_LENGTH;
	}

	unsigned int maxreadcnt = flash->mst->spi.max_data_read;
	if (readcnt > maxreadcnt) {
		msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n",
			  __func__, readcnt, maxreadcnt);
		return SPI_INVALID_LENGTH;
	}
	return 0;
}

static void execute_command(void)
{
	msg_pspew("Executing... ");
	mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
	while (mmio_readb(sb600_spibar + 2) & 1)
		;
	msg_pspew("done\n");
}

static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
				  unsigned int readcnt,
				  const unsigned char *writearr,
				  unsigned char *readarr)
{
	/* First byte is cmd which can not be sent through the FIFO. */
	unsigned char cmd = *writearr++;
	writecnt--;
	msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
	mmio_writeb(cmd, sb600_spibar + 0);

	int ret = check_readwritecnt(flash, writecnt, readcnt);
	if (ret != 0)
		return ret;

	/* This is a workaround for a bug in SPI controller. If we only send
	 * an opcode and no additional data/address, the SPI controller will
	 * read one byte too few from the chip. Basically, the last byte of
	 * the chip response is discarded and will not end up in the FIFO.
	 * It is unclear if the CS# line is set high too early as well.
	 */
	unsigned int readoffby1 = (writecnt > 0) ? 0 : 1;
	uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt);
	mmio_writeb(readwrite, sb600_spibar + 1);

	reset_internal_fifo_pointer();
	msg_pspew("Filling FIFO: ");
	unsigned int count;
	for (count = 0; count < writecnt; count++) {
		msg_pspew("[%02x]", writearr[count]);
		mmio_writeb(writearr[count], sb600_spibar + 0xC);
	}
	msg_pspew("\n");
	if (compare_internal_fifo_pointer(writecnt))
		return SPI_PROGRAMMER_ERROR;

	/*
	 * We should send the data in sequence, which means we need to reset
	 * the FIFO pointer to the first byte we want to send.
	 */
	reset_internal_fifo_pointer();
	execute_command();
	if (compare_internal_fifo_pointer(writecnt + readcnt))
		return SPI_PROGRAMMER_ERROR;

	/*
	 * After the command executed, we should find out the index of the
	 * received byte. Here we just reset the FIFO pointer and skip the
	 * writecnt.
	 * It would be possible to increase the FIFO pointer by one instead
	 * of reading and discarding one byte from the FIFO.
	 * The FIFO is implemented on top of an 8 byte ring buffer and the
	 * buffer is never cleared. For every byte that is shifted out after
	 * the opcode, the FIFO already stores the response from the chip.
	 * Usually, the chip will respond with 0x00 or 0xff.
	 */
	reset_internal_fifo_pointer();

	/* Skip the bytes we sent. */
	msg_pspew("Skipping: ");
	for (count = 0; count < writecnt; count++) {
		msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC));
	}
	msg_pspew("\n");
	if (compare_internal_fifo_pointer(writecnt))
		return SPI_PROGRAMMER_ERROR;

	msg_pspew("Reading FIFO: ");
	for (count = 0; count < readcnt; count++) {
		readarr[count] = mmio_readb(sb600_spibar + 0xC);
		msg_pspew("[%02x]", readarr[count]);
	}
	msg_pspew("\n");
	if (compare_internal_fifo_pointer(writecnt+readcnt))
		return SPI_PROGRAMMER_ERROR;

	if (mmio_readb(sb600_spibar + 1) != readwrite) {
		msg_perr("Unexpected change in AMD SPI read/write count!\n");
		msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
			 "Please stop all applications and drivers and IPMI which access the flash chip.\n");
		return SPI_PROGRAMMER_ERROR;
	}

	return 0;
}

static int spi100_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
				  unsigned int readcnt,
				  const unsigned char *writearr,
				  unsigned char *readarr)
{
	/* First byte is cmd which can not be sent through the buffer. */
	unsigned char cmd = *writearr++;
	writecnt--;
	msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
	mmio_writeb(cmd, sb600_spibar + 0);

	int ret = check_readwritecnt(flash, writecnt, readcnt);
	if (ret != 0)
		return ret;

	/* Use the extended TxByteCount and RxByteCount registers. */
	mmio_writeb(writecnt, sb600_spibar + 0x48);
	mmio_writeb(readcnt, sb600_spibar + 0x4b);

	msg_pspew("Filling buffer: ");
	unsigned int count;
	for (count = 0; count < writecnt; count++) {
		msg_pspew("[%02x]", writearr[count]);
		mmio_writeb(writearr[count], sb600_spibar + 0x80 + count);
	}
	msg_pspew("\n");

	execute_command();

	msg_pspew("Reading buffer: ");
	for (count = 0; count < readcnt; count++) {
		readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE);
		msg_pspew("[%02x]", readarr[count]);
	}
	msg_pspew("\n");

	return 0;
}

struct spispeed {
	const char *const name;
	const uint8_t speed;
};

static const char* spispeeds[] = {
	"66 MHz",
	"33 MHz",
	"22 MHz",
	"16.5 MHz",
	"100 MHz",
	"Reserved",
	"Reserved",
	"800 kHz",
};

static const char* spireadmodes[] = {
	"Normal (up to 33 MHz)",
	"Reserved",
	"Dual IO (1-1-2)",
	"Quad IO (1-1-4)",
	"Dual IO (1-2-2)",
	"Quad IO (1-4-4)",
	"Normal (up to 66 MHz)",
	"Fast Read",
};

static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t speed)
{
	bool success = false;

	msg_pdbg("Setting SPI clock to %s (%i)... ", spispeeds[speed], speed);
	if (amd_gen >= CHIPSET_YANGTZE) {
		rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22);
		uint16_t tmp = mmio_readw(sb600_spibar + 0x22);
		success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed &&
			   ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed);
	} else {
		rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd);
		success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3));
	}

	if (!success) {
		msg_perr("FAILED!\n");
		return 1;
	}
	msg_pdbg("succeeded.\n");
	return 0;
}

static int set_mode(struct pci_dev *dev, uint8_t mode)
{
	msg_pdbg("Setting SPI read mode to %s (%i)... ", spireadmodes[mode], mode);
	uint32_t tmp = mmio_readl(sb600_spibar + 0x00);
	tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */
	tmp |= ((mode & 0x6) << 28) | ((mode & 0x1) << 18);
	rmmio_writel(tmp, sb600_spibar + 0x00);
	if (tmp != mmio_readl(sb600_spibar + 0x00)) {
		msg_perr("FAILED!\n");
		return 1;
	}
	msg_pdbg("succeeded.\n");
	return 0;
}

static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
{
	uint32_t tmp;
	int16_t spispeed_idx = -1;
	int16_t spireadmode_idx = -1;
	char *spispeed;
	char *spireadmode;

	spispeed = extract_programmer_param("spispeed");
	if (spispeed != NULL) {
		unsigned int i;
		for (i = 0; i < ARRAY_SIZE(spispeeds); i++) {
			if (strcasecmp(spispeeds[i], spispeed) == 0) {
				spispeed_idx = i;
				break;
			}
		}
		/* "reserved" is not a valid speed.
		 * Error out on speeds not present in the spispeeds array.
		 * Only Yangtze supports the second half of indices.
		 * No 66 MHz before SB8xx. */
		if ((strcasecmp(spispeed, "reserved") == 0) ||
		    (i == ARRAY_SIZE(spispeeds)) ||
		    (amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) ||
		    (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) {
			msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed);
			free(spispeed);
			return 1;
		}
		free(spispeed);
	}

 	spireadmode = extract_programmer_param("spireadmode");
	if (spireadmode != NULL) {
		unsigned int i;
		for (i = 0; i < ARRAY_SIZE(spireadmodes); i++) {
			if (strcasecmp(spireadmodes[i], spireadmode) == 0) {
				spireadmode_idx = i;
				break;
			}
		}
		if ((strcasecmp(spireadmode, "reserved") == 0) ||
		    (i == ARRAY_SIZE(spireadmodes))) {
			msg_perr("Error: Invalid spireadmode value: '%s'.\n", spireadmode);
			free(spireadmode);
			return 1;
		}
		if (amd_gen < CHIPSET_BOLTON) {
			msg_perr("Warning: spireadmode not supported for this chipset.");
		}
		free(spireadmode);