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* cli_classic: include a fallback inplementation of getoptThomas Heijligen2023-04-271-0/+43
| | | | | | | | | | | | Some systems, DJGPP/DOS for now, may not provide getopt and their gnu extensions. So provide a fallback implementation. The code is based on musl libc. Change-Id: I6ebbde075014e3b45b0f9e04b34b72aa969e1197 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73102 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Case write_granularity enum valuesEdward O'Callaghan2023-04-061-10/+10
| | | | | | | | Change-Id: Ic8c655225abe477c1b618dc685b743e691c16ebd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74165 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal: Move laptop_ok into board_cfgEdward O'Callaghan2023-04-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | Due to how internal is structured around chipset_flash_enable() entry we need to prepare a crafted programmer_cfg that contains a board_enable substructure with data derived from the board_enable subsystem. While this is certainly not perfection, it does make clear the relationships between board_enable into chipset_flash_enable and subsequently the overall internal programmer initialisation in a RAII fashion at the type level over closure upon global state that is impossible to reason about. Also flip predicate in report_nonwl_laptop_detected() and return early with the trivial base-case. TEST=`$ sudo ./flashrom -p internal --flash-name`. Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* internal: Move is_laptop into board_cfgEdward O'Callaghan2023-04-021-1/+1
| | | | | | | | Change-Id: I24e38e4457299934acdcd70325d0bf0f4b139e5f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73455 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enables: Allow for prog cfg coupling with board cfgEdward O'Callaghan2023-04-021-5/+8
| | | | | | | | | | | | | | Some boards need to configure the programmer in specific ways. For example, a programmer such as internal may need to be configured either as laptop or not type and as such the board enable needs the ability to feed state back into the programmer configuration. Plumb this though by creating a board_cfg structure that can be packed. Change-Id: I7058a693e714a6966a842ae97cc8da7296e63e5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71623 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dmi.c: Pass is_laptop by ref into dmiEdward O'Callaghan2023-03-281-2/+2
| | | | | | | | | | | Prefix the remaining global cases with `g_` to avoid shadowing issues and for easy greping. Change-Id: I3d5ad6c0623269492d775a99a947fd6fe26c5f91 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* tree/: Rename 'laptop_ok-> g_laptop_ok' to avoid shadowingEdward O'Callaghan2023-03-281-1/+1
| | | | | | | | | | Avoid global symbol shadowing in local functions. Change-Id: Idfca0b7e46d8051bf680227250cf40483e19dc53 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashchips: Add Macronix MX25V1635F supportPoroCYon2023-03-261-0/+1
| | | | | | | | | | | | | | | See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf . I've tested this patch with the MX25V1635F I have here, using serprog and ftdi by (re)writing a few images to the flash and seeing if changes were stored correctly. This also included erasing and rewriting the memory with completely different data, so erase is tested, too. Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V8035F supportPoroCYon2023-03-261-0/+1
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V4035F supportPoroCYon2023-03-261-0/+1
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert printlock func ptr into enumerate valuesEdward O'Callaghan2023-03-222-68/+48
| | | | | | | | | | | | | | | | | | | Converting the printlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: I9131348f72c1010e2c213dca4dc4b675a8d8681e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* Revert "pcidev: remove pcidev_getdevfn() function"Thomas Heijligen2023-03-201-0/+1
| | | | | | | | | | | | | | | As Edward pointed out correctly this function does more than abstracting the different versions of `pci_get_dev()`. It also hide the usage of the global `struct pci_access pacc` from the caller. This reverts commit 0e8902f1ff2b927bb91a5e89e4fde3d8d71f6692. Change-Id: I0cd2f54cb6a6e35dc353476e0f5e502cbbd06cba Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert unlock func ptr into enumerate valuesEdward O'Callaghan2023-03-202-47/+33
| | | | | | | | | | | | | | | | | | | Converting the blockprotect unlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: Ie5c5db1b09d07e1a549990d6f5a622fae4c83233 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* pcidev: remove pcidev_getdevfn() functionThomas Heijligen2023-03-101-1/+0
| | | | | | | | | | | This function is only called once. Move the content of the function into the caller. Change-Id: Id2983420080f75ae6992edfb032bf5c83b29c803 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* libpci: drop support for pciutils < 2.2.0Thomas Heijligen2023-03-101-12/+14
| | | | | | | | | | | | | | This version was released in september 2005 and had a breaking api change. Drop it so that we don't need to maintain the old codepath any longer. Beside that, we have already a second codepath which is using the new `pci_get_dev` variant exclusively. Change-Id: If943db350b561a005d8292a53d9255223db3d571 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/pci.h: Use __has_include() macro to test pci.h pathThomas Heijligen2023-03-101-3/+7
| | | | | | | | | | | | | | | Some NetBSDs have the pci.h under pciutils/ instead of pci/. But we can't say for sure which variants uses which include path. Just test them with the __has_include() compiler macro. https://gcc.gnu.org/onlinedocs/cpp/_005f_005fhas_005finclude.html Change-Id: Ib20de6bffede910b89937f554b4d56f4799f0762 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73292 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree/: Drop default_spi_probe_opcode for NULL caseEdward O'Callaghan2023-03-032-2/+2
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate as it implies default behaviour of a supported opcode within the `check_block_eraser()` match supported loop. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi: Make default cmd helpers static internalEdward O'Callaghan2023-03-031-3/+0
| | | | | | | | | | | | | | | | | | | | Avoid these leaking into driver implementations as a NULL field now implies their implementation. This removes one source of a driver bug where both `mst->command` AND `mst->multicommand` are set to default implementations which is actually a cyclical control flow condition. The driver however must still have either `mst->command` OR `mst->multicommand` defined and so both cannot be NULL. This simplifies the code and driver development. Change-Id: I4ef95846c2f005cf4aa727f31548c6877d2d4801 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect: Add function to get register values and WP bit masksNikolai Artemiev2023-03-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | Add a new wp_cfg_to_reg_values() function that takes a generic wp_cfg instance and returns the chip-specific values that need to be written to the chip's registers to enable the specified protection range/mode. The function returns three values for each chip register: - reg_values[reg] - Value writeprotect will write to reg - bit_masks[reg] - Bit mask for WP-related bits in reg - write_masks[reg] - Bit mask for writable WP-related bits in reg (i.e. the ones writeprotect will try to write) BUG=b:260019525,b:259013033,260020006 BRANCH=none TEST=ninja test Change-Id: Ib2a47153b230c9f82bb4eca357c335f2abbacc20 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69847 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* ch347_spi: Add initial support for the WCH CH347Nicholas Chin2023-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* asm106x: add programmer for ASM106x SATA controllersAlex Badea2023-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* serial: Call set_custom_baudrate() thricePeter Stuge2023-02-161-1/+7
| | | | | | | | | | | | | | | | | | | | | | | Call the function before tcsetattr() settings are known, then again with settings prepared but not yet applied and finally a third time after tcsetattr(). Darwin support needs this change; there custom_baud code must be called to modify the settings passed to tcsetattr() and then again after tcsetattr() returns. The change should be non-functional on all currently supported systems; current code calls set_custom_baudrate() before any tcsetattr() settings are prepared, so we have three stages in total. This change originates from discussion of the macOS patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I40cc443cfb7bf6b212b31826d437b898cc13c427 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* internal: Move parallel logic into internal_par implementationEdward O'Callaghan2023-02-151-1/+2
| | | | | | | | | | | | | The parallel internal programmer is its own implementation. Move it and call into it from the top-level internal.c programmer implementation. Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c: Add functions for new erase selection algorithmAarya Chaumal2023-02-131-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add function to flatten out the addresses of the flash chip as per the different erase functions. This function will return a list of layouts which is dynamically allocated. So after use all the layouts as well as the list itself should be freed. The free_erase_layout function does that. 2) Add function to align start and end address of the region (in struct walk_info) to some erase sector boundaries and modify the region start and end addresses to match nearest erase sector boundaries. This function will be used in the new algorithm for erase function selection. 3) Add function that returns a list of sectors (as seen by the first erase function) that need erasing. 4) Add a function to call the erase algorithm. Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmers: Allow opaque programmers to specify custom delayEdward O'Callaghan2023-02-011-0/+1
| | | | | | | | | | | | | | | The dummyprogrammer in the opaque case can have a NOP delay to avoid wasting CPU time and energy. BUG=b:266014935 TEST=builds Change-Id: Ia86ad21f011214abc2aa0891a43559f91e2a9591 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72424 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Change chip restore data type from uint8_t to void ptrNikolai Artemiev2023-01-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip restore callbacks currently are used by - spi25_statusreg.c unlock functions to restore status register 1. - s25f.c to restore config register 3. Both of these cases only need to save a single uint8_t value to restore the original chip state, however storing a void pointer will allow more flexible chip restore behaviour. In particular, it will allow flashrom_wp_cfg objects to be saved and restored, enabling writeprotect-based unlocking. BUG=b:237485865,b:247421511 BRANCH=none TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W): `flashrom --wp-range 0x0,0x1000000 \ flashrom --wp-status # Result: range=0x0,0x1000000 \ flashrom -w random.bin # Result: success \ flashrom -v random.bin # Result: success \ flashrom --wp-status # Result: range=0x0,0x1000000` Change-Id: I311b468a4b0349f4da9584c12b36af6ec2394527 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flash.h: Make functions global that will be used for new erase algorithmAarya Chaumal2023-01-162-0/+9
| | | | | | | | | | | | The new erase algorithm uses some of the functions which are static to `flashrom.c`. So make these functions global and add prototypes to `include\flash.h` and `include\layout.h'. Change-Id: I7ee7e208948337b88467935fd2861b5f9ad6af9d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* internal,board_enable: Remove force_boardenable from globalsEdward O'Callaghan2023-01-151-4/+3
| | | | | | | | | | | | Make `force_boardenable` stack local to the internal_init() entry-point. It's life-time should not exceed that of the internal's init entry function. Change-Id: I3324681f024003694a5531d9d35bb13d2c583eb0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70031 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer.h: Guard against sending spi commands on non-spi mstEdward O'Callaghan2023-01-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Validate (flash->chip->bustype == BUS_SPI) as ich copies the chip flags in the opaque master and tries incorrectly to issue 4BA commands which results in failure. The issue was detected only in the case of chips >16MB, in this case 'W25Q256FV' that has the feature bits: ``` .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, ``` The regression was noticed from, commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip` TEST=In the case of 'W25Q256FV' on TigerLake. Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Sam McNally <sammc@google.com>
* parallel: Drop explicit fallback_chip_X boilerplateEdward O'Callaghan2023-01-111-6/+0
| | | | | | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => fallback_chip_X' as to not need this explicit specification. Therefore drop the explicit need to specify these fallback callback function pointer in the par_master struct. This is a reasonable default for every driver in the tree. Furthermore, move the 'fallback_chip_X()' func from the generic programmer.c register logic into its relevant home of parallel.c and make static local to clean up link-time symbol space. This simplifies the code and driver development. Change-Id: If25c0048a07057aa72be6ffa8d8ad7f0a568dcf7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71745 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom: Add flags to skip unreadable and unwritable regionsNikolai Artemiev2022-12-182-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add flags to allow libflashrom users to configure how operations that include unreadable or unwritable regions should be behave. If the flags are set to true, a read/write operation will just skip the inaccessible region and will still be executed in other regions. If the flags are set to false, the inaccessible region will cause the entire operation to fail. BUG=b:260440773 BRANCH=none TEST=builds Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer: Add get_region to spi/opaque mastersNikolai Artemiev2022-12-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a get_region function to spi and opaque masters so that they can expose access permissions for multiple regions within the flash. A get_region() implementation is added for the ichspi driver in a following patch. Finally, another patch uses get_region() to make read_flash() and write_flash() skip inaccessable regions, making read, write, and erase operations work on Intel platforms with active an CSME coprocessor. This logic will be integrated with layout in the future, but for now this moves ichspi support forward without making refactoring too hard later on. BUG=b:260440773 BRANCH=none TEST=ninja test Change-Id: I8c43f6b705f36ef18842a04ba6241d3a0b36b232 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout.h: Add {read,write}_prot flags to flash_regionNikolai Artemiev2022-12-151-0/+2
| | | | | | | | | | | | | | | | | Add protection bits to `struct flash_region` to keep track of the CSME restrictions for each flash region. BUG=b:260440773 BRANCH=none TEST=builds Change-Id: I0e5b3b4369dc868a8a64338935c5c5249b9a4ada CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70437 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Factor out flash_region structure from romentryNikolai Artemiev2022-12-151-3/+8
| | | | | | | | | | | | | | | | | | | | | | | The romentry structure is the container ADT with some annotated meta-data such as 'included' or 'file' however the substantive substructure is a 'flash_region'. Therefore factor this out. That is to say, the link list node 'romentry' is obscured by the implementation details of its use-case of 'flash_region' that we clear up here. BUG=b:260440773 BRANCH=none TEST=flashrom_tester Change-Id: I768742b73db901df5b5208fcbcb8a324a06014c2 CoAuthored-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69196 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi.c: Add AT45 & SF25F erasefn opcode mappingThomas Heijligen2022-12-141-1/+1
| | | | | | | | | Change-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67717 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcodeThomas Heijligen2022-12-141-1/+1
| | | | | | | | | | | This function works only with spi25 chips Change-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Rename 'internal_delay()' to 'default_delay()'Edward O'Callaghan2022-12-122-2/+2
| | | | | | | | | | | | | | | The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Move programmer_delay() out of programmer state machineEdward O'Callaghan2022-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | Handle the special cases of both serprog and ch341a_spi. Also rewrite programmer_delay() to handle the two base cases of zero time and no valid flashctx yet before handling per master branching. Additionally, modify the custom delay function pointer signature to allow closure over the flashctx. This allows driver specific delay implementations to recover programmer specific opaque data within their delay implementations. Therefore programmer specific delay functions can avoid programmer specific globals. Change-Id: Id059abb58b31a066a408009073912da2b224d40c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add selfcheck to unit testsEvan Benn2022-12-051-0/+1
| | | | | | | | | | | | | | | | | Add unit tests for programmer_table, flashchips, and board_matches structs. The tests are derived from the selfcheck function, checking that the required fields have been filled in. BUG=b:140595239 BRANCH=None TEST=meson test Change-Id: I41cd014d9bf909296b6c28e3e00548e6883ff41a Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69620 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Make probe_opcode() flashctx argument constNikolai Artemiev2022-12-041-2/+2
| | | | | | | | | | | | | | | | | | | Probing an opcode generally shouldn't involve mutating the flashctx state and currently no probe_opcode functions do that. Make the flashctx arg const so that call sites don't need to have a non-const pointer. BUG=b:253715389,b:253713774 BRANCH=none TEST=ninja test Change-Id: I19e98be50d682de2d2715417f8b7b8c62b871617 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchips db to use indirection for printlockNikolai Artemiev2022-11-231-0/+44
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip printlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: Icff868d9454e9b0a059a736457bb562430436033 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchips db to use indirection for unlockEdward O'Callaghan2022-11-231-0/+26
| | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip unlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I3ed51142cd22becc8286959f5504565158fa2de0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* writeprotect_ranges.c: add more range functionsSergii Dmytruk2022-11-192-1/+7
| | | | | | | | | | | | Not all chips follow the same pattern. There are differences in how CMP bit is treated or in block size used. Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg: support reading/writing configuration registerSergii Dmytruk2022-11-192-0/+9
| | | | | | | | | | | | | | One more variation of registers. This one is read via a separate RDCR command, but written as if it's SR2 using WRSR_EXT2. Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg.c: support reading security registerSergii Dmytruk2022-11-192-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not to be confused with "secure registers" of OTP. Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing special write commands with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL commands). No WREN is necessary, but at least some datasheets indicate BUSY state after those write commands. Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode. The register is found in at least these chips by Macronix: * MX25L6436E * MX25L6445E * MX25L6465E * MX25L6473E Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* writeprotect.c: refuse to work with chip if OTP WPS == 1Sergii Dmytruk2022-11-181-1/+2
| | | | | | | | | | | | | Perform the check right in read_wp_bits() as it's used by various WP operations and also because its results won't make sense if WPS bit is on and can't be changed. Change-Id: I143186066a1d3af89809b7135886cb8b0d038085 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tests: ensure chip erase operation is executedNikolai Artemiev2022-11-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The `full_chip_erase_with_wp_dummyflasher_test_success` test case checks that erasing a write-protected region of a dummyflasher chip fails. However erase optimization may cause the erase operation to be skipped if the flash contents are already erased, so the erase operation appears to succeed and the test case fails. Writing a non-erased value to the chip ensures that an erase operation will be executed and write protection will be properly tested. BUG=b:237620197 BRANCH=none TEST=ninja test Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer: Drop dead fallback_map() boilerplateEdward O'Callaghan2022-11-121-2/+0
| | | | | | | | | | | | | | The fallback_{un}map() boilerplate code doesn't do anything, merely distracts away from otherwise linear control flow. Just drop it as anything in the future that could need such a thing is free to implement it when required. Change-Id: Ibb7760f807fae040416cef2797a7dbf6572f7df9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68963 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip erase_block func ptr to enumerateEdward O'Callaghan2022-11-112-38/+41
| | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. Change-Id: I02ae7e4c67c5bf34ec2fd7ffe4af8a2aba6fd5e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69133 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchips db to use indirection for erase_blockEdward O'Callaghan2022-11-111-0/+36
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip erase_block func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-18 22:04:50 +0000