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* chipset_enable.c: Add Gemini Lake eSPI PCI device IDAngel Pons2021-05-181-0/+1
* Add Gemini Lake supportAngel Pons2021-05-161-0/+9
* chipset_enable.c: Add IDs for H310C and B365 PCHsAngel Pons2021-04-271-0/+2
* chipset_enable.c: Add CMP-H IDsGaggery Tsai2021-04-261-0/+7
* chipset_enable: Mark QS67 as DEPEvgeny Zinoviev2021-04-241-1/+1
* chipset_enable.c: Add PCI ID for Comet Lake U BaseSam McNally2021-03-111-0/+1
* chipset_enable: Mark Intel C216 as DEPJacob Garber2021-02-281-1/+1
* chipset_enable.c: Mark Intel H110 as DEPAngel Pons2020-12-181-1/+1
* chipset_enable.c: mark "Broadwell U Base" as DEPNikolai Artemiev2020-12-141-1/+1
* chipset_enable.c: Validate physmap() return rcrb valueEdward O'Callaghan2020-12-021-0/+2
* chipset_enable.c: Mark Intel Q67 as DEPAngel Pons2020-11-231-1/+1
* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2020-10-271-0/+2
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+9
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
* chipset_enable.c: Add support for Intel C620 Series Chipset SPI ControllerLuka Kovacic2020-08-251-0/+1
* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
* chipset_enable.c: Disable SPI on ICH7 if booted from LPCAngel Pons2020-04-171-0/+8
* chipset_enable.c: Add more Lewisburg PCH IDsAngel Pons2020-03-271-0/+8
* chipset_enable: Mark Intel HM75 as DEPEvgeny Zinoviev2020-03-191-1/+1
* chipset_enable.c: Mark Skylake U Premium as DEPAngel Pons2020-03-191-1/+1
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
* chipset_enable.c: Mark Intel Q75 as DEPAngel Pons2019-10-081-1/+1
* chipset_enable: Mark Intel CM236 and CM246 as DEPNico Huber2019-08-081-2/+2
* chipset_enable: Add support for Cannon Lake U PremiumMatt DeVillier2019-08-081-0/+1
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-10/+10
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-081-0/+18
* chipset_enable: Fix recent -Wmissing-field-initializer troubleNico Huber2019-07-311-14/+14
* ichspi: Add Apollo Lake supportNico Huber2019-07-061-1/+1
* chipset_enable: Add Apollo LakeNico Huber2019-07-061-4/+20
* Rework internal bus handling and laptop bail-outNico Huber2019-06-061-377/+440
* chipset_enable: Mark Intel QS77 as DEPEvgeny Zinoviev2019-06-031-1/+1
* Remove trailing whitespaceElyes HAOUAS2019-03-041-1/+1
* chipset_enable.c: Mark Intel C224 as DEPTristan Corrick2018-12-221-1/+1
* chipset_enable.c: Mark Intel PM55 as DEPAngel Pons2018-11-031-1/+1
* chipset_enable.c: Mark Intel H81 as DEPTristan Corrick2018-11-011-1/+1
* chipset_enable.c: Mark Intel HM65 as DEPAngel Pons2018-10-081-1/+1
* Remove unneeded whitespaceElyes HAOUAS2018-10-051-1/+1
* chipset_enable.c: Mark Broadwell U Premium as DEPAngel Pons2018-10-031-1/+1
* chipset_enable.c: Mark Intel HM55 as DEPAngel Pons2018-08-221-1/+1
* Remove unneeded white spacesElyes HAOUAS2018-06-241-2/+2
* chipset_enable: Add PCI IDs for discrete Kaby Lake PCHsNico Huber2018-06-041-0/+7
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
* Fix whitespace errorsElyes HAOUAS2018-04-241-1/+1
* chipset_enable: Mark VX855 as testedLubomir Rintel2018-01-261-1/+1
* chipset_enable: Mark VX900 as testedLubomir Rintel2018-01-021-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 19:19:18 +0000