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* atahpt: Refactor singleton states into reentrant patternAlexander Goncharov2022-06-191-6/+27
| | | | | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". Implements: https://ticket.coreboot.org/issues/391 BUG=b:185191942 TEST=builds Change-Id: I82e4c82916dc835e9462b80750b06f9d78701edf Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* atavia: fix BYTE_OFFSET's macro argument valueAlexander Goncharov2022-06-181-1/+1
| | | | | | | | | | | A macro value has to use a correct argument name. Change-Id: I666204ec92c6df625b34ca721b3e1af78772bccf Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher: Wire variable size feature via opaque infraAnastasia Klimchuk2022-06-163-70/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire "variable size" feature in dummy programmer via opaque infra. This patch fixes the broken build with CONFIG_DUMMY=no. Dummyflasher registers opaque master for the case when it is initialised with EMULATE_VARIABLE_SIZE. Dummy opaque master emulates read/write/erase as simple memory operations over `data->flashchip_contents`. The feature works via "Opaque flash chip" in flashchips.c which has one block eraser at the moment. If this changes in future, each block eraser needs to be updated in `probe_variable_size`. Fixes: https://ticket.coreboot.org/issues/365 TEST=the following scenarious run successfully Testing build $ make clean && make CONFIG_DUMMY=no $ flashrom -h : dummy is not in the list $ make clean && make CONFIG_EVERYTHING=yes $ flashrom -h : dummy is in the list Testing "variable size" feature $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V $ head -c 8388608 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V also same as above with erase_to_zero=yes Testing standard flow $ flashrom -p dummy:emulate=W25Q128FV -V $ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V $ head -c 16777216 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V Testing invalid combination of programmer params (`init_data` fails and prints error message which is WAI) $ flashrom -p dummy:size=8388608 -V -> init_data: size parameter is only valid for VARIABLE_SIZE chip. $ flashrom -p dummy:emulate=VARIABLE_SIZE -V -> init_data: the size parameter is not given. $ flashrom -p dummy:emulate=W25Q128FV,erase_to_zero=yes -V -> init_data: erase_to_zero parameter is not valid for real chip. Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom.map: Add missing functions from libflashrom.hEvan Benn2022-06-151-1/+18
| | | | | | | | | | | | Some functions were not being defined, namely flashrom_wp_*. Thus, add all missing functions from libflashrom.h header file. Change-Id: Ic90b3c20780d3a07b00bfca82d23d44c4fa6f22f Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tree: Consolidate BIT() macroEdward O'Callaghan2022-06-103-3/+2
| | | | | | | | | Change-Id: I7e61f7671b70ca5ed751d99405714436bcd18d5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Add W25Q512NW-IM ID to flashromAtul Dhudase2022-06-072-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25Q512NW-IM chip ID and specs to flashrom. BUG=b:200173901 BRANCH=none TEST=flash W25Q512NW-IM using CCD. Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890 Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shelley Chen <shchen@chromium.org> Original-Commit-Queue: Shelley Chen <shchen@chromium.org> (cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61) Note: this commit was cherry-picked from the cros tree but includes corrections to errors in the original commit's 4BA feature flags that were spotted by Angel Pons Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* test_build.sh: Allow WARNERROR to be overriddenMartin Roth2022-05-311-1/+1
| | | | | | | | | | | | | | | | Currently, WARNERROR is hardcoded to 'yes' which is what we want most of the time, but there are cases (such as when building with -fanalyzer) that we don't want it enabled, so we see the entire output of the build, and it doesn't halt at the first error. Removing the WARNERROR line from the script allows the variable to be overridden from an environment variable. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iea931e57f2a6992762566dc3dbaae8bb8df5b226 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62745 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: use files() for srcs listThomas Heijligen2022-05-311-61/+64
| | | | | | | | | | | | | | | Meson looks up if the file xyz.c exists when calling file('xyz.c'). Furthermore it keeps track of the directory of the file. This is handy when using multiple directories. Change-Id: I346b5468b4203f1521ec73a90f93ff3b13ebf43c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Fix W25Q256.WPatrick Rudolph2022-05-261-3/+8
| | | | | | | | | | | | | | | | | The JW is the only known variant. A W25Q256FW may have existed with less 4BA instructions supported, but it never showed up and no data- sheet is available. Used the datasheet from here: https://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/362 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* flashchips.c: add CMP bit entry to W25Q256.VNikolai Artemiev2022-05-261-0/+1
| | | | | | | | | | | | | | | Add bit that was missed in `commit a850fd0a` BUG=b:182223106 BRANCH=none TEST=builds Change-Id: I1cb400f6b8542a9054875b8f2557db1cc06292e2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64607 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom: Return progress state to the library userRichard Hughes2022-05-2522-3/+184
| | | | | | | | | | | | | | | | | | | | | | Projects using libflashrom like fwupd expect the user to wait for the operation to complete. To avoid the user thinking the process has "hung" or "got stuck" report back the progress complete of the erase, write and read operations. Add a new --progress flag to the CLI to report progress of operations. Include a test for the dummy spi25 device. TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c Signed-off-by: Richard Hughes <richard@hughsie.com> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom: initialize restore func count in correct placeNikolai Artemiev2022-05-231-1/+3
| | | | | | | | | | | | | | | | | | | | | Set `flash->chip_restore_fn_count` to zero before calling the chip's unlock funciton in `prepare_flash_access()`. Previously `flash->chip_restore_fn_count` was uninitialized before calling `chip->unlock()` and subsequently reset after the dispatch by initializing it. This caused the restore handler that is registered within `spi_disable_blockprotect_generic()` to be lost. BUG=b:228945411 BRANCH=none TEST=enable wp; flashrom -w; check wp still enabled. Change-Id: I4c7df424bd2ae2b5fb2a2ab6b47a3c9ff3233acf Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi: Add Intel Alder Lake-S supportMichał Kopeć2022-05-192-2/+15
| | | | | | | | | | | | Add ADL PCH-S device IDs to enable flashrom on Alder Lake-S platforms. TEST=Dump BIOS on MSI Z690 PRO DDR4 WIFI Change-Id: Ib2a8c057994874a41ed400b176f156048dae43c0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* util/shell.nix: Add libjaylinkFelix Singer2022-05-191-1/+1
| | | | | | | | | | | | libjaylink is packaged since NixOS 21.11 and it is out for many months now. Thus, include the package libjaylink and remove comments. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I56e750831143a4e34be95ec111a37bb476abfe85 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64352 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cli_classic: fix memory leakAlexander Goncharov2022-05-171-0/+1
| | | | | | | | | | | | | | If parameter --wp-region is used and wp_region is allocated, free the last one at the exit of the application. Found-by: scan-build, clang v13.0.1 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Change-Id: I8520e302e9d63ed1215c5d9beb90a93fb52a91fe Reviewed-on: https://review.coreboot.org/c/flashrom/+/64351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* include/flash.h: Drop dead struct membersEdward O'Callaghan2022-05-171-2/+0
| | | | | | | | | | | | | These were part of the original wp implementation, now dead code left over. Change-Id: I43b25175c6ff833b822a93c4e752a28cf97d64b8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.c: Make need_erase() helper static localEdward O'Callaghan2022-05-172-2/+1
| | | | | | | | | | | | The need_erase() helper is only used within flashrom.c Change-Id: Ic0946bb109fca2fc18e15eefa11cccea284ded0b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom: Drop read_flash_to_file() usageEdward O'Callaghan2022-05-134-44/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspire towards a goal of making cli_classic more of just a user of libflashrom than having quasi-parallel paths in flashrom.c This converts remaining read_flash_to_file() usage to the do_read() provider wrapper around libflashrom. BUG=b:208132085 TEST=` sudo ./flashrom -p ft2232_spi:type=232H,divisor=1000 -f -r out -c W25X05 Flashrom output: No EEPROM/flash device found. Force read (-f -r -c) requested, pretending the chip is there: Assuming Winbond flash chip "W25X05" (64 kB, SPI) on ft2232_spi. Please note that forced reads most likely contain garbage. Block protection could not be disabled! Reading flash... done. Data read: xxd out-1khz 00000000: 0000 07ff ffff e000 0000 7fff fffe 0000 ................ 00000010: 0007 ffff ffe0 0000 007f ffff fe00 0000 ................ 00000020: 07ff ffff e000 0000 7fff fffe 0000 0007 ................ 00000030: ffff ffe0 0000 007f ffff fe00 0000 0fff ................ xxd out-100khz 00000000: b6db 6db6 db6d b6db 6db6 db6d b6db 6db6 ..m..m..m..m..m. 00000010: db6d b6db 6db6 db6d b6db 6db6 db6d b6db .m..m..m..m..m.. 00000020: 6db6 db6d b6db 6db6 db24 9249 2492 4924 m..m..m..$.I$.I$ 00000030: 9249 2492 4924 9249 2492 4924 9249 2492 .I$.I$.I$.I$.I$. ` Change-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Rearange CPP guardsThomas Heijligen2022-05-122-33/+41
| | | | | | | | | | | | | | | This fixes -Werror=unused-function when not all programmer tests are build. `run_basic_lifecycle` and `run_probe_lifecycle` need to have a prototype to not throw a -Werror=unused-function if no programmer needs them. Change-Id: I02880e73996b30df618738e86b8a52126fbe5b3b Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* meson: link flashrom binary against static libflashromThomas Heijligen2022-05-121-20/+7
| | | | | | | | | | | | | TEST: meson build && ninja -C build Read chip successfully with ch341a_spi programmer Change-Id: Ic522610f59e00299ebfa1bd29482ff92120ec52b Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64030 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: relocate config_print_wiki & config_default_programmer_*Thomas Heijligen2022-05-121-13/+13
| | | | | | | | | | | | Change-Id: I9538b0aee31b294844d4f4ca0396334a81dfb498 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* meson: use built-in options for install pathsThomas Heijligen2022-05-121-7/+2
| | | | | | | | | | | | The install functions of meson can take a relative path and join the prefix automatically. Change-Id: I9cb9faf4bdbcfd66098478cc3a260eb3b664a2e6 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* meson: add option to disable testsThomas Heijligen2022-05-122-24/+30
| | | | | | | | | | | | | | | During development it can be useful to disable unit testing. By default tests are built if cmocka is found. To force enable tests run `meson build -Dtests=enable`. To disable tests run `meson build -Dtests=disabled`. Change-Id: I384c904c577b265dfe36bf46bf07c641bc29de9b Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* meson: use `platform/` as subdir()Thomas Heijligen2022-05-122-11/+13
| | | | | | | | | | | | | | | | Move build instructions for files inside the `platform/` directory to `platform/meson.build`. This contains instructions to build `memaccess.c`, the right endian implementation and selecting the right legacy command line option for the endian. The `platform/` directory should contain code that abstracts the underlying platform but is not involved in flashrom logic. Change-Id: I88044a3f903f316138483dd872a6d95f8686ae69 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* util/ich_descriptors_tool: Remove unneeded meson dependenciesThomas Heijligen2022-05-121-3/+0
| | | | | | | | | Change-Id: Ice1437cb294729b6af0e24f0a02692459b7a1412 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* meson: relocate add_project_arguments() for IS_WINDOWSThomas Heijligen2022-05-121-6/+5
| | | | | | | | | | | Change-Id: I6afb65fabf858449f2706bf250588225a94c1871 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* meson: relocate source file listThomas Heijligen2022-05-121-34/+34
| | | | | | | | | | | | Change-Id: I921be8a8a99b93d23c1dbd4ea54672ba9998558d Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* util/flashrom_tester: Update sys-info crate to version 0.9Angel Pons2022-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | An issue was discovered in the sys-info crate before 0.8.0 for Rust. sys_info::disk_info calls can trigger a double free. To prevent any potential problems, update this crate to version 0.9 (as of writing, sys-info version 0.9.1 is the latest). Refer to CVE-2020-36434 for more details about the sys-info crate bug. TEST=Run `cargo build` in `util/flashrom_tester`, it still works fine. Change-Id: I3b6b21e830ff3107860f7bcbfe2d58b29efe0c12 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63975 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: test write protectionSergii Dmytruk2022-05-124-0/+344
| | | | | | | | | | | | Tests both WP implementation and its emulation in dummy programmer. Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* dummyflasher: enforce write protection for W25Q128FVSergii Dmytruk2022-05-122-18/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start taking bits related to write protection into account. Also add "hwwp" parameter for dummy programmer that sets state of WP pin (not inverted value). TEST=use command-line interface to run WP-related commands dummyflasher doesn't store state of the chip between runs and flashrom allows running only one command, so testing WP in this way is limited. However, WP options can be combined with other operations and are executed prior to them, so certain scenarios can be checked. List possible ranges: flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list Set a particular range and check status is correct: flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-enable \ --wp-range=0x00100000,0x00f00000 \ --wp-status Enable write protection and try erasing/writing (erasing here): # this fails flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-range=0,0x00c00000 \ --wp-enable \ --erase Write protecting empty range has no effect: # this succeeds flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-range=0,0 \ --wp-enable \ --erase Disabling WP is possible if hwwp is off: # this fails flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=yes \ --wp-disable # this succeeds flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=no \ --wp-disable Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* dummyflasher: emulate SR2 and SR3 for W25Q128FVSergii Dmytruk2022-05-121-7/+25
| | | | | | | | | | | | | | | | | | | | | | Enable emulation of SR2 and SR3 for W25Q128FV and provide logic for updating them (masks of read-only bits that can't be set from outside). TEST=check how input value affects status registers of emulated chip flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 | grep -A3 'Initial status registers' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 | grep -A3 'Initial status registers' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 | grep -A3 'Initial status registers' Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* it85spi.c: Fix some space/tab trivial style issuesEdward O'Callaghan2022-05-121-26/+27
| | | | | | | | | Change-Id: I9192461281f9e760644a241148f4c5100f76da98 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64246 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher: add SR2 and SR3 emulation harnessSergii Dmytruk2022-05-122-15/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare everything for emulating SR2 and SR3 for chips that have it. This is needed for accessing SRP1 and WPS bits which are involved in write protection. The emulated register doesn't affect anything yet and will be tested by write-protection tests. TEST=check how input value affects status registers of emulated chip flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 | grep 'Initial status register' Mind that at this point there are no chips that emulate more than one status register. Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* serprog.c: Avoid calling memcpy with NULL pointer argumentsaarya2022-05-121-1/+2
| | | | | | | | | | | | | | | | In function sp_stream_buffer_op, the variable parms might be NULL when passed to memcpy. Although, since parmlen is also 0 at that time I don't think it would make much difference. Still, add a NULL check before calling memcpy to be safe. Change-Id: I850123237e328f9548ba7f77a01888be2cbc9e7b Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* platform/swap: move swap inline functions & macros into an own headerThomas Heijligen2022-05-084-53/+82
| | | | | | | | | | | | | These inline functions and macros are only used in platform/endian_(big|little).c and do not need to be compiled into every object which includes `platform.h`. Change-Id: Ib2326e6a4eb5e000a0eace857d040372e2e9e561 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libflashrom: Move documentation to headerEvan Benn2022-05-066-471/+438
| | | | | | | | | | | | | | | | | | | | | The doxygen documentation was in the libflashrom.c file. Move the documentation to the libflashrom.h file. This allows foreign function interface binding generators (eg rust bindgen) that operate on the .h file to generate documentation for the target language. Some doxygen errors were also corrected, mostly undocumented or wrongly labeled parameters. To test, I have diffed and inspected the doxygen documentation before and after the change. All functions are documented the same, and the structs and enums are now also included in the docs. Change-Id: I856b74d5bfea13722539be15496755a95e701eea Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.8.tmpl: Add raiden_debug_spi doc entryEdward O'Callaghan2022-05-051-0/+49
| | | | | | | | | | | | BUG=b:224358254 TEST=`man ./flashrom.8.tmpl`. Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* board_enable.c: Port to use pcidev_find_vendorclass() helperEdward O'Callaghan2022-05-041-15/+9
| | | | | | | | Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-0315-26/+26
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macrosSubrata Banik2022-05-031-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces useful macros (read/write/erase) and uses these macros throughout the SPI operations. Additionally, implicitly using the HSFC_CYCLE_READ macro for the SPI read operation. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Additionally, no difference in flashrom binary seen while comparing flashrom binary generated with CB:62888 and between CB:62888 to CB:62868 below: flashrom$ cmp flashrom flashrom_old <<none>> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62868 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC_FDBC_VAL(n) macroSubrata Banik2022-05-031-2/+3
| | | | | | | | | | | | | | | This patch introduces HSFC_FDBC_VAL(n) macro to use in SPI read and write operations. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Introduce HSFC_FCYCLE_MASK(n) macroSubrata Banik2022-05-031-2/+21
| | | | | | | | | | | | | | | This patch introduces HSFC_FCYCLE_MASK(n) macro to cover both ICH and PCH hardware sequencing FCYCLE Bit width. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Reviewed-on: https://review.coreboot.org/c/flashrom/+/62891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Drop unused `_pprint_reg` macroSubrata Banik2022-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch drops `_pprint_reg` macro as `pprint_reg` macro is now able to call into msg_pdbg(). BUG=b:223630977 TEST=Able to display HSFS register offset properly as below BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000) 0x04: 0xf000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offsetSubrata Banik2022-05-031-1/+1
| | | | | | | | | | | | | | | | This patch uses `pprint_reg` macro instead `_pprint_reg` with explicit register name and offset macros being passed as argument. BUG=b:223630977 TEST=Able to display PCH100_HSFC.FCYCLE offset properly. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macrosSubrata Banik2022-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* pony_spi.c: Extract out get_params to simplify initEdward O'Callaghan2022-05-011-42/+54
| | | | | | | | | | | | | | | In light of `commit caa0335114a81`, extract out the get_param logic to its own function to simplify the number of cleanup paths. BUG=none TEST=builds Change-Id: I364febc05c870683cbad114583762b0c006f4bac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63130 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: enable write-protection for W25Q{64,128}.VSergii Dmytruk2022-05-011-4/+76
| | | | | | | | | | | | | | | | | | | | | Configuration for W25Q64 was tested on hardware (W25Q64FV). Emulation of W25Q128 in dummyflasher will be extended to support WP. Haven't tested this one on hardware, but it's the same configuration as for W25Q64 except that it has WPS. W25Q64JV chip was renamed to W25Q64JV-.M (those with QPI). W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS) and W25Q64JV-.Q (SR3 and WPS, but no QPI). Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* jlink_spi: Add option to enable target powerMarc Schink2022-04-302-1/+50
| | | | | | | | Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48380 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Document where raiden_debug_spi_requests are handledEdward O'Callaghan2022-04-301-0/+8
| | | | | | | | | | | | | | | | | Because the enum is a different name to the one within cr50 it was entirely unclear where these values were handled at the end-point and what a untargetted REQ_ENABLE actually did. Comment to avoid needing to chase this again. BUG=b:224358254 TEST=builds Change-Id: I8cc78a85660190c9f750bf67994f0d59d69592d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* Makefile: Align BITBANG_SPI with the other DEPENDS_ and USE_ configsThomas Heijligen2022-04-291-13/+5
| | | | | | | | | | Drop not needed `-DCONFIG_BITBANG_SPI=1` Change-Id: I2a519c929f7747af70568284823b51678751e285 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-15 14:09:28 +0000