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| author | Edward O'Callaghan <quasisec@google.com> | 2022-05-11 12:30:34 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-05-12 02:57:08 +0000 |
| commit | e9367e614e193ed8bc0409903b02a9dac9f88c25 (patch) | |
| tree | e6bfb4114193cd477023ca6f76057f66d061c1e5 | |
| parent | fa2cf255ec587f02baf987f21ab6d01de5db8c8e (diff) | |
| download | flashrom-e9367e614e193ed8bc0409903b02a9dac9f88c25.tar.gz flashrom-e9367e614e193ed8bc0409903b02a9dac9f88c25.tar.bz2 flashrom-e9367e614e193ed8bc0409903b02a9dac9f88c25.zip | |
it85spi.c: Fix some space/tab trivial style issues
Change-Id: I9192461281f9e760644a241148f4c5100f76da98
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64246
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | it85spi.c | 53 |
1 files changed, 27 insertions, 26 deletions
@@ -241,53 +241,54 @@ static int it85xx_spi_send_command(const struct flashctx *flash, struct it85spi_data *data = flash->mst->spi.data; it85xx_enter_scratch_rom(data); - /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt the EC. - */ + /* + * Exit scratch ROM ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt the EC. + */ #ifdef LPC_IO - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); - INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - mmio_writeb(0, data->ce_high); + mmio_writeb(0, data->ce_high); #endif - for (i = 0; i < writecnt; ++i) { + for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO - INDIRECT_WRITE(data->shm_io_base, writearr[i]); + INDIRECT_WRITE(data->shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - mmio_writeb(writearr[i], data->ce_low); + mmio_writeb(writearr[i], data->ce_low); #endif - } - for (i = 0; i < readcnt; ++i) { + } + for (i = 0; i < readcnt; ++i) { #ifdef LPC_IO - readarr[i] = INDIRECT_READ(data->shm_io_base); + readarr[i] = INDIRECT_READ(data->shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = mmio_readb(data->ce_low); + readarr[i] = mmio_readb(data->ce_low); #endif - } + } #ifdef LPC_IO - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); - INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - mmio_writeb(0, data->ce_high); + mmio_writeb(0, data->ce_high); #endif - return 0; + return 0; } static const struct spi_master spi_master_it85xx = { - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, .shutdown = it85xx_shutdown, }; |