diff options
Diffstat (limited to 'spi25.c')
| -rw-r--r-- | spi25.c | 22 |
1 files changed, 11 insertions, 11 deletions
@@ -479,7 +479,7 @@ int spi_chip_erase_60(struct flashctx *flash) * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -515,7 +515,7 @@ int spi_chip_erase_c7(struct flashctx *flash) * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -557,7 +557,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -604,7 +604,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -649,7 +649,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -692,7 +692,7 @@ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -805,7 +805,7 @@ static int spi_write_status_register_flag(struct flashctx *flash, int status, co * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { + while (spi_read_status_register(flash) & SPI_SR_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); return TIMEOUT_ERROR; @@ -1035,7 +1035,7 @@ int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); if (rc) break; - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } if (rc) @@ -1062,7 +1062,7 @@ int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, result = spi_byte_program(flash, i, buf[i - start]); if (result) return 1; - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } @@ -1157,7 +1157,7 @@ int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, */ return result; } - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); /* We already wrote 2 bytes in the multicommand step. */ @@ -1169,7 +1169,7 @@ int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, cmd[2] = buf[pos++ - start]; spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } |