diff options
| -rw-r--r-- | include/flash.h | 7 | ||||
| -rw-r--r-- | include/spi.h | 10 | ||||
| -rw-r--r-- | spi25_statusreg.c | 14 |
3 files changed, 31 insertions, 0 deletions
diff --git a/include/flash.h b/include/flash.h index ea8e25b8..197c11ea 100644 --- a/include/flash.h +++ b/include/flash.h @@ -155,6 +155,12 @@ enum write_granularity { #define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2) #define FEATURE_WRSR3 (1 << 23) +/* + * Whether chip has security register (RDSCUR/WRSCUR commands). + * Not to be confused with "secure registers" of OTP. + */ +#define FEATURE_SCUR (1 << 24) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -189,6 +195,7 @@ enum flash_reg { STATUS1, STATUS2, STATUS3, + SECURITY, MAX_REGISTERS }; diff --git a/include/spi.h b/include/spi.h index 9b38cab6..c77866c4 100644 --- a/include/spi.h +++ b/include/spi.h @@ -167,6 +167,16 @@ #define JEDEC_WRSR3_OUTSIZE 0x02 #define JEDEC_WRSR3_INSIZE 0x00 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2b +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Write Security Register */ +#define JEDEC_WRSCUR 0x2f +#define JEDEC_WRSCUR_OUTSIZE 0x01 +#define JEDEC_WRSCUR_INSIZE 0x00 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index d0ce8597..2859b232 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -100,6 +100,13 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot write SR3: unsupported by chip\n"); return 1; + case SECURITY: + /* + * Security register doesn't have a normal write operation. Instead, + * there are separate commands that set individual OTP bits. + */ + msg_cerr("Cannot write SECURITY: unsupported by design\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -195,6 +202,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot read SR3: unsupported by chip\n"); return 1; + case SECURITY: + if (feature_bits & FEATURE_SCUR) { + read_cmd = JEDEC_RDSCUR; + break; + } + msg_cerr("Cannot read SECURITY: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; |