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-rw-r--r--flash.h1
-rw-r--r--spi.h10
-rw-r--r--spi25_statusreg.c8
3 files changed, 19 insertions, 0 deletions
diff --git a/flash.h b/flash.h
index b283c6cb..509f2266 100644
--- a/flash.h
+++ b/flash.h
@@ -174,6 +174,7 @@ enum flash_reg {
INVALID_REG = 0,
STATUS1,
STATUS2,
+ STATUS3,
MAX_REGISTERS
};
diff --git a/spi.h b/spi.h
index 845b6c2a..14f71aa0 100644
--- a/spi.h
+++ b/spi.h
@@ -136,6 +136,11 @@
#define JEDEC_RDSR2_OUTSIZE 0x01
#define JEDEC_RDSR2_INSIZE 0x01
+/* Read Status Register 3 */
+#define JEDEC_RDSR3 0x15
+#define JEDEC_RDSR3_OUTSIZE 0x01
+#define JEDEC_RDSR3_INSIZE 0x01
+
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
@@ -158,6 +163,11 @@
#define JEDEC_WRSR2_OUTSIZE 0x02
#define JEDEC_WRSR2_INSIZE 0x00
+/* Write Status Register 3 */
+#define JEDEC_WRSR3 0x11
+#define JEDEC_WRSR3_OUTSIZE 0x02
+#define JEDEC_WRSR3_INSIZE 0x00
+
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 6b168398..0f430565 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -66,6 +66,11 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
}
msg_cerr("Cannot write SR2: unsupported by chip\n");
return 1;
+ case STATUS3:
+ write_cmd[0] = JEDEC_WRSR3;
+ write_cmd[1] = value;
+ write_cmd_len = JEDEC_WRSR3_OUTSIZE;
+ break;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -153,6 +158,9 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
}
msg_cerr("Cannot read SR2: unsupported by chip\n");
return 1;
+ case STATUS3:
+ read_cmd = JEDEC_RDSR3;
+ break;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;