iCE40/flashrom - clone of https://github.com/flashrom/flashrom

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author	Edward O'Callaghan <quasisec@google.com>	2020-10-09 12:56:53 +1100
committer	Edward O'Callaghan <quasisec@chromium.org>	2020-10-12 04:42:39 +0000
commit	91c10aebb35893fdabb2d094155745468b90b5f5 (patch)
tree	8812b26bd2d22a71cc2cbcc29a3a6e5bb995aca8 /util/git-hooks/applypatch-msg
parent	90ac9872cdd2a7dc254c182cec74d2314a3e9b2f (diff)
download	flashrom-91c10aebb35893fdabb2d094155745468b90b5f5.tar.gz flashrom-91c10aebb35893fdabb2d094155745468b90b5f5.tar.bz2 flashrom-91c10aebb35893fdabb2d094155745468b90b5f5.zip

dediprog.c: Fix layering violation of default_spi_read

default_spi_read() calls spi_read_chunked() with the correct max_read value of 16 set in the spi master struct. Change-Id: Ic0897f74056e3d723a33c063ed0bd8cb6e88ba45 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46232 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Diffstat (limited to 'util/git-hooks/applypatch-msg')

0 files changed, 0 insertions, 0 deletions

/* * linux/arch/ia64/kernel/time.c * * Copyright (C) 1998-2003 Hewlett-Packard Co * Stephane Eranian <eranian@hpl.hp.com> * David Mosberger <davidm@hpl.hp.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> * Copyright (C) 1999-2000 VA Linux Systems * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com> */ #include <linux/config.h> #include <linux/cpu.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/profile.h> #include <linux/sched.h> #include <linux/time.h> #include <linux/interrupt.h> #include <linux/efi.h> #include <linux/profile.h> #include <linux/timex.h> #include <asm/machvec.h> #include <asm/delay.h> #include <asm/hw_irq.h> #include <asm/ptrace.h> #include <asm/sal.h> #include <asm/sections.h> #include <asm/system.h> #ifdef XEN #include <linux/jiffies.h> // not included by xen/sched.h #endif extern unsigned long wall_jiffies; u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES; EXPORT_SYMBOL(jiffies_64); #define TIME_KEEPER_ID 0 /* smp_processor_id() of time-keeper */ #ifdef CONFIG_IA64_DEBUG_IRQ unsigned long last_cli_ip; EXPORT_SYMBOL(last_cli_ip); #endif #ifndef XEN static struct time_interpolator itc_interpolator = { .shift = 16, .mask = 0xffffffffffffffffLL, .source = TIME_SOURCE_CPU }; static irqreturn_t timer_interrupt (int irq, void *dev_id, struct pt_regs *regs) { unsigned long new_itm; if (unlikely(cpu_is_offline(smp_processor_id()))) { return IRQ_HANDLED; } platform_timer_interrupt(irq, dev_id, regs); new_itm = local_cpu_data->itm_next; if (!time_after(ia64_get_itc(), new_itm)) printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n", ia64_get_itc(), new_itm); profile_tick(CPU_PROFILING, regs); while (1) { update_process_times(user_mode(regs)); new_itm += local_cpu_data->itm_delta; if (smp_processor_id() == TIME_KEEPER_ID) { /* * Here we are in the timer irq handler. We have irqs locally * disabled, but we don't know if the timer_bh is running on * another CPU. We need to avoid to SMP race by acquiring the * xtime_lock. */ write_seqlock(&xtime_lock); do_timer(regs); local_cpu_data->itm_next = new_itm; write_sequnlock(&xtime_lock); } else local_cpu_data->itm_next = new_itm; if (time_after(new_itm, ia64_get_itc())) break; } do { /* * If we're too close to the next clock tick for * comfort, we increase the safety margin by * intentionally dropping the next tick(s). We do NOT * update itm.next because that would force us to call * do_timer() which in turn would let our clock run * too fast (with the potentially devastating effect * of losing monotony of time). */ while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2)) new_itm += local_cpu_data->itm_delta; ia64_set_itm(new_itm); /* double check, in case we got hit by a (slow) PMI: */ } while (time_after_eq(ia64_get_itc(), new_itm)); return IRQ_HANDLED; } #endif /* * Encapsulate access to the itm structure for SMP. */ void ia64_cpu_local_tick (void) { int cpu = smp_processor_id(); unsigned long shift = 0, delta; /* arrange for the cycle counter to generate a timer interrupt: */ ia64_set_itv(IA64_TIMER_VECTOR); delta = local_cpu_data->itm_delta; /* * Stagger the timer tick for each CPU so they don't occur all at (almost) the * same time: */ if (cpu) { unsigned long hi = 1UL << ia64_fls(cpu); shift = (2*(cpu - hi) + 1) * delta/hi/2; } local_cpu_data->itm_next = ia64_get_itc() + delta + shift; ia64_set_itm(local_cpu_data->itm_next); } static int nojitter; static int __init nojitter_setup(char *str) { nojitter = 1; printk("Jitter checking for ITC timers disabled\n"); return 1; } __setup("nojitter", nojitter_setup); void __devinit ia64_init_itm (void) { unsigned long platform_base_freq, itc_freq; struct pal_freq_ratio itc_ratio, proc_ratio; #ifdef XEN /* warning cleanup */ unsigned long status, platform_base_drift, itc_drift; #else long status, platform_base_drift, itc_drift; #endif /* * According to SAL v2.6, we need to use a SAL call to determine the platform base * frequency and then a PAL call to determine the frequency ratio between the ITC * and the base frequency. */ status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM, &platform_base_freq, &platform_base_drift); if (status != 0) { printk(KERN_ERR "SAL_FREQ_BASE_PLATFORM failed: %s\n", ia64_sal_strerror(status)); } else { status = ia64_pal_freq_ratios(&proc_ratio, NULL, &itc_ratio); if (status != 0) printk(KERN_ERR "PAL_FREQ_RATIOS failed with status=%ld\n", status); } if (status != 0) { /* invent "random" values */ printk(KERN_ERR "SAL/PAL failed to obtain frequency info---inventing reasonable values\n"); platform_base_freq = 100000000; platform_base_drift = -1; /* no drift info */ itc_ratio.num = 3; itc_ratio.den = 1; } if (platform_base_freq < 40000000) { printk(KERN_ERR "Platform base frequency %lu bogus---resetting to 75MHz!\n", platform_base_freq); platform_base_freq = 75000000;


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