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author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-02-13 23:41:01 +0000 |
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committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-02-13 23:41:01 +0000 |
commit | ea3b1b4db229584aad17704c87015e1623b9cb17 (patch) | |
tree | 10cd6cce461642335402ac657f45f1f2b8748e02 /print.c | |
parent | cd446f4b93ae647023a701ce92c9653a9efdea15 (diff) | |
download | flashrom-ea3b1b4db229584aad17704c87015e1623b9cb17.tar.gz flashrom-ea3b1b4db229584aad17704c87015e1623b9cb17.tar.bz2 flashrom-ea3b1b4db229584aad17704c87015e1623b9cb17.zip |
Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets from Nvidia
Huge thanks to Michael Karcher for reverse engineering the MCP67 chipset
and writing a spec. Due to this, we were able to use the chinese wall
technique for 100% clean room reverse engineering.
This patch doesn't touch any of the new registers, it only reads them.
Assuming that read has no side effects, this patch is a no-op and safe.
We need "flashrom -V" output from all post-MCP55 (nForce 5) chipset
boards. Please indicate if your board uses SPI flash or LPC flash (if
you know it). Note: That output is only helpful if it is created with
patched flashrom and if is from the first run of flashrom after a cold
boot (reset or Ctrl-Alt-Del is not sufficient). There is a pattern based
on which we can probably detect which flash type is present on the
board.
Thanks to Alessandro Polverini for testing earlier iterations of this
patch.
Note: The MCP67 should work. I guessed that the other recent Nvidia
chipsets would work in a similar way, and created a simplified
do-nothing catchall chipset enable function which dumps some info and
instructs the user to send more info.
Corresponding to flashrom svn r902.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Diffstat (limited to 'print.c')
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