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author | Brian J. Nemec <bnemec@chromium.org> | 2020-07-19 13:37:42 -0700 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-07-21 00:39:35 +0000 |
commit | a7b526d92b0f18680f495c904edc57b18dd45a77 (patch) | |
tree | 55473a325506f55c823955623a4262c6679e5bd7 /ogp_spi.c | |
parent | 7ac57c77beefc2cd098ad16d9ab2a73ef9e763e0 (diff) | |
download | flashrom-a7b526d92b0f18680f495c904edc57b18dd45a77.tar.gz flashrom-a7b526d92b0f18680f495c904edc57b18dd45a77.tar.bz2 flashrom-a7b526d92b0f18680f495c904edc57b18dd45a77.zip |
raiden_debug_spi.c: Add protocol based configuration to init
Add a configuration stage to the initialization. This enables
us to dynamically set the maximum SPI write and read limits
based on the device we are connected to and switch the command
function. These changes will enable us to have larger SPI
transfers in protocol V2 and separate out the logic flow used
for the different protocols.
BUG=b:139058552
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami.
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: Id404af14e55fa0884e29f28880206aaad4deba66
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41532
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'ogp_spi.c')
0 files changed, 0 insertions, 0 deletions