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| author | Nico Huber <nico.huber@secunet.com> | 2019-01-18 14:23:02 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-07-06 17:15:58 +0000 |
| commit | 3750986348cb99b8f0d828b73972b545a2f9c878 (patch) | |
| tree | 62b7c2d2a5b84561596fdbbeddc6111d27dfc315 /ichspi.c | |
| parent | 908adf4589d34eaf3bd8395afa52aed8c8887cfd (diff) | |
| download | flashrom-3750986348cb99b8f0d828b73972b545a2f9c878.tar.gz flashrom-3750986348cb99b8f0d828b73972b545a2f9c878.tar.bz2 flashrom-3750986348cb99b8f0d828b73972b545a2f9c878.zip | |
chipset_enable: Add Apollo Lake
It works the same as 100 series PCHs and on. The SPI device is at
0:0d.2, though. Mark as BAD until `ichspi` is revised.
Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'ichspi.c')
0 files changed, 0 insertions, 0 deletions