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| author | Rosen Penev <rosenp@gmail.com> | 2022-03-12 23:54:18 -0800 |
|---|---|---|
| committer | Thomas Heijligen <src@posteo.de> | 2022-07-18 09:52:40 +0000 |
| commit | ed2da0f2bca3bb7316c7e81cfa3cfc068a31aa71 (patch) | |
| tree | 0d89e00917af52f3803f00eaa09bf87e38eb4742 /hwaccess_physmap.c | |
| parent | c9b7ae55d1f75640a363e85d6c318e822eb255ef (diff) | |
| download | flashrom-ed2da0f2bca3bb7316c7e81cfa3cfc068a31aa71.tar.gz flashrom-ed2da0f2bca3bb7316c7e81cfa3cfc068a31aa71.tar.bz2 flashrom-ed2da0f2bca3bb7316c7e81cfa3cfc068a31aa71.zip | |
hwaccess: use __asm__ as it is done elsewhere
`asm()` doesn't work with musl libc, as it is specific to glibc. Thus,
use `__asm__` as it is done elsewhere to fix compilation under
non-glibc.
Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'hwaccess_physmap.c')
| -rw-r--r-- | hwaccess_physmap.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index 2a2a2434..81adf18e 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -383,18 +383,18 @@ static inline void sync_primitive(void) #if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ defined(_ARCH_PPC64) || defined(__ppc) - asm("eieio" : : : "memory"); + __asm__("eieio" : : : "memory"); #elif (__sparc__) || defined (__sparc) #if defined(__sparc_v9__) || defined(__sparcv9) /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we * use the strongest hardware memory barriers that exist on Sparc V9. */ - asm volatile ("membar #Sync" ::: "memory"); + __asm__ volatile ("membar #Sync" ::: "memory"); #elif defined(__sparc_v8__) || defined(__sparcv8) /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable * operation in the V8 instruction set anyway. If you know better then please tell us. */ - asm volatile ("stbar"); + __asm__ volatile ("stbar"); #else #error Unknown and/or unsupported SPARC instruction set version detected. #endif |