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| author | Edward O'Callaghan <quasisec@google.com> | 2020-03-05 15:12:29 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-03-11 06:26:37 +0000 |
| commit | 3e67cb7b78af5ff975eb6144f15ef45db0810da6 (patch) | |
| tree | 33ea073ce39dc43ddc69956e03e6ab3972fd8981 /chipset_enable.c | |
| parent | 8b191f5ced93dc4d376ce4c6e83fb3ca139c6e77 (diff) | |
| download | flashrom-3e67cb7b78af5ff975eb6144f15ef45db0810da6.tar.gz flashrom-3e67cb7b78af5ff975eb6144f15ef45db0810da6.tar.bz2 flashrom-3e67cb7b78af5ff975eb6144f15ef45db0810da6.zip | |
raiden_debug_spi.c: Add a delay following AP/EC flash enable
Add a delay following the AP and EC flash enable requests. This allows
any power rails enabled by these signals to settle and to meet the power
on to first SPI write timing requirements.
Forward ports the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
0 files changed, 0 insertions, 0 deletions