diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-08-19 12:16:40 -0700 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2020-08-27 20:30:09 +0000 |
| commit | f33f1a11793e00b88b69de8463f1336ae17d6218 (patch) | |
| tree | 685ecc4a6871ebaa5d917e139efa4150c08a48ed | |
| parent | 3b1294583526769b3fa2e4f4df6e4b033db14b2d (diff) | |
| download | flashrom-f33f1a11793e00b88b69de8463f1336ae17d6218.tar.gz flashrom-f33f1a11793e00b88b69de8463f1336ae17d6218.tar.bz2 flashrom-f33f1a11793e00b88b69de8463f1336ae17d6218.zip | |
add PCI IDs for additional c620 series PCH chips
Add PCI IDs for C621A, C627A and C629A.
Change-Id: I636becd9f08bdf604c6af81ce396049655353b04
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | chipset_enable.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 4772a1c4..5fc222b2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2035,6 +2035,9 @@ const struct penable chipset_enables[] = { {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, |