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| author | Edward O'Callaghan <quasisec@google.com> | 2020-10-15 19:19:05 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-10-27 11:33:02 +0000 |
| commit | da0825f05f0d8d1af2e12ab3ccf950051a3eb608 (patch) | |
| tree | f32d01406c791bdcb57634bc512dca6e4bae2a41 | |
| parent | c15de25a7ca6504a4191f8da44448a0723923e58 (diff) | |
| download | flashrom-da0825f05f0d8d1af2e12ab3ccf950051a3eb608.tar.gz flashrom-da0825f05f0d8d1af2e12ab3ccf950051a3eb608.tar.bz2 flashrom-da0825f05f0d8d1af2e12ab3ccf950051a3eb608.zip | |
chipset_enable.c: check return value from rphysmap() call
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 9769ba45..42734786 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1010,6 +1010,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). |