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| author | Anastasia Klimchuk <aklm@chromium.org> | 2021-10-29 15:26:28 +1100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2022-02-02 21:51:53 +0000 |
| commit | 97a1683c85b1f24ff0605e7571d2f6094e32a547 (patch) | |
| tree | 5d9782b4d2d4d0afde0fa9bf747b4e4532e1ff72 | |
| parent | 629379029310a3f76decdeeb2199a267bfffac34 (diff) | |
| download | flashrom-97a1683c85b1f24ff0605e7571d2f6094e32a547.tar.gz flashrom-97a1683c85b1f24ff0605e7571d2f6094e32a547.tar.bz2 flashrom-97a1683c85b1f24ff0605e7571d2f6094e32a547.zip | |
ichspi: Extract initialisation of swseq and hwseq into a function
Initialisation of swseq_data and hwseq_data gets its own function,
which is called from init_ich_default. This makes init_ich_default
more readable.
This patch also gives a name to (previously anonymous) struct
swseq_data. Its sibling struct hwseq_data already has a name. Structs
need names to be able to declare function parameters.
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3
Tested-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | ichspi.c | 75 |
1 files changed, 41 insertions, 34 deletions
@@ -507,7 +507,7 @@ static void prettyprint_pch100_reg_dlock(const uint32_t reg_val) pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n"); } -static struct { +static struct swseq_data { size_t reg_ssfsc; size_t reg_preop; size_t reg_optype; @@ -1784,18 +1784,10 @@ static int get_ich_spi_mode_param(enum ich_spi_mode *ich_spi_mode) return 0; } - -static int init_ich_default(void *spibar, enum ich_chipset ich_gen) +static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data *hwseq, + size_t *num_freg, size_t *num_pr, size_t *reg_pr0, + enum ich_chipset ich_gen) { - unsigned int i; - uint16_t tmp2; - uint32_t tmp; - int ich_spi_rw_restricted = 0; - int desc_valid = 0; - struct ich_descriptors desc = { 0 }; - enum ich_spi_mode ich_spi_mode = ich_auto; - size_t num_freg, num_pr, reg_pr0; - /* Moving registers / bits */ switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1805,46 +1797,61 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen) case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: - num_pr = 6; /* Includes GPR0 */ - reg_pr0 = PCH100_REG_FPR0; - swseq_data.reg_ssfsc = PCH100_REG_SSFSC; - swseq_data.reg_preop = PCH100_REG_PREOP; - swseq_data.reg_optype = PCH100_REG_OPTYPE; - swseq_data.reg_opmenu = PCH100_REG_OPMENU; - hwseq_data.addr_mask = PCH100_FADDR_FLA; - hwseq_data.only_4k = true; - hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; + *num_pr = 6; /* Includes GPR0 */ + *reg_pr0 = PCH100_REG_FPR0; + swseq->reg_ssfsc = PCH100_REG_SSFSC; + swseq->reg_preop = PCH100_REG_PREOP; + swseq->reg_optype = PCH100_REG_OPTYPE; + swseq->reg_opmenu = PCH100_REG_OPMENU; + hwseq->addr_mask = PCH100_FADDR_FLA; + hwseq->only_4k = true; + hwseq->hsfc_fcycle = PCH100_HSFC_FCYCLE; break; default: - num_pr = 5; - reg_pr0 = ICH9_REG_PR0; - swseq_data.reg_ssfsc = ICH9_REG_SSFS; - swseq_data.reg_preop = ICH9_REG_PREOP; - swseq_data.reg_optype = ICH9_REG_OPTYPE; - swseq_data.reg_opmenu = ICH9_REG_OPMENU; - hwseq_data.addr_mask = ICH9_FADDR_FLA; - hwseq_data.only_4k = false; - hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + *num_pr = 5; + *reg_pr0 = ICH9_REG_PR0; + swseq->reg_ssfsc = ICH9_REG_SSFS; + swseq->reg_preop = ICH9_REG_PREOP; + swseq->reg_optype = ICH9_REG_OPTYPE; + swseq->reg_opmenu = ICH9_REG_OPMENU; + hwseq->addr_mask = ICH9_FADDR_FLA; + hwseq->only_4k = false; + hwseq->hsfc_fcycle = HSFC_FCYCLE; break; } + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: - num_freg = 10; + *num_freg = 10; break; case CHIPSET_C620_SERIES_LEWISBURG: - num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ + *num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: - num_freg = 16; + *num_freg = 16; break; default: - num_freg = 5; + *num_freg = 5; break; } +} + +static int init_ich_default(void *spibar, enum ich_chipset ich_gen) +{ + unsigned int i; + uint16_t tmp2; + uint32_t tmp; + int ich_spi_rw_restricted = 0; + int desc_valid = 0; + struct ich_descriptors desc = { 0 }; + enum ich_spi_mode ich_spi_mode = ich_auto; + size_t num_freg, num_pr, reg_pr0; + + init_chipset_properties(&swseq_data, &hwseq_data, &num_freg, &num_pr, ®_pr0, ich_gen); int ret = get_ich_spi_mode_param(&ich_spi_mode); if (ret) |