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| author | Nikolai Artemiev <nartemiev@google.com> | 2021-10-21 01:12:39 +1100 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-03-01 04:04:04 +0000 |
| commit | 645e5e777a3c2ebc83e0bdb52d73355a9b5814fa (patch) | |
| tree | 54b8c7d195511f13ce6715c034479c73eca41e0b | |
| parent | e00790865726b6f1a6492af0833e3cbf9c215496 (diff) | |
| download | flashrom-645e5e777a3c2ebc83e0bdb52d73355a9b5814fa.tar.gz flashrom-645e5e777a3c2ebc83e0bdb52d73355a9b5814fa.tar.bz2 flashrom-645e5e777a3c2ebc83e0bdb52d73355a9b5814fa.zip | |
writeprotect.h: add structure to represent chip wp configuration bits
Add `struct wp_bits` for representing values of all WP bits in a chip's
status/config register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | writeprotect.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/writeprotect.h b/writeprotect.h index 8510226d..2f473f74 100644 --- a/writeprotect.h +++ b/writeprotect.h @@ -18,6 +18,42 @@ #ifndef __WRITEPROTECT_H__ #define __WRITEPROTECT_H__ 1 +#include <stdint.h> +#include <stdbool.h> +#include <stddef.h> + #define MAX_BP_BITS 4 +/* + * Description of a chip's write protection configuration. + * + * It allows most WP code to store and manipulate a chip's configuration + * without knowing the exact layout of bits in the chip's status registers. + */ +struct wp_bits { + /* Status register protection bit (SRP) */ + bool srp_bit_present; + uint8_t srp; + + /* Status register lock bit (SRL) */ + bool srl_bit_present; + uint8_t srl; + + /* Complement bit (CMP) */ + bool cmp_bit_present; + uint8_t cmp; + + /* Sector/block protection bit (SEC) */ + bool sec_bit_present; + uint8_t sec; + + /* Top/bottom protection bit (TB) */ + bool tb_bit_present; + uint8_t tb; + + /* Block protection bits (BP) */ + size_t bp_bit_count; + uint8_t bp[MAX_BP_BITS]; +}; + #endif /* !__WRITEPROTECT_H__ */ |