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authorNico Huber <nico.huber@secunet.com>2022-06-20 19:37:37 +0200
committerNico Huber <nico.h@gmx.de>2022-06-23 14:42:11 +0000
commit62b020ac5f9445135674253d4cb639cfe7002049 (patch)
tree6d5340e2ce9ab261809a2a18bd431d74f4792588
parente8ce432faafc6794540a2e074af34e5d1fabf138 (diff)
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flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512S
According to its datasheet, Spansion S25FL512S supports writing/ reading its extended address register via 0x17/0x16 opcodes. With that enabled, we can also enable the EAR7 feature, i.e. toggling 4BA mode via bit 7 of that register. S25FL512S did not advertise EAR support at all, so we set it to TEST_UNTESTED again. Change-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
-rw-r--r--flashchips.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/flashchips.c b/flashchips.c
index 5edf6a20..eee1ed98 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -16843,8 +16843,9 @@ const struct flashchip flashchips[] = {
.total_size = 65536, /* 512 Mb (=> 64 MB)) */
.page_size = 256,
/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_NATIVE,
- .tested = TEST_OK_PREW,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
+ FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
+ .tested = TEST_UNTESTED,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =