diff options
author | Nico Huber <nico.h@gmx.de> | 2017-12-13 00:44:45 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2017-12-19 12:30:05 +0000 |
commit | 19eb0792b8439198d7ef0077b8f79f275fa39a9d (patch) | |
tree | b2d1e9a9e53150c48828f2e38afbf6264d48b6ac | |
parent | 3083ed90c62e9516615e2322f23ca798e5124a8f (diff) | |
download | flashrom-19eb0792b8439198d7ef0077b8f79f275fa39a9d.tar.gz flashrom-19eb0792b8439198d7ef0077b8f79f275fa39a9d.tar.bz2 flashrom-19eb0792b8439198d7ef0077b8f79f275fa39a9d.zip |
ichspi: Fix 100 series PCH (Skylake) support
Pretty subtle missing `else` made flashrom treat Skylake like older
chipsets.
Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net>
Reviewed-on: https://review.coreboot.org/22832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
-rw-r--r-- | ichspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1715,7 +1715,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { + } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; |