blob: dcf9d1299dec484b5bdb097a92fa436b9b5d8642 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
`timescale 1ns/1ns
module touch
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire touch_key ,
output reg led
);
wire touch_en ;
//reg define
reg touch_key_dly1 ;
reg touch_key_dly2 ;
assign touch_en = touch_key_dly2 & (~touch_key_dly1);
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
begin
touch_key_dly1 <= 1'b0;
touch_key_dly2 <= 1'b0;
end
else
begin
touch_key_dly1 <= touch_key;
touch_key_dly2 <= touch_key_dly1;
end
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
led <= 1'b1;
else if(touch_en == 1'b1)
led <= ~led;
endmodule
|
