path: root/fpga/hp_lcd_driver/zynq7_wrapper.vhdl

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-- Copyright (C) 2020 - embed-me
--
-- Lukas Lichtl <support@embed-me.com>
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License v2 as published by
-- the Free Software Foundation.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Function description:
-- 
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library UNISIM;
use UNISIM.vcomponents.all;


entity zynq7_wrapper is
    generic (input_video_width : natural := 2;
             video_width       : natural := 2;
             addr_width        : natural := 18;
             phase_slip        : natural := 320;
             i_clk_multiple    : natural := 4;
             use_pclk          : natural := 0;
             target            : string  := "zynq7");
    port (
        -- ddr
        ddr_addr_io          : inout std_logic_vector (14 downto 0);
        ddr_ba_io            : inout std_logic_vector (2 downto 0);
        ddr_cas_n_io         : inout std_logic;
        ddr_ck_n_io          : inout std_logic;
        ddr_ck_p_io          : inout std_logic;
        ddr_cke_io           : inout std_logic;
        ddr_cs_n_io          : inout std_logic;
        ddr_dm_io            : inout std_logic_vector (3 downto 0);
        ddr_dq_io            : inout std_logic_vector (31 downto 0);
        ddr_dqs_n_io         : inout std_logic_vector (3 downto 0);
        ddr_dqs_p_io         : inout std_logic_vector (3 downto 0);
        ddr_odt_io           : inout std_logic;
        ddr_ras_n_io         : inout std_logic;
        ddr_reset_n_io       : inout std_logic;
        ddr_we_n_io          : inout std_logic;
        -- eth0
        eth0_clk_o           : out   std_logic;  -- alternative clock, only used when Oscillator is missing on the PCB
        eth0_gmii_rx_clk_i   : in    std_logic;
        eth0_gmii_rx_dv_i    : in    std_logic;
        eth0_gmii_rxd_i      : in    std_logic_vector (3 downto 0);
        eth0_gmii_tx_clk_i   : in    std_logic;
        eth0_gmii_tx_en_o    : out   std_logic_vector (0 to 0);
        eth0_gmii_txd_o      : out   std_logic_vector (3 downto 0);
        eth0_mdio_mdc_o      : out   std_logic;
        eth0_mdio_mdio_io    : inout std_logic;
        -- ios
        fixed_io_ddr_vrn_io  : inout std_logic;
        fixed_io_ddr_vrp_io  : inout std_logic;
        fixed_io_mio_io      : inout std_logic_vector (53 downto 0);
        fixed_io_ps_clk_io   : inout std_logic;
        fixed_io_ps_porb_io  : inout std_logic;
        fixed_io_ps_srstb_io : inout std_logic;
        green_led            : out   std_logic;
        red_led              : out   std_logic;

--in
        video    : in  std_logic_vector(input_video_width -1 downto 0);
        hsync_in : in  std_logic;
        vsync_in : in  std_logic;
        pclk_in  : in  std_logic;
-- hdmi
        hdmi_c_p : out std_logic;
        hdmi_c_n : out std_logic;
        hdmi_r_p : out std_logic;
        hdmi_r_n : out std_logic;
        hdmi_g_p : out std_logic;
        hdmi_g_n : out std_logic;
        hdmi_b_p : out std_logic;
        hdmi_b_n : out std_logic;
        hdmi_vcc : out std_logic
        );

end entity zynq7_wrapper;



architecture arch of zynq7_wrapper is

    signal eth0_gmii_txd : std_logic_vector(7 downto 0);
    signal eth0_gmii_rxd : std_logic_vector(7 downto 0);

    signal emio_i : std_logic_vector(63 downto 0);
    signal emio_o : std_logic_vector(63 downto 0);
    signal emio_t : std_logic_vector(63 downto 0);



    signal gp0_aclk : std_logic;
    signal gp0_nrst : std_logic;

    signal hp0_aclk    : std_logic;
    signal hp0_nrst    : std_logic;
    signal hp0_arvalid : std_logic;
    signal hp0_araddr  : std_logic_vector(31 downto 0);
    signal hp0_arready : std_logic;
    signal hp0_awaddr  : std_logic_vector(31 downto 0);
    signal hp0_awready : std_logic;
    signal hp0_awvalid : std_logic;
    signal hp0_bready  : std_logic;
    signal hp0_bvalid  : std_logic;
    signal hp0_rdata   : std_logic_vector(63 downto 0);
    signal hp0_wdata   : std_logic_vector(63 downto 0);
    signal hp0_rready  : std_logic;
    signal hp0_rvalid  : std_logic;
    signal hp0_wready  : std_logic;
    signal hp0_wvalid  : std_logic;
    signal hp0_wstrb   : std_logic_vector(7 downto 0);


    signal fifo_rst_cnt : natural;
    signal fifo_rst     : std_logic;
    signal fifo_wr_en   : std_logic;
    signal fifo_wdata   : std_logic_vector(64 downto 0);
    signal fifo_rd_en   : std_logic;
    signal fifo_rdata   : std_logic_vector(64 downto 0);
    signal fifo_empty   : std_logic;

    signal run : std_logic;

    signal eth0_mdio_mdio_i : std_logic;
    signal eth0_mdio_mdio_o : std_logic;
    signal eth0_mdio_mdio_t : std_logic;

    signal clk_50m   : std_logic;
    signal sys_rst_n : std_logic;

    signal vnc_clk   : std_logic;
    signal vnc_valid : std_logic;
    signal vnc_data  : std_logic_vector(video_width-1 downto 0);
    signal vnc_index : std_logic;


begin


    clk_50m <= hp0_aclk;

    common_i : entity work.common
        generic map (
            input_video_width => input_video_width,
            video_width       => video_width,
            addr_width        => addr_width,
            phase_slip        => phase_slip,
            i_clk_multiple    => i_clk_multiple,
            use_pclk          => use_pclk,
            target            => target)
        port map (clk_50m         => clk_50m,
                  sys_rst_n       => sys_rst_n,
                  video           => video,
                  hsync_in        => hsync_in,
                  vsync_in        => vsync_in,
                  pclk_in         => pclk_in,
                  r_out           => open,
                  b_out           => open,
                  g_out           => open,
                  hsync_out       => open,
                  vsync_out       => open,
                  hdmi_c_p        => hdmi_c_p,
                  hdmi_c_n        => hdmi_c_n,
                  hdmi_r_p        => hdmi_r_p,
                  hdmi_r_n        => hdmi_r_n,
                  hdmi_g_p        => hdmi_g_p,
                  hdmi_g_n        => hdmi_g_n,
                  hdmi_b_p        => hdmi_b_p,
                  hdmi_b_n        => hdmi_b_n,
                  hdmi_vcc        => hdmi_vcc,
                  i_clk_out       => open,
                  led             => open,
                  video_out_clk   => vnc_clk,
                  video_out_valid => vnc_valid,
                  video_out_data  => vnc_data,
                  video_out_index => vnc_index
                  );

    processing_system7_0_i : entity work.processing_system7_0
        port map (
            DDR_Addr      => ddr_addr_io,
            DDR_BankAddr  => ddr_ba_io,
            DDR_CAS_n     => ddr_cas_n_io,
            DDR_Clk_n     => ddr_ck_n_io,
            DDR_Clk       => ddr_ck_p_io,
            DDR_CKE       => ddr_cke_io,
            DDR_CS_n      => ddr_cs_n_io,
            DDR_DM        => ddr_dm_io,
            DDR_DQ        => ddr_dq_io,
            DDR_DQS_n     => ddr_dqs_n_io,
            DDR_DQS       => ddr_dqs_p_io,
            DDR_ODT       => ddr_odt_io,
            DDR_RAS_n     => ddr_ras_n_io,
            DDR_DRSTB     => ddr_reset_n_io,
            DDR_WEB       => ddr_we_n_io,
            FCLK_CLK0     => eth0_clk_o,
            FCLK_CLK1     => gp0_aclk,
            FCLK_CLK2     => hp0_aclk,
            FCLK_CLK2     => clk_50m,
            FCLK_RESET1_N => gp0_nrst,
            FCLK_RESET2_N => hp0_nrst,
            FCLK_RESET3_N => sys_rst_n,

            ENET0_GMII_RX_CLK => eth0_gmii_rx_clk_i,
            ENET0_GMII_RX_DV  => eth0_gmii_rx_dv_i,
            ENET0_GMII_RXD    => eth0_gmii_rxd,
            ENET0_GMII_RX_ER  => '0',
            ENET0_GMII_COL    => '0',
            ENET0_GMII_CRS    => '0',


            ENET0_GMII_TX_CLK => eth0_gmii_tx_clk_i,
            ENET0_GMII_TX_EN  => eth0_gmii_tx_en_o,
            ENET0_GMII_TXD    => eth0_gmii_txd,

            ENET0_MDIO_MDC   => eth0_mdio_mdc_o,
            ENET0_MDIO_O     => eth0_mdio_mdio_o,
            ENET0_MDIO_I     => eth0_mdio_mdio_i,
            ENET0_MDIO_T     => eth0_mdio_mdio_t,
            DDR_VRN          => fixed_io_ddr_vrn_io,
            DDR_VRP          => fixed_io_ddr_vrp_io,
            MIO(53 downto 0) => fixed_io_mio_io,
            PS_CLK           => fixed_io_ps_clk_io,
            PS_PORB          => fixed_io_ps_porb_io,
            PS_SRSTB         => fixed_io_ps_srstb_io,
            GPIO_I           => emio_i,
            GPIO_O           => emio_o,
            GPIO_T           => emio_t,

            M_AXI_GP0_ACLK    => gp0_aclk,
            M_AXI_GP0_ARREADY => '0',
            M_AXI_GP0_AWREADY => '0',
            M_AXI_GP0_BID     => (others => '0'),
            M_AXI_GP0_BRESP   => (others => '0'),
            M_AXI_GP0_BVALID  => '0',
            M_AXI_GP0_RDATA   => (others => '0'),
            M_AXI_GP0_RID     => (others => '0'),
            M_AXI_GP0_RLAST   => '1',
            M_AXI_GP0_RRESP   => (others => '0'),
            M_AXI_GP0_RVALID  => '0',
            M_AXI_GP0_WREADY  => '0',


            S_AXI_HP0_ACLK    => hp0_aclk,
            S_AXI_HP0_ARADDR  => hp0_araddr,
            S_AXI_HP0_ARBURST => "01",
            S_AXI_HP0_ARCACHE => "0001",
            S_AXI_HP0_ARID    => (others => '0'),
            S_AXI_HP0_ARLEN   => "0000",
            S_AXI_HP0_ARLOCK  => "00",
            S_AXI_HP0_ARPROT  => "000",
            S_AXI_HP0_ARQOS   => "0000",  -- not present in AXI3 which is this 
            S_AXI_HP0_ARREADY => hp0_arready,
            S_AXI_HP0_ARSIZE  => "011",   -- 8 bytes ??
            S_AXI_HP0_ARVALID => hp0_arvalid,
            S_AXI_HP0_AWADDR  => hp0_awaddr,
            S_AXI_HP0_AWBURST => "01",
            S_AXI_HP0_AWCACHE => "0001",
            S_AXI_HP0_AWID    => (others => '0'),
            S_AXI_HP0_AWLEN   => "0000",
            S_AXI_HP0_AWLOCK  => "00",
            S_AXI_HP0_AWPROT  => "000",
            S_AXI_HP0_AWQOS   => "0000",  -- not present in AXI3 which this is
            S_AXI_HP0_AWREADY => hp0_awready,
            S_AXI_HP0_AWSIZE  => "011",   -- 8 bytes?
            S_AXI_HP0_AWVALID => hp0_awvalid,
            S_AXI_HP0_BID     => open,
            S_AXI_HP0_BREADY  => hp0_bready,
            S_AXI_HP0_BRESP   => open,
            S_AXI_HP0_BVALID  => hp0_bvalid,
            S_AXI_HP0_RDATA   => hp0_rdata,
            S_AXI_HP0_RID     => open,
            S_AXI_HP0_RLAST   => open,
            S_AXI_HP0_RREADY  => hp0_rready,
            S_AXI_HP0_RRESP   => open,
            S_AXI_HP0_RVALID  => hp0_rvalid,
            S_AXI_HP0_WDATA   => hp0_wdata,
            S_AXI_HP0_WID     => "000000",
            S_AXI_HP0_WLAST   => '1',
            S_AXI_HP0_WREADY  => hp0_wready,
            S_AXI_HP0_WSTRB   => hp0_wstrb,
            S_AXI_HP0_WVALID  => hp0_wvalid
            );

    eth0_mdio_mdio_iobuf : IOBUF
        port map (
            I  => eth0_mdio_mdio_o,
            IO => eth0_mdio_mdio_io,
            O  => eth0_mdio_mdio_i,
            T  => eth0_mdio_mdio_t
            );


    vnc_serializer_i : entity work.vnc_serializer
        generic map (
            video_width => video_width
            )
        port map (
            clk       => vnc_clk,
            vnc_valid => vnc_valid,
            vnc_data  => vnc_data,
            vnc_index => vnc_index,

            fifo_data => fifo_wdata,
            fifo_wren => fifo_wr_en);


    process (clk_50m)
    begin
        if rising_edge(clk_50m) then
            if sys_rst_n = '0' then
                fifo_rst_cnt <= 20;
                fifo_rst     <= '1';
            elsif fifo_rst_cnt /= 0 then
                fifo_rst_cnt <= fifo_rst_cnt -1;
            else
                fifo_rst <= '0';
            end if;
        end if;
    end process;

    fifo_i : entity work.fifo_generator_0
        port map (
            rst    => fifo_rst,
            wr_clk => vnc_clk,
            din    => fifo_wdata,
            wr_en  => fifo_wr_en,
            rd_clk => hp0_aclk,
            rd_en  => fifo_rd_en,
            dout   => fifo_rdata,
            empty  => fifo_empty
            );



    fifo_to_axi_i : entity work.fifo_to_axi
        port map(
            aclk        => hp0_aclk,
            aresetn     => hp0_nrst,
            axi_awaddr  => hp0_awaddr,
            axi_awvalid => hp0_awvalid,
            axi_awready => hp0_awready,
            axi_wdata   => hp0_wdata,
            axi_wstrb   => hp0_wstrb,
            axi_wvalid  => hp0_wvalid,
            axi_wready  => hp0_wready,
            axi_bvalid  => hp0_bvalid,
            axi_bready  => hp0_bready,

            run => run,

            fifo_empty => fifo_empty,
            fifo_rdata => fifo_rdata,
            fifo_rd_en => fifo_rd_en
            );


    hp0_araddr  <= (others => '0');
    hp0_arvalid <= '0';
    hp0_rready  <= '0';

    -----------------------------------------------------------------------------
    -- IOs
    -----------------------------------------------------------------------------

    eth0_gmii_txd_o <= eth0_gmii_txd(eth0_gmii_txd_o'range);
    eth0_gmii_rxd   <= b"0000" & eth0_gmii_rxd_i;

    red_led   <= emio_o(0);
    green_led <= emio_o(1);
    run       <= emio_o(2);


end architecture arch;