fpga/hp_lcd_driver/vram_artix7.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

library ieee;
use ieee.std_logic_1164.all;

entity vram is
    generic (
        addr_width  : natural := 18;
        video_width : natural := 6
        );
    port (
        wr_clk  : in  std_logic;
        wr_en   : in  std_logic;
        wr_addr : in  std_logic_vector(addr_width-1 downto 0);
        wr_data : in  std_logic_vector(video_width-1 downto 0);
        rd_clk  : in  std_logic;
        rd_addr : in  std_logic_vector(addr_width-1 downto 0);
        rd_data : out std_logic_vector(video_width-1 downto 0)
        );
end vram;

architecture beh of vram is
    signal wr_en_v : std_logic_vector(0 downto 0);
    signal wr_data_6 : std_logic_vector(5 downto 0);
    signal rd_data_6 : std_logic_vector(5 downto 0);
begin

    wr_data_6 <= "00" & wr_data;
    rd_data <= rd_data_6(3 downto 0);


    wr_en_v(0) <= wr_en;

    bmg0 : entity work.blk_mem_gen_0
        port map (
            ena   => '1',
            enb   => '1',
            clka  => wr_clk,
            wea   => wr_en_v,
            addra => wr_addr,
            dina  => wr_data_6,
            clkb  => rd_clk,
            doutb => rd_data_6,
            addrb => rd_addr
            );
end beh;