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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;
entity vnc_serializer is
generic (
video_width : integer := 2
);
port (
clk : in std_logic;
vnc_valid : in std_logic;
vnc_data : in std_logic_vector(video_width -1 downto 0);
vnc_index : in std_logic;
fifo_data : out std_logic_vector(64 downto 0);
fifo_wren : out std_logic);
end vnc_serializer;
architecture Behavioural of vnc_serializer is
--type REGS is array (0 to 7) of std_logic_vector(video_width-1 downto 0);
type REGS is array (0 to 7) of std_logic_vector(7 downto 0);
signal reg : REGS;
signal i : natural := 0;
signal wren : std_logic;
signal next_index : std_logic;
signal index : std_logic;
signal rgb : std_logic_vector(7 downto 0);
begin
rgb(2 downto 0) <= "111" when vnc_data(0)='1' else
"000";
rgb(5 downto 3) <= "111" when vnc_data(1)='1' and vnc_data(3)='1' else
"100" when vnc_data(1)='1' else
"000";
rgb(7 downto 6) <= "11" when vnc_data(2)='1' and vnc_data(3)='1' else
"10" when vnc_data(2)='1' else
"00";
process (clk)
begin
if rising_edge(clk) then
if vnc_valid = '1' then
if vnc_index = '1' then
reg(0)<=rgb;
next_index <= '1';
i <= 1;
wren <= '0';
else
reg(i) <=rgb;
if i /= 7 then
i <= i+1;
wren <= '0';
else
i <= 0;
wren <= '1';
index <= next_index;
next_index <= '0';
end if;
end if;
else
wren <= '0';
end if;
end if;
end process;
g_j : for j in 0 to 7 generate
-- fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j);
-- fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0');
fifo_data(((j*8)+7) downto (j*8)) <= reg(j);
end generate g_j;
fifo_data(64) <= index;
fifo_wren <= wren;
end Behavioural;
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