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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity output_analog is
port
(
clk : in std_logic;
sys_rst_n : in std_logic;
r_in : in std_logic;
g_in : in std_logic;
b_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
blank_in : in std_logic;
r_out : out std_logic;
g_out : out std_logic;
b_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic
);
end output_analog;
architecture beh of output_analog is
signal r_r : std_logic;
signal g_r : std_logic;
signal b_r : std_logic;
signal hsync_r : std_logic;
signal vsync_r : std_logic;
signal blank_r : std_logic;
begin
process (sys_rst_n, clk)
begin
if sys_rst_n = '0' then
r_r <= '0';
g_r <= '0';
b_r <= '0';
hsync_r <= '0';
vsync_r <= '0';
blank_r <= '0';
elsif rising_edge(clk) then
r_r <= r_in;
g_r <= g_in;
b_r <= b_in;
hsync_r <= hsync_in;
vsync_r <= vsync_in;
blank_r <= blank_in;
end if;
end process;
process (sys_rst_n, clk)
begin
if sys_rst_n = '0' then
r_out <= '0';
g_out <= '0';
b_out <= '0';
hsync_out <= '0';
vsync_out <= '0';
elsif rising_edge(clk) then
r_out <= r_r and not blank_r;
g_out <= g_r and not blank_r;
b_out <= b_r and not blank_r;
hsync_out <= hsync_r;
vsync_out <= vsync_r;
end if;
end process;
end beh;
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