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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity edge_det is
port (clk : in std_logic;
sig : in std_logic;
pe : out std_logic;
ne : out std_logic;
e : out std_logic
);
end edge_det;
architecture Behavioral of edge_det is
signal last : std_logic := '0';
begin
process(clk, last, sig)
begin
if rising_edge(clk) then
last <= sig;
end if;
end process;
pe <= '1' when sig = '1' and last = '0' else '0';
ne <= '1' when sig = '0' and last = '1' else '0';
e <= sig xor last;
end Behavioral;
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