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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;
entity clkgen is
port (
sys_rst_n : in std_logic;
clk_in : in std_logic;
i_clk : out std_logic;
o_clk : out std_logic;
o_clk_x2 : out std_logic;
o_clk_phy : out std_logic;
locked : out std_logic
);
end clkgen;
architecture Behavioural of clkgen is
signal clkfbout : std_logic;
signal clk_120m : std_logic;
signal clk_78_642m : std_logic;
signal clk_48m : std_logic;
signal clk_24m : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
begin
clkgen_a : entity work.clkgen_cyclone4_a_impl
port map (
areset => not sys_rst_n,
inclk0 => clk_in,
c0 => clk_78_642m,
locked => open);
i_clk <= clk_78_642m;
clkgen_b : entity work.clkgen_cyclone4_b_impl
port map (
areset => not sys_rst_n,
inclk0 => clk_in,
c0 => clk_120m,
c1 => open,
c2 => clk_48m,
c3 => clk_24m,
locked => pll_locked);
o_clk <= clk_24m;
-- not used in the cyclone design
o_clk_x2 <= clk_48m;
o_clk_phy <= clk_120m;
locked <= pll_locked;
end Behavioural;
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