1 files changed, 73 insertions, 0 deletions
diff --git a/spartan6/hp_lcd_driver/clkgen.vhdl b/spartan6/hp_lcd_driver/clkgen.vhdl
new file mode 100644
index 0000000..5d3c8f2
--- /dev/null
+++ b/spartan6/hp_lcd_driver/clkgen.vhdl
@@ -0,0 +1,73 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clkgen is
+    port (
+		sys_rst_n:in std_logic;
+		clk_in: in std_logic;
+		i_clk:out std_logic;
+		o_clk:out std_logic;
+		o_clk_x2: out std_logic;
+		o_clk_x10: out std_logic;
+		locked: out std_logic
+	);
+end clkgen;
+architecture Behavioural of clkgen is
+
+    signal clkfbout     : std_logic;
+    signal clk_200m     : std_logic;
+    signal clk_80m      : std_logic;
+    signal clk_40m      : std_logic;
+    signal clk_20m      : std_logic;
+    signal pll_locked   : std_logic;
+
+    signal reset	: std_logic;
+begin 
+ 
+    pll : PLL_BASE generic map (
+        CLKIN_PERIOD   => 20.0,
+        CLKFBOUT_MULT  => 8,
+        CLKOUT0_DIVIDE => 2,
+        CLKOUT1_DIVIDE => 5,
+        CLKOUT2_DIVIDE => 10,
+        CLKOUT3_DIVIDE => 20,
+        COMPENSATION   => "INTERNAL")
+        port map (
+            CLKFBOUT => clkfbout,
+            CLKOUT0  => clk_200m,
+            CLKOUT1  => clk_80m,
+            CLKOUT2  => clk_40m,
+            CLKOUT3  => clk_20m,
+            LOCKED   => pll_locked,
+            CLKFBIN  => clkfbout,
+            CLKIN    => clk_in,
+            RST      => reset);
+
+    reset <= (not pll_locked) or (not sys_rst_n);
+
+
+
+    o_clk_buf : BUFG port map (
+        I =>clk_20m,
+        O =>o_clk);
+
+
+    o_clk_x2_buf : BUFG port map (
+        I =>clk_40m,
+        O =>o_clk_x2);
+
+
+    i_clk_buf : BUFG port map (
+        I =>clk_80m,
+        O =>i_clk);
+  
+    o_clk_x10 <= clk_200m;
+
+    locked <= pll_locked;
+
+end Behavioural;