45 files changed, 179686 insertions, 0 deletions
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt
new file mode 100644
index 0000000..24ef7b8
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt
@@ -0,0 +1 @@
+00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 
+\ No newline at end of file
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx
new file mode 100644
index 0000000..83a2e48
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt
new file mode 100644
index 0000000..790cae7
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt
@@ -0,0 +1,5 @@
+PLL_Name	clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1
+PLLJITTER	30
+PLLSPEmax	84
+PLLSPEmin	-53
+
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf
new file mode 100644
index 0000000..a0d0ea9
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="clk_gen" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip
new file mode 100644
index 0000000..ec92e56
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"]
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v
new file mode 100644
index 0000000..07e1850
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v
@@ -0,0 +1,348 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_gen.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module clk_gen (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 1,
+		altpll_component.clk1_phase_shift = "10000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "10000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v
new file mode 100644
index 0000000..c60b06d
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v
@@ -0,0 +1,232 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_gen.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module clk_gen (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "10000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v
new file mode 100644
index 0000000..bad6ce7
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v
@@ -0,0 +1,7 @@
+clk_gen	clk_gen_inst (
+	.areset ( areset_sig ),
+	.inclk0 ( inclk0_sig ),
+	.c0 ( c0_sig ),
+	.c1 ( c1_sig ),
+	.locked ( locked_sig )
+	);
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..a059cd0
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt
@@ -0,0 +1,66 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=1
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=1
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=1
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=1
+CLK1_PHASE_SHIFT=10000
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_USED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_USED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+SELF_RESET_ON_LOSS_LOCK=OFF
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone IV E"
+CBX_AUTO_BLACKBOX=ALL
+areset
+inclk
+inclk
+clk
+clk
+locked
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip
new file mode 100644
index 0000000..d27d36e
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_rd_data.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_rd_data_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_rd_data_bb.v"]
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v
new file mode 100644
index 0000000..7e69a6c
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v
@@ -0,0 +1,156 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths 
+
+// ============================================================
+// File Name: fifo_rd_data.v
+// Megafunction Name(s):
+// 			dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_rd_data (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q);
+
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[7:0]  q;
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	dcfifo_mixed_widths	dcfifo_mixed_widths_component (
+				.data (data),
+				.rdclk (rdclk),
+				.rdreq (rdreq),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.q (sub_wire0),
+				.aclr (1'b0),
+				.rdempty (),
+				.rdfull (),
+				.rdusedw (),
+				.wrempty (),
+				.wrfull (),
+				.wrusedw ());
+	defparam
+		dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
+		dcfifo_mixed_widths_component.lpm_numwords = 512,
+		dcfifo_mixed_widths_component.lpm_showahead = "OFF",
+		dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
+		dcfifo_mixed_widths_component.lpm_width = 16,
+		dcfifo_mixed_widths_component.lpm_widthu = 9,
+		dcfifo_mixed_widths_component.lpm_widthu_r = 10,
+		dcfifo_mixed_widths_component.lpm_width_r = 8,
+		dcfifo_mixed_widths_component.overflow_checking = "ON",
+		dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
+		dcfifo_mixed_widths_component.underflow_checking = "ON",
+		dcfifo_mixed_widths_component.use_eab = "ON",
+		dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v
new file mode 100644
index 0000000..4230405
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v
@@ -0,0 +1,118 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths 
+
+// ============================================================
+// File Name: fifo_rd_data.v
+// Megafunction Name(s):
+// 			dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module fifo_rd_data (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q);
+
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[7:0]  q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v
new file mode 100644
index 0000000..e97cd51
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v
@@ -0,0 +1,8 @@
+fifo_rd_data	fifo_rd_data_inst (
+	.data ( data_sig ),
+	.rdclk ( rdclk_sig ),
+	.rdreq ( rdreq_sig ),
+	.wrclk ( wrclk_sig ),
+	.wrreq ( wrreq_sig ),
+	.q ( q_sig )
+	);
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..bacc0ff
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt
@@ -0,0 +1,23 @@
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_NUMWORDS=512
+LPM_SHOWAHEAD=OFF
+LPM_TYPE=dcfifo_mixed_widths
+LPM_WIDTH=16
+LPM_WIDTHU=9
+LPM_WIDTHU_R=10
+LPM_WIDTH_R=8
+OVERFLOW_CHECKING=ON
+RDSYNC_DELAYPIPE=4
+UNDERFLOW_CHECKING=ON
+USE_EAB=ON
+WRSYNC_DELAYPIPE=4
+DEVICE_FAMILY="Cyclone IV E"
+data
+rdclk
+rdreq
+wrclk
+wrreq
+q
+rdusedw
+wrfull
+wrusedw
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip
new file mode 100644
index 0000000..8ccea8e
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_wr_data.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_wr_data_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_wr_data_bb.v"]
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v
new file mode 100644
index 0000000..1ddb948
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v
@@ -0,0 +1,161 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths 
+
+// ============================================================
+// File Name: fifo_wr_data.v
+// Megafunction Name(s):
+// 			dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_wr_data (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdusedw);
+
+	input	[7:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	[8:0]  rdusedw;
+
+	wire [8:0] sub_wire0;
+	wire [15:0] sub_wire1;
+	wire [8:0] rdusedw = sub_wire0[8:0];
+	wire [15:0] q = sub_wire1[15:0];
+
+	dcfifo_mixed_widths	dcfifo_mixed_widths_component (
+				.data (data),
+				.rdclk (rdclk),
+				.rdreq (rdreq),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.rdusedw (sub_wire0),
+				.q (sub_wire1),
+				.aclr (1'b0),
+				.rdempty (),
+				.rdfull (),
+				.wrempty (),
+				.wrfull (),
+				.wrusedw ());
+	defparam
+		dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
+		dcfifo_mixed_widths_component.lpm_numwords = 1024,
+		dcfifo_mixed_widths_component.lpm_showahead = "OFF",
+		dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
+		dcfifo_mixed_widths_component.lpm_width = 8,
+		dcfifo_mixed_widths_component.lpm_widthu = 10,
+		dcfifo_mixed_widths_component.lpm_widthu_r = 9,
+		dcfifo_mixed_widths_component.lpm_width_r = 16,
+		dcfifo_mixed_widths_component.overflow_checking = "ON",
+		dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
+		dcfifo_mixed_widths_component.underflow_checking = "ON",
+		dcfifo_mixed_widths_component.use_eab = "ON",
+		dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_bb.v TRUE
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v
new file mode 100644
index 0000000..0d15210
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v
@@ -0,0 +1,121 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths 
+
+// ============================================================
+// File Name: fifo_wr_data.v
+// Megafunction Name(s):
+// 			dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module fifo_wr_data (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdusedw);
+
+	input	[7:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	[8:0]  rdusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_bb.v TRUE
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v
new file mode 100644
index 0000000..106098f
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v
@@ -0,0 +1,9 @@
+fifo_wr_data	fifo_wr_data_inst (
+	.data ( data_sig ),
+	.rdclk ( rdclk_sig ),
+	.rdreq ( rdreq_sig ),
+	.wrclk ( wrclk_sig ),
+	.wrreq ( wrreq_sig ),
+	.q ( q_sig ),
+	.rdusedw ( rdusedw_sig )
+	);
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..a6f0d77
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt
@@ -0,0 +1,22 @@
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_NUMWORDS=1024
+LPM_SHOWAHEAD=OFF
+LPM_TYPE=dcfifo_mixed_widths
+LPM_WIDTH=8
+LPM_WIDTHU=10
+LPM_WIDTHU_R=9
+LPM_WIDTH_R=16
+OVERFLOW_CHECKING=ON
+RDSYNC_DELAYPIPE=4
+UNDERFLOW_CHECKING=ON
+USE_EAB=ON
+WRSYNC_DELAYPIPE=4
+DEVICE_FAMILY="Cyclone IV E"
+data
+rdclk
+rdreq
+wrclk
+wrreq
+q
+rdusedw
+wrusedw
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft
new file mode 100644
index 0000000..efdb038
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim (Verilog)"
+set corner_file_list {
+	{{"Slow -8 1.2V 85 Model"} {uart_sd_8_1200mv_85c_slow.vo uart_sd_8_1200mv_85c_v_slow.sdo}}
+	{{"Slow -8 1.2V 0 Model"} {uart_sd_8_1200mv_0c_slow.vo uart_sd_8_1200mv_0c_v_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {uart_sd_min_1200mv_0c_fast.vo uart_sd_min_1200mv_0c_v_fast.sdo}}
+}
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo
new file mode 100644
index 0000000..a6403c2
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo
@@ -0,0 +1,24509 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "06/02/2023 04:03:14"
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module uart_sd (
+	sys_clk,
+	sys_rst_n,
+	rx,
+	sd_miso,
+	sd_clk,
+	sd_cs_n,
+	sd_mosi,
+	tx);
+input 	sys_clk;
+input 	sys_rst_n;
+input 	rx;
+input 	sd_miso;
+output 	sd_clk;
+output 	sd_cs_n;
+output 	sd_mosi;
+output 	tx;
+
+// Design Ports Information
+// sd_clk	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_cs_n	=>  Location: PIN_E7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_mosi	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// tx	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_rst_n	=>  Location: PIN_U20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_clk	=>  Location: PIN_T22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_miso	=>  Location: PIN_E9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// rx	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("uart_sd_v.sdo");
+// synopsys translate_on
+
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ;
+wire \uart_tx_inst|baud_cnt[2]~17_combout ;
+wire \uart_tx_inst|baud_cnt[5]~23_combout ;
+wire \uart_tx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ;
+wire \uart_rx_inst|Add1~4_combout ;
+wire \uart_rx_inst|baud_cnt[4]~21_combout ;
+wire \uart_rx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ;
+wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ;
+wire \data_rw_ctrl_inst|send_data_num[7]~27 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~29 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ;
+wire \data_rw_ctrl_inst|send_data_num[9]~31 ;
+wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ;
+wire \data_rw_ctrl_inst|send_data_num[10]~33 ;
+wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ;
+wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ;
+wire \uart_tx_inst|always0~0_combout ;
+wire \uart_tx_inst|Mux0~1_combout ;
+wire \uart_tx_inst|Mux0~2_combout ;
+wire \uart_tx_inst|Mux0~3_combout ;
+wire \uart_tx_inst|Mux0~4_combout ;
+wire \uart_tx_inst|Mux0~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \uart_tx_inst|work_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \uart_tx_inst|Add1~1_combout ;
+wire \uart_tx_inst|bit_cnt[2]~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ;
+wire \data_rw_ctrl_inst|tx_flag~q ;
+wire \uart_tx_inst|work_en~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ;
+wire \uart_rx_inst|always8~0_combout ;
+wire \uart_rx_inst|rx_reg3~q ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ;
+wire \uart_rx_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ;
+wire \uart_rx_inst|rx_reg2~q ;
+wire \data_rw_ctrl_inst|always3~2_combout ;
+wire \uart_rx_inst|Equal1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ;
+wire \uart_rx_inst|rx_reg1~q ;
+wire \uart_rx_inst|start_nedge~q ;
+wire \uart_rx_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \uart_rx_inst|rx_data[7]~0_combout ;
+wire \uart_rx_inst|rx_reg1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ;
+wire \rx~input_o ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|tx_flag~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ;
+wire \uart_rx_inst|po_data[1]~feeder_combout ;
+wire \uart_rx_inst|rx_data[0]~feeder_combout ;
+wire \uart_rx_inst|po_data[5]~feeder_combout ;
+wire \uart_rx_inst|rx_data[4]~feeder_combout ;
+wire \uart_rx_inst|po_data[6]~feeder_combout ;
+wire \uart_rx_inst|rx_data[5]~feeder_combout ;
+wire \uart_rx_inst|po_data[7]~feeder_combout ;
+wire \uart_rx_inst|rx_data[6]~feeder_combout ;
+wire \uart_rx_inst|po_data[3]~feeder_combout ;
+wire \uart_rx_inst|rx_data[2]~feeder_combout ;
+wire \uart_rx_inst|po_data[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ;
+wire \uart_rx_inst|rx_reg2~feeder_combout ;
+wire \sys_clk~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ;
+wire \sys_rst_n~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ;
+wire \rst_n~0_combout ;
+wire \rst_n~0clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_miso~input_o ;
+wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|init_end~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ;
+wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ;
+wire \data_rw_ctrl_inst|wr_busy_dly~q ;
+wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ;
+wire \data_rw_ctrl_inst|rd_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \uart_rx_inst|Add1~1 ;
+wire \uart_rx_inst|Add1~3 ;
+wire \uart_rx_inst|Add1~5 ;
+wire \uart_rx_inst|Add1~6_combout ;
+wire \uart_rx_inst|bit_cnt~0_combout ;
+wire \uart_rx_inst|Add1~0_combout ;
+wire \uart_rx_inst|bit_cnt~1_combout ;
+wire \uart_rx_inst|Add1~2_combout ;
+wire \uart_rx_inst|always4~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~13_combout ;
+wire \uart_rx_inst|Equal1~0_combout ;
+wire \uart_rx_inst|baud_cnt[5]~23_combout ;
+wire \uart_rx_inst|baud_cnt[2]~17_combout ;
+wire \uart_rx_inst|Equal1~1_combout ;
+wire \uart_rx_inst|Equal1~3_combout ;
+wire \uart_rx_inst|work_en~0_combout ;
+wire \uart_rx_inst|work_en~q ;
+wire \uart_rx_inst|always5~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~14 ;
+wire \uart_rx_inst|baud_cnt[1]~15_combout ;
+wire \uart_rx_inst|baud_cnt[1]~16 ;
+wire \uart_rx_inst|baud_cnt[2]~18 ;
+wire \uart_rx_inst|baud_cnt[3]~19_combout ;
+wire \uart_rx_inst|baud_cnt[3]~20 ;
+wire \uart_rx_inst|baud_cnt[4]~22 ;
+wire \uart_rx_inst|baud_cnt[5]~24 ;
+wire \uart_rx_inst|baud_cnt[6]~25_combout ;
+wire \uart_rx_inst|baud_cnt[6]~26 ;
+wire \uart_rx_inst|baud_cnt[7]~27_combout ;
+wire \uart_rx_inst|baud_cnt[7]~28 ;
+wire \uart_rx_inst|baud_cnt[8]~29_combout ;
+wire \uart_rx_inst|baud_cnt[8]~30 ;
+wire \uart_rx_inst|baud_cnt[9]~31_combout ;
+wire \uart_rx_inst|baud_cnt[9]~32 ;
+wire \uart_rx_inst|baud_cnt[10]~34 ;
+wire \uart_rx_inst|baud_cnt[11]~35_combout ;
+wire \uart_rx_inst|baud_cnt[11]~36 ;
+wire \uart_rx_inst|baud_cnt[12]~37_combout ;
+wire \uart_rx_inst|Equal2~1_combout ;
+wire \uart_rx_inst|Equal2~2_combout ;
+wire \uart_rx_inst|bit_flag~q ;
+wire \uart_rx_inst|always4~1_combout ;
+wire \uart_rx_inst|rx_flag~q ;
+wire \uart_rx_inst|po_flag~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ;
+wire \sd_ctrl_inst|comb~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ;
+wire \sd_ctrl_inst|comb~0_combout ;
+wire \sd_ctrl_inst|comb~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_mosi~0_combout ;
+wire \sd_ctrl_inst|sd_mosi~1_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
+wire \uart_tx_inst|baud_cnt[0]~13_combout ;
+wire \uart_tx_inst|Equal1~0_combout ;
+wire \uart_tx_inst|Equal1~1_combout ;
+wire \uart_tx_inst|baud_cnt[4]~21_combout ;
+wire \uart_tx_inst|Equal1~2_combout ;
+wire \uart_tx_inst|Equal1~3_combout ;
+wire \uart_tx_inst|always1~0_combout ;
+wire \uart_tx_inst|baud_cnt[0]~14 ;
+wire \uart_tx_inst|baud_cnt[1]~15_combout ;
+wire \uart_tx_inst|baud_cnt[1]~16 ;
+wire \uart_tx_inst|baud_cnt[2]~18 ;
+wire \uart_tx_inst|baud_cnt[3]~19_combout ;
+wire \uart_tx_inst|baud_cnt[3]~20 ;
+wire \uart_tx_inst|baud_cnt[4]~22 ;
+wire \uart_tx_inst|baud_cnt[5]~24 ;
+wire \uart_tx_inst|baud_cnt[6]~25_combout ;
+wire \uart_tx_inst|baud_cnt[6]~26 ;
+wire \uart_tx_inst|baud_cnt[7]~27_combout ;
+wire \uart_tx_inst|baud_cnt[7]~28 ;
+wire \uart_tx_inst|baud_cnt[8]~29_combout ;
+wire \uart_tx_inst|baud_cnt[8]~30 ;
+wire \uart_tx_inst|baud_cnt[9]~31_combout ;
+wire \uart_tx_inst|baud_cnt[9]~32 ;
+wire \uart_tx_inst|baud_cnt[10]~34 ;
+wire \uart_tx_inst|baud_cnt[11]~35_combout ;
+wire \uart_tx_inst|baud_cnt[11]~36 ;
+wire \uart_tx_inst|baud_cnt[12]~37_combout ;
+wire \uart_tx_inst|Equal2~0_combout ;
+wire \uart_tx_inst|Equal2~1_combout ;
+wire \uart_tx_inst|bit_flag~q ;
+wire \uart_tx_inst|always3~0_combout ;
+wire \uart_tx_inst|always0~1_combout ;
+wire \uart_tx_inst|bit_cnt[0]~5_combout ;
+wire \uart_tx_inst|bit_cnt[1]~4_combout ;
+wire \uart_tx_inst|Add1~0_combout ;
+wire \uart_tx_inst|bit_cnt[3]~2_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~23 ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ;
+wire \data_rw_ctrl_inst|Equal3~0_combout ;
+wire \data_rw_ctrl_inst|rd_busy_dly~q ;
+wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ;
+wire \data_rw_ctrl_inst|send_data_num[0]~13 ;
+wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ;
+wire \data_rw_ctrl_inst|send_data_num[1]~15 ;
+wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ;
+wire \data_rw_ctrl_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|send_data_num[2]~17 ;
+wire \data_rw_ctrl_inst|send_data_num[3]~19 ;
+wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ;
+wire \data_rw_ctrl_inst|send_data_num[4]~21 ;
+wire \data_rw_ctrl_inst|send_data_num[5]~23 ;
+wire \data_rw_ctrl_inst|send_data_num[6]~25 ;
+wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ;
+wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ;
+wire \data_rw_ctrl_inst|always3~1_combout ;
+wire \data_rw_ctrl_inst|always3~3_combout ;
+wire \data_rw_ctrl_inst|send_data_en~0_combout ;
+wire \data_rw_ctrl_inst|send_data_en~q ;
+wire \data_rw_ctrl_inst|Equal3~1_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~17 ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~19 ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~21 ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ;
+wire \data_rw_ctrl_inst|Equal2~3_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~25 ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~28 ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~30 ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~32 ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~34 ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~36 ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~38 ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~40 ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~42 ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~44 ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~46 ;
+wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ;
+wire \data_rw_ctrl_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ;
+wire \data_rw_ctrl_inst|Equal2~1_combout ;
+wire \data_rw_ctrl_inst|Equal2~2_combout ;
+wire \data_rw_ctrl_inst|Equal2~4_combout ;
+wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ;
+wire \uart_tx_inst|Mux0~0_combout ;
+wire \uart_tx_inst|tx~0_combout ;
+wire \uart_tx_inst|tx~q ;
+wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ;
+wire [12:0] \uart_tx_inst|baud_cnt ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ;
+wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ;
+wire [3:0] \uart_tx_inst|bit_cnt ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ;
+wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ;
+wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ;
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ;
+wire [7:0] \uart_rx_inst|rx_data ;
+wire [7:0] \uart_rx_inst|po_data ;
+wire [3:0] \uart_rx_inst|bit_cnt ;
+wire [12:0] \uart_rx_inst|baud_cnt ;
+wire [11:0] \data_rw_ctrl_inst|send_data_num ;
+wire [15:0] \data_rw_ctrl_inst|cnt_wait ;
+wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ;
+wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ;
+wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ;
+wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ;
+wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ;
+wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ;
+wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ;
+wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ;
+
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ;
+wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4];
+
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16];
+
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+
+// Location: PLL_2
+cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 (
+	.areset(!\sys_rst_n~input_o ),
+	.pfdena(vcc),
+	.fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.phaseupdown(gnd),
+	.phasestep(gnd),
+	.scandata(gnd),
+	.scanclk(gnd),
+	.scanclkena(vcc),
+	.configupdate(gnd),
+	.clkswitch(gnd),
+	.inclk({gnd,\sys_clk~input_o }),
+	.phasecounterselect(3'b000),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.activeclock(),
+	.locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.vcooverrange(),
+	.vcounderrange(),
+	.fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ),
+	.clkbad());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND)))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: M9K_X13_Y13_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(18'b000000000000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y27_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9],
+\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2],
+\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(9'b000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0])
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N13
+dffeas \uart_tx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N7
+dffeas \uart_tx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N23
+dffeas \uart_tx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[2]~17_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16  & VCC))
+// \uart_tx_inst|baud_cnt[2]~18  = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_tx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[5]~23_combout  = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_tx_inst|baud_cnt[5]~24  = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5]))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_tx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[10]~33_combout  = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32  & VCC))
+// \uart_tx_inst|baud_cnt[10]~34  = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_tx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N11
+dffeas \data_rw_ctrl_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[5]~27_combout  = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[5]~28  = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[5]~28 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|Add1~4 (
+// Equation(s):
+// \uart_rx_inst|Add1~4_combout  = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3  $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3  & VCC))
+// \uart_rx_inst|Add1~5  = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 ))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~3 ),
+	.combout(\uart_rx_inst|Add1~4_combout ),
+	.cout(\uart_rx_inst|Add1~5 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N11
+dffeas \uart_rx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N23
+dffeas \uart_rx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N7
+dffeas \data_rw_ctrl_inst|send_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N13
+dffeas \data_rw_ctrl_inst|send_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N17
+dffeas \data_rw_ctrl_inst|send_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N19
+dffeas \data_rw_ctrl_inst|send_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N21
+dffeas \data_rw_ctrl_inst|send_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N23
+dffeas \data_rw_ctrl_inst|send_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[4]~21_combout  = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20  & VCC))
+// \uart_rx_inst|baud_cnt[4]~22  = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_rx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[10]~33_combout  = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32  & VCC))
+// \uart_rx_inst|baud_cnt[10]~34  = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_rx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[3]~18_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[3]~19  = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[2]~17 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[3]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[6]~24_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23  & VCC))
+// \data_rw_ctrl_inst|send_data_num[6]~25  = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 ))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[5]~23 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[6]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[7]~26_combout  = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[7]~27  = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[6]~25 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[7]~27 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[8]~28_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27  & VCC))
+// \data_rw_ctrl_inst|send_data_num[8]~29  = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[7]~27 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[8]~29 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[9]~30_combout  = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[9]~31  = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[8]~29 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[9]~31 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[10]~32_combout  = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31  & VCC))
+// \data_rw_ctrl_inst|send_data_num[10]~33  = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[9]~31 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[10]~33 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[11]~34_combout  = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 )
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|send_data_num[10]~33 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~1_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [14])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [15]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & 
+// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~6_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # 
+// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & 
+// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & 
+// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout  = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout  & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout  = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout  & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N15
+dffeas \uart_tx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneive_lcell_comb \uart_tx_inst|always0~0 (
+// Equation(s):
+// \uart_tx_inst|always0~0_combout  = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F;
+defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N30
+cycloneive_lcell_comb \uart_tx_inst|Mux0~1 (
+// Equation(s):
+// \uart_tx_inst|Mux0~1_combout  = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2;
+defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Mux0~2 (
+// Equation(s):
+// \uart_tx_inst|Mux0~2_combout  = (\uart_tx_inst|Mux0~1_combout  & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout  & 
+// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))
+
+	.dataa(\uart_tx_inst|Mux0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62;
+defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|Mux0~3 (
+// Equation(s):
+// \uart_tx_inst|Mux0~3_combout  = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0;
+defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneive_lcell_comb \uart_tx_inst|Mux0~4 (
+// Equation(s):
+// \uart_tx_inst|Mux0~4_combout  = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000;
+defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneive_lcell_comb \uart_tx_inst|Mux0~5 (
+// Equation(s):
+// \uart_tx_inst|Mux0~5_combout  = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout ))))
+
+	.dataa(\uart_tx_inst|Mux0~3_combout ),
+	.datab(\uart_tx_inst|Mux0~4_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|Mux0~2_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E;
+defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003;
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout  = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout  = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~0_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N17
+dffeas \uart_rx_inst|po_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N19
+dffeas \uart_rx_inst|po_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N21
+dffeas \uart_rx_inst|po_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N15
+dffeas \uart_rx_inst|po_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N9
+dffeas \uart_rx_inst|po_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N27
+dffeas \uart_rx_inst|po_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N13
+dffeas \uart_rx_inst|po_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N31
+dffeas \uart_rx_inst|po_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N21
+dffeas \uart_tx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_tx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneive_lcell_comb \uart_tx_inst|Add1~1 (
+// Equation(s):
+// \uart_tx_inst|Add1~1_combout  = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0;
+defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N14
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[2]~3_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|Add1~1_combout ))))
+
+	.dataa(\uart_tx_inst|Add1~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2;
+defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N1
+dffeas \uart_rx_inst|rx_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N11
+dffeas \uart_rx_inst|rx_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N29
+dffeas \uart_rx_inst|rx_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N23
+dffeas \uart_rx_inst|rx_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N27
+dffeas \uart_rx_inst|rx_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[7]~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N25
+dffeas \uart_rx_inst|rx_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N3
+dffeas \uart_rx_inst|rx_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N5
+dffeas \uart_rx_inst|rx_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N13
+dffeas \data_rw_ctrl_inst|tx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|tx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|tx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|work_en~0 (
+// Equation(s):
+// \uart_tx_inst|work_en~0_combout  = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q  & !\uart_tx_inst|always0~1_combout ))
+
+	.dataa(\data_rw_ctrl_inst|tx_flag~q ),
+	.datab(gnd),
+	.datac(\uart_tx_inst|work_en~q ),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N27
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [2])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & \sd_ctrl_inst|sd_init_inst|miso_dly~q )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N13
+dffeas \uart_rx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|always8~0 (
+// Equation(s):
+// \uart_rx_inst|always8~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|always4~0_combout  $ (!\uart_rx_inst|bit_cnt [3])))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282;
+defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N31
+dffeas \uart_rx_inst|rx_reg3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_reg2~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg3 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Equal2~0 (
+// Equation(s):
+// \uart_rx_inst|Equal2~0_combout  = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N1
+dffeas \uart_rx_inst|rx_reg2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~2_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [8]),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(\data_rw_ctrl_inst|send_data_num [11]),
+	.datad(\data_rw_ctrl_inst|send_data_num [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002;
+defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N30
+cycloneive_lcell_comb \uart_rx_inst|Equal1~2 (
+// Equation(s):
+// \uart_rx_inst|Equal1~2_combout  = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N3
+dffeas \uart_rx_inst|rx_reg1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg1~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg1 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N7
+dffeas \uart_rx_inst|start_nedge (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|start_nedge~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true";
+defparam \uart_rx_inst|start_nedge .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|always3~0 (
+// Equation(s):
+// \uart_rx_inst|always3~0_combout  = (!\uart_rx_inst|rx_reg3~q  & \uart_rx_inst|rx_reg2~q )
+
+	.dataa(\uart_rx_inst|rx_reg3~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg2~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050;
+defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 (
+// Equation(s):
+// \uart_rx_inst|rx_data[7]~0_combout  = !\uart_rx_inst|rx_reg3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg3~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F;
+defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 (
+// Equation(s):
+// \uart_rx_inst|rx_reg1~0_combout  = !\rx~input_o 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\rx~input_o ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF;
+defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneive_io_ibuf \rx~input (
+	.i(rx),
+	.ibar(gnd),
+	.o(\rx~input_o ));
+// synopsys translate_off
+defparam \rx~input .bus_hold = "false";
+defparam \rx~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|tx_flag~feeder_combout  = \data_rw_ctrl_inst|rd_fifo_rd_en~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N16
+cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[1]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[0]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N18
+cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[5]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N4
+cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[4]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N20
+cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[6]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N10
+cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[5]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N8
+cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[7]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N28
+cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[6]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N26
+cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[3]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N22
+cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[2]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N12
+cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[0]~feeder_combout  = \uart_rx_inst|rx_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N0
+cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_reg2~feeder_combout  = \uart_rx_inst|rx_reg1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_reg1~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOOBUF_X5_Y29_N23
+cycloneive_io_obuf \sd_clk~output (
+	.i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_clk),
+	.obar());
+// synopsys translate_off
+defparam \sd_clk~output .bus_hold = "false";
+defparam \sd_clk~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y29_N23
+cycloneive_io_obuf \sd_cs_n~output (
+	.i(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_cs_n),
+	.obar());
+// synopsys translate_off
+defparam \sd_cs_n~output .bus_hold = "false";
+defparam \sd_cs_n~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X1_Y29_N9
+cycloneive_io_obuf \sd_mosi~output (
+	.i(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_mosi),
+	.obar());
+// synopsys translate_off
+defparam \sd_mosi~output .bus_hold = "false";
+defparam \sd_mosi~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N16
+cycloneive_io_obuf \tx~output (
+	.i(!\uart_tx_inst|tx~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(tx),
+	.obar());
+// synopsys translate_off
+defparam \tx~output .bus_hold = "false";
+defparam \tx~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N22
+cycloneive_io_ibuf \sys_clk~input (
+	.i(sys_clk),
+	.ibar(gnd),
+	.o(\sys_clk~input_o ));
+// synopsys translate_off
+defparam \sys_clk~input .bus_hold = "false";
+defparam \sys_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y4_N1
+cycloneive_io_ibuf \sys_rst_n~input (
+	.i(sys_rst_n),
+	.ibar(gnd),
+	.o(\sys_rst_n~input_o ));
+// synopsys translate_off
+defparam \sys_rst_n~input .bus_hold = "false";
+defparam \sys_rst_n~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N0
+cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder (
+// Equation(s):
+// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout  = VCC
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y1_N1
+dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.asdata(vcc),
+	.clrn(\sys_rst_n~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N26
+cycloneive_lcell_comb \rst_n~0 (
+// Equation(s):
+// \rst_n~0_combout  = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )
+
+	.dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.datab(\sys_rst_n~input_o ),
+	.datac(gnd),
+	.datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.cin(gnd),
+	.combout(\rst_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \rst_n~0 .lut_mask = 16'h77FF;
+defparam \rst_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G16
+cycloneive_clkctrl \rst_n~0clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\rst_n~0_combout }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\rst_n~0clkctrl_outclk ));
+// synopsys translate_off
+defparam \rst_n~0clkctrl .clock_type = "global clock";
+defparam \rst_n~0clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X11_Y29_N29
+cycloneive_io_ibuf \sd_miso~input (
+	.i(sd_miso),
+	.ibar(gnd),
+	.o(\sd_miso~input_o ));
+// synopsys translate_off
+defparam \sd_miso~input .bus_hold = "false";
+defparam \sd_miso~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|miso_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_miso~input_o ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout  & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (((\sd_ctrl_inst|sd_read_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N3
+dffeas \sd_ctrl_inst|sd_read_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & \sd_ctrl_inst|sd_read_inst|ack_en~q ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N19
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout  & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  = (\sd_ctrl_inst|sd_init_inst|ack_en~q  & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout  = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [11]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [12]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [13]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [14]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [15]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [17]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [18]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [19]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [29]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [30]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [32]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [33]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [36]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [37]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N27
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2;
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N9
+dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0;
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr18~combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout  & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout  = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout  & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|init_end (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout  = (\data_rw_ctrl_inst|rd_en~q  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))
+
+	.dataa(\data_rw_ctrl_inst|rd_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout  & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Add3~0_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0;
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [12])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N29
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [13])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [14])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [9])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [10])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [7])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N3
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout  = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout  & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [4])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N1
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~3_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~4_combout  = (\sd_ctrl_inst|sd_read_inst|always3~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~4_combout  & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & 
+// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout  & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout 
+//  & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N3
+dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|miso_dly~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (((\sd_ctrl_inst|sd_write_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q  & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N23
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N19
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N25
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N31
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N21
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N27
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N1
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) 
+// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~2_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~1_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit 
+// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~3_combout  = (\sd_ctrl_inst|sd_write_inst|always4~1_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N17
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N27
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N9
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N31
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N13
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N25
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N15
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N5
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N19
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1])))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout  = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout  & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q )))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA;
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout  = (\sd_ctrl_inst|comb~2_combout  & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout  = \sd_ctrl_inst|sd_write_inst|state.IDLE~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N19
+dffeas \data_rw_ctrl_inst|wr_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_fall~0_combout  = (\data_rw_ctrl_inst|wr_busy_dly~q  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC;
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N11
+dffeas \data_rw_ctrl_inst|rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout  = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230;
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) 
+// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout  = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F;
+defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & (((\sd_ctrl_inst|sd_init_inst|mosi~q  & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~1_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout )))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N1
+dffeas \sd_ctrl_inst|sd_read_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Add1~0 (
+// Equation(s):
+// \uart_rx_inst|Add1~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] & VCC))
+// \uart_rx_inst|Add1~1  = CARRY((\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [0]))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Add1~0_combout ),
+	.cout(\uart_rx_inst|Add1~1 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Add1~2 (
+// Equation(s):
+// \uart_rx_inst|Add1~2_combout  = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND)))
+// \uart_rx_inst|Add1~3  = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~1 ),
+	.combout(\uart_rx_inst|Add1~2_combout ),
+	.cout(\uart_rx_inst|Add1~3 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|Add1~6 (
+// Equation(s):
+// \uart_rx_inst|Add1~6_combout  = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|Add1~5 ),
+	.combout(\uart_rx_inst|Add1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C;
+defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~0_combout  = (\uart_rx_inst|Add1~6_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|Add1~6_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC;
+defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N5
+dffeas \uart_rx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~1_combout  = (\uart_rx_inst|Add1~0_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(\uart_rx_inst|Add1~0_combout ),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0;
+defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N25
+dffeas \uart_rx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N11
+dffeas \uart_rx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|always4~0 (
+// Equation(s):
+// \uart_rx_inst|always4~0_combout  = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(\uart_rx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011;
+defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[0]~13_combout  = (\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] & VCC))
+// \uart_rx_inst|baud_cnt[0]~14  = CARRY((\uart_rx_inst|work_en~q  & \uart_rx_inst|baud_cnt [0]))
+
+	.dataa(\uart_rx_inst|work_en~q ),
+	.datab(\uart_rx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_rx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|Equal1~0 (
+// Equation(s):
+// \uart_rx_inst|Equal1~0_combout  = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0])))
+
+	.dataa(\uart_rx_inst|baud_cnt [8]),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(\uart_rx_inst|baud_cnt [1]),
+	.datad(\uart_rx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000;
+defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[5]~23_combout  = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_rx_inst|baud_cnt[5]~24  = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5]))
+
+	.dataa(\uart_rx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_rx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N13
+dffeas \uart_rx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[2]~17_combout  = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16  & VCC))
+// \uart_rx_inst|baud_cnt[2]~18  = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_rx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N7
+dffeas \uart_rx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Equal1~1 (
+// Equation(s):
+// \uart_rx_inst|Equal1~1_combout  = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|Equal1~3 (
+// Equation(s):
+// \uart_rx_inst|Equal1~3_combout  = (\uart_rx_inst|Equal1~2_combout  & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal1~2_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000;
+defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|work_en~0 (
+// Equation(s):
+// \uart_rx_inst|work_en~0_combout  = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q  & !\uart_rx_inst|always4~1_combout ))
+
+	.dataa(\uart_rx_inst|start_nedge~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|work_en~q ),
+	.datad(\uart_rx_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N17
+dffeas \uart_rx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_rx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|always5~0 (
+// Equation(s):
+// \uart_rx_inst|always5~0_combout  = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|Equal1~3_combout ),
+	.datac(gnd),
+	.datad(\uart_rx_inst|work_en~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF;
+defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N3
+dffeas \uart_rx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[1]~15_combout  = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_rx_inst|baud_cnt[1]~16  = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_rx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N5
+dffeas \uart_rx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[3]~19_combout  = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_rx_inst|baud_cnt[3]~20  = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_rx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N9
+dffeas \uart_rx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[6]~25_combout  = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24  & VCC))
+// \uart_rx_inst|baud_cnt[6]~26  = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_rx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N15
+dffeas \uart_rx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[7]~27_combout  = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_rx_inst|baud_cnt[7]~28  = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_rx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N17
+dffeas \uart_rx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[8]~29_combout  = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28  & VCC))
+// \uart_rx_inst|baud_cnt[8]~30  = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_rx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N19
+dffeas \uart_rx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[9]~31_combout  = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_rx_inst|baud_cnt[9]~32  = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_rx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N21
+dffeas \uart_rx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[11]~35_combout  = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_rx_inst|baud_cnt[11]~36  = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_rx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N25
+dffeas \uart_rx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[12]~37_combout  = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_rx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N27
+dffeas \uart_rx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|Equal2~1 (
+// Equation(s):
+// \uart_rx_inst|Equal2~1_combout  = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|Equal2~2 (
+// Equation(s):
+// \uart_rx_inst|Equal2~2_combout  = (\uart_rx_inst|Equal2~0_combout  & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal2~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal2~0_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000;
+defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N23
+dffeas \uart_rx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Equal2~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|always4~1 (
+// Equation(s):
+// \uart_rx_inst|always4~1_combout  = (\uart_rx_inst|always4~0_combout  & (\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_flag~q ),
+	.datad(\uart_rx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000;
+defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N1
+dffeas \uart_rx_inst|rx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always4~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N1
+dffeas \uart_rx_inst|po_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_flag~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\uart_rx_inst|po_flag~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datac(\uart_rx_inst|po_flag~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q  $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & 
+// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N4
+cycloneive_lcell_comb \sd_ctrl_inst|comb~1 (
+// Equation(s):
+// \sd_ctrl_inst|comb~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N0
+cycloneive_lcell_comb \sd_ctrl_inst|comb~0 (
+// Equation(s):
+// \sd_ctrl_inst|comb~0_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N2
+cycloneive_lcell_comb \sd_ctrl_inst|comb~2 (
+// Equation(s):
+// \sd_ctrl_inst|comb~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  & 
+// (\sd_ctrl_inst|comb~1_combout  & \sd_ctrl_inst|comb~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.datac(\sd_ctrl_inst|comb~1_combout ),
+	.datad(\sd_ctrl_inst|comb~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & (((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & 
+// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|comb~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~2_combout  = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~3_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~4_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~5_combout  = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~8_combout  = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout  & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout  & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X11_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|mosi~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & (!\sd_ctrl_inst|sd_init_inst|mosi~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05;
+defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G8
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N2
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[0]~13_combout  = (\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] & VCC))
+// \uart_tx_inst|baud_cnt[0]~14  = CARRY((\uart_tx_inst|work_en~q  & \uart_tx_inst|baud_cnt [0]))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_tx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N0
+cycloneive_lcell_comb \uart_tx_inst|Equal1~0 (
+// Equation(s):
+// \uart_tx_inst|Equal1~0_combout  = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0])))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(\uart_tx_inst|baud_cnt [3]),
+	.datad(\uart_tx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100;
+defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|Equal1~1 (
+// Equation(s):
+// \uart_tx_inst|Equal1~1_combout  = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout  & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9])))
+
+	.dataa(\uart_tx_inst|baud_cnt [8]),
+	.datab(\uart_tx_inst|Equal1~0_combout ),
+	.datac(\uart_tx_inst|baud_cnt [11]),
+	.datad(\uart_tx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004;
+defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[4]~21_combout  = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20  & VCC))
+// \uart_tx_inst|baud_cnt[4]~22  = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_tx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N11
+dffeas \uart_tx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N30
+cycloneive_lcell_comb \uart_tx_inst|Equal1~2 (
+// Equation(s):
+// \uart_tx_inst|Equal1~2_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Equal1~3 (
+// Equation(s):
+// \uart_tx_inst|Equal1~3_combout  = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12])
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(\uart_tx_inst|baud_cnt [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0;
+defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|always1~0 (
+// Equation(s):
+// \uart_tx_inst|always1~0_combout  = ((\uart_tx_inst|Equal1~1_combout  & (\uart_tx_inst|Equal1~2_combout  & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|Equal1~1_combout ),
+	.datac(\uart_tx_inst|Equal1~2_combout ),
+	.datad(\uart_tx_inst|Equal1~3_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555;
+defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N3
+dffeas \uart_tx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[1]~15_combout  = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_tx_inst|baud_cnt[1]~16  = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_tx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N5
+dffeas \uart_tx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[3]~19_combout  = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_tx_inst|baud_cnt[3]~20  = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_tx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N9
+dffeas \uart_tx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[6]~25_combout  = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24  & VCC))
+// \uart_tx_inst|baud_cnt[6]~26  = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_tx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N15
+dffeas \uart_tx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[7]~27_combout  = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_tx_inst|baud_cnt[7]~28  = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_tx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N17
+dffeas \uart_tx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[8]~29_combout  = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28  & VCC))
+// \uart_tx_inst|baud_cnt[8]~30  = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_tx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N19
+dffeas \uart_tx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[9]~31_combout  = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_tx_inst|baud_cnt[9]~32  = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_tx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N21
+dffeas \uart_tx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[11]~35_combout  = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_tx_inst|baud_cnt[11]~36  = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_tx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N25
+dffeas \uart_tx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N26
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[12]~37_combout  = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_tx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_tx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N27
+dffeas \uart_tx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N28
+cycloneive_lcell_comb \uart_tx_inst|Equal2~0 (
+// Equation(s):
+// \uart_tx_inst|Equal2~0_combout  = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Equal2~1 (
+// Equation(s):
+// \uart_tx_inst|Equal2~1_combout  = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout  & \uart_tx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(\uart_tx_inst|baud_cnt [12]),
+	.datac(\uart_tx_inst|Equal2~0_combout ),
+	.datad(\uart_tx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N25
+dffeas \uart_tx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|Equal2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N18
+cycloneive_lcell_comb \uart_tx_inst|always3~0 (
+// Equation(s):
+// \uart_tx_inst|always3~0_combout  = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_tx_inst|bit_flag~q ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF;
+defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneive_lcell_comb \uart_tx_inst|always0~1 (
+// Equation(s):
+// \uart_tx_inst|always0~1_combout  = (\uart_tx_inst|always0~0_combout  & (\uart_tx_inst|bit_flag~q  & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3])))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[0]~5_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q  & \uart_tx_inst|bit_flag~q )))))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078;
+defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N5
+dffeas \uart_tx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[1]~4_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [1]),
+	.datad(\uart_tx_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014;
+defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N1
+dffeas \uart_tx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Add1~0 (
+// Equation(s):
+// \uart_tx_inst|Add1~0_combout  = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))))
+
+	.dataa(\uart_tx_inst|bit_cnt [2]),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC;
+defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[3]~2_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|Add1~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [3]),
+	.datad(\uart_tx_inst|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140;
+defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N3
+dffeas \uart_tx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[0]~16_combout  = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC)
+// \data_rw_ctrl_inst|cnt_wait[0]~17  = CARRY(\data_rw_ctrl_inst|cnt_wait [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[0]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[3]~22_combout  = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[3]~23  = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[3]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[4]~24_combout  = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[4]~25  = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[4]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N9
+dffeas \data_rw_ctrl_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~0_combout  = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5])
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5;
+defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N15
+dffeas \data_rw_ctrl_inst|rd_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[0]~12_combout  = \data_rw_ctrl_inst|send_data_num [0] $ (VCC)
+// \data_rw_ctrl_inst|send_data_num[0]~13  = CARRY(\data_rw_ctrl_inst|send_data_num [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[0]~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N1
+dffeas \data_rw_ctrl_inst|send_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[1]~14_combout  = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[1]~15  = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[0]~13 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[1]~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N3
+dffeas \data_rw_ctrl_inst|send_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[2]~16_combout  = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15  & VCC))
+// \data_rw_ctrl_inst|send_data_num[2]~17  = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[1]~15 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[2]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N5
+dffeas \data_rw_ctrl_inst|send_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~0_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(\data_rw_ctrl_inst|send_data_num [2]),
+	.datad(\data_rw_ctrl_inst|send_data_num [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[4]~20_combout  = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19  & VCC))
+// \data_rw_ctrl_inst|send_data_num[4]~21  = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[3]~19 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[4]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N9
+dffeas \data_rw_ctrl_inst|send_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[5]~22_combout  = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[5]~23  = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[4]~21 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[5]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N15
+dffeas \data_rw_ctrl_inst|send_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N11
+dffeas \data_rw_ctrl_inst|send_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~1_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(\data_rw_ctrl_inst|send_data_num [4]),
+	.datad(\data_rw_ctrl_inst|send_data_num [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~3_combout  = (\data_rw_ctrl_inst|always3~2_combout  & (\data_rw_ctrl_inst|always3~0_combout  & (\data_rw_ctrl_inst|always3~1_combout  & \data_rw_ctrl_inst|Equal2~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|always3~2_combout ),
+	.datab(\data_rw_ctrl_inst|always3~0_combout ),
+	.datac(\data_rw_ctrl_inst|always3~1_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_en~0_combout  = (!\data_rw_ctrl_inst|always3~3_combout  & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & \data_rw_ctrl_inst|rd_busy_dly~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datab(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4;
+defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N23
+dffeas \data_rw_ctrl_inst|send_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~1_combout  = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~26_combout  = ((\data_rw_ctrl_inst|Equal2~2_combout  & (!\data_rw_ctrl_inst|Equal3~0_combout  & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q )
+
+	.dataa(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.datab(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N1
+dffeas \data_rw_ctrl_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[1]~18_combout  = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[1]~19  = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[1]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N3
+dffeas \data_rw_ctrl_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[2]~20_combout  = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[2]~21  = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[2]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N5
+dffeas \data_rw_ctrl_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N7
+dffeas \data_rw_ctrl_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~3_combout  = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[6]~29_combout  = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[6]~30  = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 ))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[6]~30 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[7]~31_combout  = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[7]~32  = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[7]~32 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N15
+dffeas \data_rw_ctrl_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[8]~33_combout  = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[8]~34  = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[8]~34 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N17
+dffeas \data_rw_ctrl_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[9]~35_combout  = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[9]~36  = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[9]~36 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N19
+dffeas \data_rw_ctrl_inst|cnt_wait[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[10]~37_combout  = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[10]~38  = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[10]~38 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N21
+dffeas \data_rw_ctrl_inst|cnt_wait[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[11]~39_combout  = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[11]~40  = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[11]~40 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[12]~41_combout  = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[12]~42  = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[12]~42 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N25
+dffeas \data_rw_ctrl_inst|cnt_wait[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~43_combout  = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[13]~44  = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[13]~44 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[14]~45_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[14]~46  = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[14]~46 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N29
+dffeas \data_rw_ctrl_inst|cnt_wait[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[15]~47_combout  = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 )
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N31
+dffeas \data_rw_ctrl_inst|cnt_wait[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N13
+dffeas \data_rw_ctrl_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~0_combout  = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N27
+dffeas \data_rw_ctrl_inst|cnt_wait[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N23
+dffeas \data_rw_ctrl_inst|cnt_wait[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~1_combout  = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [11]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~2_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout  & \data_rw_ctrl_inst|Equal2~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datac(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~4_combout  = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout  & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000;
+defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N7
+dffeas \data_rw_ctrl_inst|rd_fifo_rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\data_rw_ctrl_inst|rd_fifo_rd_en~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q  $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (\data_rw_ctrl_inst|rd_fifo_rd_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout  = (\sd_miso~input_o  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|Mux0~0 (
+// Equation(s):
+// \uart_tx_inst|Mux0~0_combout  = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout )))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4;
+defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N8
+cycloneive_lcell_comb \uart_tx_inst|tx~0 (
+// Equation(s):
+// \uart_tx_inst|tx~0_combout  = (\uart_tx_inst|bit_flag~q  & (!\uart_tx_inst|Mux0~5_combout  & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q  & (((\uart_tx_inst|tx~q ))))
+
+	.dataa(\uart_tx_inst|Mux0~5_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|tx~q ),
+	.datad(\uart_tx_inst|Mux0~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|tx~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074;
+defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N9
+dffeas \uart_tx_inst|tx (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|tx~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|tx~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|tx .is_wysiwyg = "true";
+defparam \uart_tx_inst|tx .power_up = "low";
+// synopsys translate_on
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo
new file mode 100644
index 0000000..6b66e8b
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo
@@ -0,0 +1,24509 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "06/02/2023 04:03:14"
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module uart_sd (
+	sys_clk,
+	sys_rst_n,
+	rx,
+	sd_miso,
+	sd_clk,
+	sd_cs_n,
+	sd_mosi,
+	tx);
+input 	sys_clk;
+input 	sys_rst_n;
+input 	rx;
+input 	sd_miso;
+output 	sd_clk;
+output 	sd_cs_n;
+output 	sd_mosi;
+output 	tx;
+
+// Design Ports Information
+// sd_clk	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_cs_n	=>  Location: PIN_E7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_mosi	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// tx	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_rst_n	=>  Location: PIN_U20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_clk	=>  Location: PIN_T22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_miso	=>  Location: PIN_E9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// rx	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("uart_sd_8_1200mv_0c_v_slow.sdo");
+// synopsys translate_on
+
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ;
+wire \uart_tx_inst|baud_cnt[2]~17_combout ;
+wire \uart_tx_inst|baud_cnt[5]~23_combout ;
+wire \uart_tx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ;
+wire \uart_rx_inst|Add1~4_combout ;
+wire \uart_rx_inst|baud_cnt[4]~21_combout ;
+wire \uart_rx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ;
+wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ;
+wire \data_rw_ctrl_inst|send_data_num[7]~27 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~29 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ;
+wire \data_rw_ctrl_inst|send_data_num[9]~31 ;
+wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ;
+wire \data_rw_ctrl_inst|send_data_num[10]~33 ;
+wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ;
+wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ;
+wire \uart_tx_inst|always0~0_combout ;
+wire \uart_tx_inst|Mux0~1_combout ;
+wire \uart_tx_inst|Mux0~2_combout ;
+wire \uart_tx_inst|Mux0~3_combout ;
+wire \uart_tx_inst|Mux0~4_combout ;
+wire \uart_tx_inst|Mux0~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \uart_tx_inst|work_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \uart_tx_inst|Add1~1_combout ;
+wire \uart_tx_inst|bit_cnt[2]~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ;
+wire \data_rw_ctrl_inst|tx_flag~q ;
+wire \uart_tx_inst|work_en~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ;
+wire \uart_rx_inst|always8~0_combout ;
+wire \uart_rx_inst|rx_reg3~q ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ;
+wire \uart_rx_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ;
+wire \uart_rx_inst|rx_reg2~q ;
+wire \data_rw_ctrl_inst|always3~2_combout ;
+wire \uart_rx_inst|Equal1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ;
+wire \uart_rx_inst|rx_reg1~q ;
+wire \uart_rx_inst|start_nedge~q ;
+wire \uart_rx_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \uart_rx_inst|rx_data[7]~0_combout ;
+wire \uart_rx_inst|rx_reg1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ;
+wire \rx~input_o ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|tx_flag~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ;
+wire \uart_rx_inst|po_data[1]~feeder_combout ;
+wire \uart_rx_inst|rx_data[0]~feeder_combout ;
+wire \uart_rx_inst|po_data[5]~feeder_combout ;
+wire \uart_rx_inst|rx_data[4]~feeder_combout ;
+wire \uart_rx_inst|po_data[6]~feeder_combout ;
+wire \uart_rx_inst|rx_data[5]~feeder_combout ;
+wire \uart_rx_inst|po_data[7]~feeder_combout ;
+wire \uart_rx_inst|rx_data[6]~feeder_combout ;
+wire \uart_rx_inst|po_data[3]~feeder_combout ;
+wire \uart_rx_inst|rx_data[2]~feeder_combout ;
+wire \uart_rx_inst|po_data[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ;
+wire \uart_rx_inst|rx_reg2~feeder_combout ;
+wire \sys_clk~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ;
+wire \sys_rst_n~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ;
+wire \rst_n~0_combout ;
+wire \rst_n~0clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_miso~input_o ;
+wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|init_end~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ;
+wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ;
+wire \data_rw_ctrl_inst|wr_busy_dly~q ;
+wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ;
+wire \data_rw_ctrl_inst|rd_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \uart_rx_inst|Add1~1 ;
+wire \uart_rx_inst|Add1~3 ;
+wire \uart_rx_inst|Add1~5 ;
+wire \uart_rx_inst|Add1~6_combout ;
+wire \uart_rx_inst|bit_cnt~0_combout ;
+wire \uart_rx_inst|Add1~0_combout ;
+wire \uart_rx_inst|bit_cnt~1_combout ;
+wire \uart_rx_inst|Add1~2_combout ;
+wire \uart_rx_inst|always4~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~13_combout ;
+wire \uart_rx_inst|Equal1~0_combout ;
+wire \uart_rx_inst|baud_cnt[5]~23_combout ;
+wire \uart_rx_inst|baud_cnt[2]~17_combout ;
+wire \uart_rx_inst|Equal1~1_combout ;
+wire \uart_rx_inst|Equal1~3_combout ;
+wire \uart_rx_inst|work_en~0_combout ;
+wire \uart_rx_inst|work_en~q ;
+wire \uart_rx_inst|always5~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~14 ;
+wire \uart_rx_inst|baud_cnt[1]~15_combout ;
+wire \uart_rx_inst|baud_cnt[1]~16 ;
+wire \uart_rx_inst|baud_cnt[2]~18 ;
+wire \uart_rx_inst|baud_cnt[3]~19_combout ;
+wire \uart_rx_inst|baud_cnt[3]~20 ;
+wire \uart_rx_inst|baud_cnt[4]~22 ;
+wire \uart_rx_inst|baud_cnt[5]~24 ;
+wire \uart_rx_inst|baud_cnt[6]~25_combout ;
+wire \uart_rx_inst|baud_cnt[6]~26 ;
+wire \uart_rx_inst|baud_cnt[7]~27_combout ;
+wire \uart_rx_inst|baud_cnt[7]~28 ;
+wire \uart_rx_inst|baud_cnt[8]~29_combout ;
+wire \uart_rx_inst|baud_cnt[8]~30 ;
+wire \uart_rx_inst|baud_cnt[9]~31_combout ;
+wire \uart_rx_inst|baud_cnt[9]~32 ;
+wire \uart_rx_inst|baud_cnt[10]~34 ;
+wire \uart_rx_inst|baud_cnt[11]~35_combout ;
+wire \uart_rx_inst|baud_cnt[11]~36 ;
+wire \uart_rx_inst|baud_cnt[12]~37_combout ;
+wire \uart_rx_inst|Equal2~1_combout ;
+wire \uart_rx_inst|Equal2~2_combout ;
+wire \uart_rx_inst|bit_flag~q ;
+wire \uart_rx_inst|always4~1_combout ;
+wire \uart_rx_inst|rx_flag~q ;
+wire \uart_rx_inst|po_flag~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ;
+wire \sd_ctrl_inst|comb~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ;
+wire \sd_ctrl_inst|comb~0_combout ;
+wire \sd_ctrl_inst|comb~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_mosi~0_combout ;
+wire \sd_ctrl_inst|sd_mosi~1_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
+wire \uart_tx_inst|baud_cnt[0]~13_combout ;
+wire \uart_tx_inst|Equal1~0_combout ;
+wire \uart_tx_inst|Equal1~1_combout ;
+wire \uart_tx_inst|baud_cnt[4]~21_combout ;
+wire \uart_tx_inst|Equal1~2_combout ;
+wire \uart_tx_inst|Equal1~3_combout ;
+wire \uart_tx_inst|always1~0_combout ;
+wire \uart_tx_inst|baud_cnt[0]~14 ;
+wire \uart_tx_inst|baud_cnt[1]~15_combout ;
+wire \uart_tx_inst|baud_cnt[1]~16 ;
+wire \uart_tx_inst|baud_cnt[2]~18 ;
+wire \uart_tx_inst|baud_cnt[3]~19_combout ;
+wire \uart_tx_inst|baud_cnt[3]~20 ;
+wire \uart_tx_inst|baud_cnt[4]~22 ;
+wire \uart_tx_inst|baud_cnt[5]~24 ;
+wire \uart_tx_inst|baud_cnt[6]~25_combout ;
+wire \uart_tx_inst|baud_cnt[6]~26 ;
+wire \uart_tx_inst|baud_cnt[7]~27_combout ;
+wire \uart_tx_inst|baud_cnt[7]~28 ;
+wire \uart_tx_inst|baud_cnt[8]~29_combout ;
+wire \uart_tx_inst|baud_cnt[8]~30 ;
+wire \uart_tx_inst|baud_cnt[9]~31_combout ;
+wire \uart_tx_inst|baud_cnt[9]~32 ;
+wire \uart_tx_inst|baud_cnt[10]~34 ;
+wire \uart_tx_inst|baud_cnt[11]~35_combout ;
+wire \uart_tx_inst|baud_cnt[11]~36 ;
+wire \uart_tx_inst|baud_cnt[12]~37_combout ;
+wire \uart_tx_inst|Equal2~0_combout ;
+wire \uart_tx_inst|Equal2~1_combout ;
+wire \uart_tx_inst|bit_flag~q ;
+wire \uart_tx_inst|always3~0_combout ;
+wire \uart_tx_inst|always0~1_combout ;
+wire \uart_tx_inst|bit_cnt[0]~5_combout ;
+wire \uart_tx_inst|bit_cnt[1]~4_combout ;
+wire \uart_tx_inst|Add1~0_combout ;
+wire \uart_tx_inst|bit_cnt[3]~2_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~23 ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ;
+wire \data_rw_ctrl_inst|Equal3~0_combout ;
+wire \data_rw_ctrl_inst|rd_busy_dly~q ;
+wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ;
+wire \data_rw_ctrl_inst|send_data_num[0]~13 ;
+wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ;
+wire \data_rw_ctrl_inst|send_data_num[1]~15 ;
+wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ;
+wire \data_rw_ctrl_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|send_data_num[2]~17 ;
+wire \data_rw_ctrl_inst|send_data_num[3]~19 ;
+wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ;
+wire \data_rw_ctrl_inst|send_data_num[4]~21 ;
+wire \data_rw_ctrl_inst|send_data_num[5]~23 ;
+wire \data_rw_ctrl_inst|send_data_num[6]~25 ;
+wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ;
+wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ;
+wire \data_rw_ctrl_inst|always3~1_combout ;
+wire \data_rw_ctrl_inst|always3~3_combout ;
+wire \data_rw_ctrl_inst|send_data_en~0_combout ;
+wire \data_rw_ctrl_inst|send_data_en~q ;
+wire \data_rw_ctrl_inst|Equal3~1_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~17 ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~19 ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~21 ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ;
+wire \data_rw_ctrl_inst|Equal2~3_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~25 ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~28 ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~30 ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~32 ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~34 ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~36 ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~38 ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~40 ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~42 ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~44 ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~46 ;
+wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ;
+wire \data_rw_ctrl_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ;
+wire \data_rw_ctrl_inst|Equal2~1_combout ;
+wire \data_rw_ctrl_inst|Equal2~2_combout ;
+wire \data_rw_ctrl_inst|Equal2~4_combout ;
+wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ;
+wire \uart_tx_inst|Mux0~0_combout ;
+wire \uart_tx_inst|tx~0_combout ;
+wire \uart_tx_inst|tx~q ;
+wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ;
+wire [12:0] \uart_tx_inst|baud_cnt ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ;
+wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ;
+wire [3:0] \uart_tx_inst|bit_cnt ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ;
+wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ;
+wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ;
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ;
+wire [7:0] \uart_rx_inst|rx_data ;
+wire [7:0] \uart_rx_inst|po_data ;
+wire [3:0] \uart_rx_inst|bit_cnt ;
+wire [12:0] \uart_rx_inst|baud_cnt ;
+wire [11:0] \data_rw_ctrl_inst|send_data_num ;
+wire [15:0] \data_rw_ctrl_inst|cnt_wait ;
+wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ;
+wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ;
+wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ;
+wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ;
+wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ;
+wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ;
+wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ;
+wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ;
+
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ;
+wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4];
+
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16];
+
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+
+// Location: PLL_2
+cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 (
+	.areset(!\sys_rst_n~input_o ),
+	.pfdena(vcc),
+	.fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.phaseupdown(gnd),
+	.phasestep(gnd),
+	.scandata(gnd),
+	.scanclk(gnd),
+	.scanclkena(vcc),
+	.configupdate(gnd),
+	.clkswitch(gnd),
+	.inclk({gnd,\sys_clk~input_o }),
+	.phasecounterselect(3'b000),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.activeclock(),
+	.locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.vcooverrange(),
+	.vcounderrange(),
+	.fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ),
+	.clkbad());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND)))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: M9K_X13_Y13_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(18'b000000000000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y27_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9],
+\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2],
+\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(9'b000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0])
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N13
+dffeas \uart_tx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N7
+dffeas \uart_tx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N23
+dffeas \uart_tx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[2]~17_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16  & VCC))
+// \uart_tx_inst|baud_cnt[2]~18  = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_tx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[5]~23_combout  = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_tx_inst|baud_cnt[5]~24  = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5]))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_tx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[10]~33_combout  = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32  & VCC))
+// \uart_tx_inst|baud_cnt[10]~34  = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_tx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N11
+dffeas \data_rw_ctrl_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[5]~27_combout  = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[5]~28  = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[5]~28 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|Add1~4 (
+// Equation(s):
+// \uart_rx_inst|Add1~4_combout  = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3  $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3  & VCC))
+// \uart_rx_inst|Add1~5  = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 ))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~3 ),
+	.combout(\uart_rx_inst|Add1~4_combout ),
+	.cout(\uart_rx_inst|Add1~5 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N11
+dffeas \uart_rx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N23
+dffeas \uart_rx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N7
+dffeas \data_rw_ctrl_inst|send_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N13
+dffeas \data_rw_ctrl_inst|send_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N17
+dffeas \data_rw_ctrl_inst|send_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N19
+dffeas \data_rw_ctrl_inst|send_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N21
+dffeas \data_rw_ctrl_inst|send_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N23
+dffeas \data_rw_ctrl_inst|send_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[4]~21_combout  = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20  & VCC))
+// \uart_rx_inst|baud_cnt[4]~22  = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_rx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[10]~33_combout  = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32  & VCC))
+// \uart_rx_inst|baud_cnt[10]~34  = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_rx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[3]~18_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[3]~19  = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[2]~17 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[3]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[6]~24_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23  & VCC))
+// \data_rw_ctrl_inst|send_data_num[6]~25  = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 ))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[5]~23 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[6]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[7]~26_combout  = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[7]~27  = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[6]~25 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[7]~27 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[8]~28_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27  & VCC))
+// \data_rw_ctrl_inst|send_data_num[8]~29  = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[7]~27 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[8]~29 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[9]~30_combout  = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[9]~31  = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[8]~29 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[9]~31 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[10]~32_combout  = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31  & VCC))
+// \data_rw_ctrl_inst|send_data_num[10]~33  = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[9]~31 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[10]~33 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[11]~34_combout  = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 )
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|send_data_num[10]~33 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~1_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [14])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [15]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & 
+// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~6_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # 
+// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & 
+// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & 
+// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout  = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout  & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout  = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout  & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N15
+dffeas \uart_tx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneive_lcell_comb \uart_tx_inst|always0~0 (
+// Equation(s):
+// \uart_tx_inst|always0~0_combout  = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F;
+defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N30
+cycloneive_lcell_comb \uart_tx_inst|Mux0~1 (
+// Equation(s):
+// \uart_tx_inst|Mux0~1_combout  = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2;
+defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Mux0~2 (
+// Equation(s):
+// \uart_tx_inst|Mux0~2_combout  = (\uart_tx_inst|Mux0~1_combout  & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout  & 
+// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))
+
+	.dataa(\uart_tx_inst|Mux0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62;
+defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|Mux0~3 (
+// Equation(s):
+// \uart_tx_inst|Mux0~3_combout  = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0;
+defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneive_lcell_comb \uart_tx_inst|Mux0~4 (
+// Equation(s):
+// \uart_tx_inst|Mux0~4_combout  = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000;
+defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneive_lcell_comb \uart_tx_inst|Mux0~5 (
+// Equation(s):
+// \uart_tx_inst|Mux0~5_combout  = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout ))))
+
+	.dataa(\uart_tx_inst|Mux0~3_combout ),
+	.datab(\uart_tx_inst|Mux0~4_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|Mux0~2_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E;
+defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003;
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout  = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout  = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~0_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N17
+dffeas \uart_rx_inst|po_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N19
+dffeas \uart_rx_inst|po_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N21
+dffeas \uart_rx_inst|po_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N15
+dffeas \uart_rx_inst|po_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N9
+dffeas \uart_rx_inst|po_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N27
+dffeas \uart_rx_inst|po_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N13
+dffeas \uart_rx_inst|po_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N31
+dffeas \uart_rx_inst|po_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N21
+dffeas \uart_tx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_tx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneive_lcell_comb \uart_tx_inst|Add1~1 (
+// Equation(s):
+// \uart_tx_inst|Add1~1_combout  = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0;
+defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N14
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[2]~3_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|Add1~1_combout ))))
+
+	.dataa(\uart_tx_inst|Add1~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2;
+defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N1
+dffeas \uart_rx_inst|rx_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N11
+dffeas \uart_rx_inst|rx_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N29
+dffeas \uart_rx_inst|rx_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N23
+dffeas \uart_rx_inst|rx_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N27
+dffeas \uart_rx_inst|rx_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[7]~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N25
+dffeas \uart_rx_inst|rx_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N3
+dffeas \uart_rx_inst|rx_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N5
+dffeas \uart_rx_inst|rx_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N13
+dffeas \data_rw_ctrl_inst|tx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|tx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|tx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|work_en~0 (
+// Equation(s):
+// \uart_tx_inst|work_en~0_combout  = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q  & !\uart_tx_inst|always0~1_combout ))
+
+	.dataa(\data_rw_ctrl_inst|tx_flag~q ),
+	.datab(gnd),
+	.datac(\uart_tx_inst|work_en~q ),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N27
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [2])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & \sd_ctrl_inst|sd_init_inst|miso_dly~q )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N13
+dffeas \uart_rx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|always8~0 (
+// Equation(s):
+// \uart_rx_inst|always8~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|always4~0_combout  $ (!\uart_rx_inst|bit_cnt [3])))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282;
+defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N31
+dffeas \uart_rx_inst|rx_reg3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_reg2~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg3 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Equal2~0 (
+// Equation(s):
+// \uart_rx_inst|Equal2~0_combout  = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N1
+dffeas \uart_rx_inst|rx_reg2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~2_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [8]),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(\data_rw_ctrl_inst|send_data_num [11]),
+	.datad(\data_rw_ctrl_inst|send_data_num [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002;
+defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N30
+cycloneive_lcell_comb \uart_rx_inst|Equal1~2 (
+// Equation(s):
+// \uart_rx_inst|Equal1~2_combout  = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N3
+dffeas \uart_rx_inst|rx_reg1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg1~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg1 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N7
+dffeas \uart_rx_inst|start_nedge (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|start_nedge~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true";
+defparam \uart_rx_inst|start_nedge .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|always3~0 (
+// Equation(s):
+// \uart_rx_inst|always3~0_combout  = (!\uart_rx_inst|rx_reg3~q  & \uart_rx_inst|rx_reg2~q )
+
+	.dataa(\uart_rx_inst|rx_reg3~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg2~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050;
+defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 (
+// Equation(s):
+// \uart_rx_inst|rx_data[7]~0_combout  = !\uart_rx_inst|rx_reg3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg3~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F;
+defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 (
+// Equation(s):
+// \uart_rx_inst|rx_reg1~0_combout  = !\rx~input_o 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\rx~input_o ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF;
+defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneive_io_ibuf \rx~input (
+	.i(rx),
+	.ibar(gnd),
+	.o(\rx~input_o ));
+// synopsys translate_off
+defparam \rx~input .bus_hold = "false";
+defparam \rx~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|tx_flag~feeder_combout  = \data_rw_ctrl_inst|rd_fifo_rd_en~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N16
+cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[1]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[0]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N18
+cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[5]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N4
+cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[4]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N20
+cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[6]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N10
+cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[5]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N8
+cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[7]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N28
+cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[6]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N26
+cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[3]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N22
+cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[2]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N12
+cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[0]~feeder_combout  = \uart_rx_inst|rx_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N0
+cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_reg2~feeder_combout  = \uart_rx_inst|rx_reg1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_reg1~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOOBUF_X5_Y29_N23
+cycloneive_io_obuf \sd_clk~output (
+	.i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_clk),
+	.obar());
+// synopsys translate_off
+defparam \sd_clk~output .bus_hold = "false";
+defparam \sd_clk~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y29_N23
+cycloneive_io_obuf \sd_cs_n~output (
+	.i(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_cs_n),
+	.obar());
+// synopsys translate_off
+defparam \sd_cs_n~output .bus_hold = "false";
+defparam \sd_cs_n~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X1_Y29_N9
+cycloneive_io_obuf \sd_mosi~output (
+	.i(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_mosi),
+	.obar());
+// synopsys translate_off
+defparam \sd_mosi~output .bus_hold = "false";
+defparam \sd_mosi~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N16
+cycloneive_io_obuf \tx~output (
+	.i(!\uart_tx_inst|tx~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(tx),
+	.obar());
+// synopsys translate_off
+defparam \tx~output .bus_hold = "false";
+defparam \tx~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N22
+cycloneive_io_ibuf \sys_clk~input (
+	.i(sys_clk),
+	.ibar(gnd),
+	.o(\sys_clk~input_o ));
+// synopsys translate_off
+defparam \sys_clk~input .bus_hold = "false";
+defparam \sys_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y4_N1
+cycloneive_io_ibuf \sys_rst_n~input (
+	.i(sys_rst_n),
+	.ibar(gnd),
+	.o(\sys_rst_n~input_o ));
+// synopsys translate_off
+defparam \sys_rst_n~input .bus_hold = "false";
+defparam \sys_rst_n~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N0
+cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder (
+// Equation(s):
+// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout  = VCC
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y1_N1
+dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.asdata(vcc),
+	.clrn(\sys_rst_n~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N26
+cycloneive_lcell_comb \rst_n~0 (
+// Equation(s):
+// \rst_n~0_combout  = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )
+
+	.dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.datab(\sys_rst_n~input_o ),
+	.datac(gnd),
+	.datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.cin(gnd),
+	.combout(\rst_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \rst_n~0 .lut_mask = 16'h77FF;
+defparam \rst_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G16
+cycloneive_clkctrl \rst_n~0clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\rst_n~0_combout }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\rst_n~0clkctrl_outclk ));
+// synopsys translate_off
+defparam \rst_n~0clkctrl .clock_type = "global clock";
+defparam \rst_n~0clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X11_Y29_N29
+cycloneive_io_ibuf \sd_miso~input (
+	.i(sd_miso),
+	.ibar(gnd),
+	.o(\sd_miso~input_o ));
+// synopsys translate_off
+defparam \sd_miso~input .bus_hold = "false";
+defparam \sd_miso~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|miso_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_miso~input_o ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout  & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (((\sd_ctrl_inst|sd_read_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N3
+dffeas \sd_ctrl_inst|sd_read_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & \sd_ctrl_inst|sd_read_inst|ack_en~q ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N19
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout  & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  = (\sd_ctrl_inst|sd_init_inst|ack_en~q  & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout  = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [11]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [12]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [13]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [14]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [15]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [17]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [18]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [19]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [29]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [30]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [32]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [33]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [36]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [37]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N27
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2;
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N9
+dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0;
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr18~combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout  & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout  = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout  & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|init_end (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout  = (\data_rw_ctrl_inst|rd_en~q  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))
+
+	.dataa(\data_rw_ctrl_inst|rd_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout  & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Add3~0_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0;
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [12])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N29
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [13])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [14])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [9])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [10])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [7])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N3
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout  = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout  & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [4])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N1
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~3_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~4_combout  = (\sd_ctrl_inst|sd_read_inst|always3~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~4_combout  & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & 
+// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout  & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout 
+//  & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N3
+dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|miso_dly~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (((\sd_ctrl_inst|sd_write_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q  & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N23
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N19
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N25
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N31
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N21
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N27
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N1
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) 
+// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~2_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~1_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit 
+// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~3_combout  = (\sd_ctrl_inst|sd_write_inst|always4~1_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N17
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N27
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N9
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N31
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N13
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N25
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N15
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N5
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N19
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1])))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout  = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout  & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q )))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA;
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout  = (\sd_ctrl_inst|comb~2_combout  & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout  = \sd_ctrl_inst|sd_write_inst|state.IDLE~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N19
+dffeas \data_rw_ctrl_inst|wr_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_fall~0_combout  = (\data_rw_ctrl_inst|wr_busy_dly~q  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC;
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N11
+dffeas \data_rw_ctrl_inst|rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout  = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230;
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) 
+// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout  = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F;
+defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & (((\sd_ctrl_inst|sd_init_inst|mosi~q  & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~1_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout )))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N1
+dffeas \sd_ctrl_inst|sd_read_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Add1~0 (
+// Equation(s):
+// \uart_rx_inst|Add1~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] & VCC))
+// \uart_rx_inst|Add1~1  = CARRY((\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [0]))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Add1~0_combout ),
+	.cout(\uart_rx_inst|Add1~1 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Add1~2 (
+// Equation(s):
+// \uart_rx_inst|Add1~2_combout  = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND)))
+// \uart_rx_inst|Add1~3  = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~1 ),
+	.combout(\uart_rx_inst|Add1~2_combout ),
+	.cout(\uart_rx_inst|Add1~3 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|Add1~6 (
+// Equation(s):
+// \uart_rx_inst|Add1~6_combout  = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|Add1~5 ),
+	.combout(\uart_rx_inst|Add1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C;
+defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~0_combout  = (\uart_rx_inst|Add1~6_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|Add1~6_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC;
+defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N5
+dffeas \uart_rx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~1_combout  = (\uart_rx_inst|Add1~0_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(\uart_rx_inst|Add1~0_combout ),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0;
+defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N25
+dffeas \uart_rx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N11
+dffeas \uart_rx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|always4~0 (
+// Equation(s):
+// \uart_rx_inst|always4~0_combout  = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(\uart_rx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011;
+defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[0]~13_combout  = (\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] & VCC))
+// \uart_rx_inst|baud_cnt[0]~14  = CARRY((\uart_rx_inst|work_en~q  & \uart_rx_inst|baud_cnt [0]))
+
+	.dataa(\uart_rx_inst|work_en~q ),
+	.datab(\uart_rx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_rx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|Equal1~0 (
+// Equation(s):
+// \uart_rx_inst|Equal1~0_combout  = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0])))
+
+	.dataa(\uart_rx_inst|baud_cnt [8]),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(\uart_rx_inst|baud_cnt [1]),
+	.datad(\uart_rx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000;
+defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[5]~23_combout  = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_rx_inst|baud_cnt[5]~24  = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5]))
+
+	.dataa(\uart_rx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_rx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N13
+dffeas \uart_rx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[2]~17_combout  = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16  & VCC))
+// \uart_rx_inst|baud_cnt[2]~18  = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_rx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N7
+dffeas \uart_rx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Equal1~1 (
+// Equation(s):
+// \uart_rx_inst|Equal1~1_combout  = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|Equal1~3 (
+// Equation(s):
+// \uart_rx_inst|Equal1~3_combout  = (\uart_rx_inst|Equal1~2_combout  & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal1~2_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000;
+defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|work_en~0 (
+// Equation(s):
+// \uart_rx_inst|work_en~0_combout  = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q  & !\uart_rx_inst|always4~1_combout ))
+
+	.dataa(\uart_rx_inst|start_nedge~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|work_en~q ),
+	.datad(\uart_rx_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N17
+dffeas \uart_rx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_rx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|always5~0 (
+// Equation(s):
+// \uart_rx_inst|always5~0_combout  = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|Equal1~3_combout ),
+	.datac(gnd),
+	.datad(\uart_rx_inst|work_en~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF;
+defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N3
+dffeas \uart_rx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[1]~15_combout  = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_rx_inst|baud_cnt[1]~16  = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_rx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N5
+dffeas \uart_rx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[3]~19_combout  = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_rx_inst|baud_cnt[3]~20  = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_rx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N9
+dffeas \uart_rx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[6]~25_combout  = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24  & VCC))
+// \uart_rx_inst|baud_cnt[6]~26  = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_rx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N15
+dffeas \uart_rx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[7]~27_combout  = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_rx_inst|baud_cnt[7]~28  = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_rx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N17
+dffeas \uart_rx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[8]~29_combout  = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28  & VCC))
+// \uart_rx_inst|baud_cnt[8]~30  = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_rx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N19
+dffeas \uart_rx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[9]~31_combout  = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_rx_inst|baud_cnt[9]~32  = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_rx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N21
+dffeas \uart_rx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[11]~35_combout  = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_rx_inst|baud_cnt[11]~36  = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_rx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N25
+dffeas \uart_rx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[12]~37_combout  = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_rx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N27
+dffeas \uart_rx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|Equal2~1 (
+// Equation(s):
+// \uart_rx_inst|Equal2~1_combout  = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|Equal2~2 (
+// Equation(s):
+// \uart_rx_inst|Equal2~2_combout  = (\uart_rx_inst|Equal2~0_combout  & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal2~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal2~0_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000;
+defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N23
+dffeas \uart_rx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Equal2~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|always4~1 (
+// Equation(s):
+// \uart_rx_inst|always4~1_combout  = (\uart_rx_inst|always4~0_combout  & (\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_flag~q ),
+	.datad(\uart_rx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000;
+defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N1
+dffeas \uart_rx_inst|rx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always4~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N1
+dffeas \uart_rx_inst|po_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_flag~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\uart_rx_inst|po_flag~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datac(\uart_rx_inst|po_flag~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q  $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & 
+// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N4
+cycloneive_lcell_comb \sd_ctrl_inst|comb~1 (
+// Equation(s):
+// \sd_ctrl_inst|comb~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N0
+cycloneive_lcell_comb \sd_ctrl_inst|comb~0 (
+// Equation(s):
+// \sd_ctrl_inst|comb~0_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N2
+cycloneive_lcell_comb \sd_ctrl_inst|comb~2 (
+// Equation(s):
+// \sd_ctrl_inst|comb~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  & 
+// (\sd_ctrl_inst|comb~1_combout  & \sd_ctrl_inst|comb~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.datac(\sd_ctrl_inst|comb~1_combout ),
+	.datad(\sd_ctrl_inst|comb~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & (((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & 
+// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|comb~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~2_combout  = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~3_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~4_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~5_combout  = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~8_combout  = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout  & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout  & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X11_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|mosi~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & (!\sd_ctrl_inst|sd_init_inst|mosi~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05;
+defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G8
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N2
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[0]~13_combout  = (\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] & VCC))
+// \uart_tx_inst|baud_cnt[0]~14  = CARRY((\uart_tx_inst|work_en~q  & \uart_tx_inst|baud_cnt [0]))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_tx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N0
+cycloneive_lcell_comb \uart_tx_inst|Equal1~0 (
+// Equation(s):
+// \uart_tx_inst|Equal1~0_combout  = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0])))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(\uart_tx_inst|baud_cnt [3]),
+	.datad(\uart_tx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100;
+defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|Equal1~1 (
+// Equation(s):
+// \uart_tx_inst|Equal1~1_combout  = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout  & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9])))
+
+	.dataa(\uart_tx_inst|baud_cnt [8]),
+	.datab(\uart_tx_inst|Equal1~0_combout ),
+	.datac(\uart_tx_inst|baud_cnt [11]),
+	.datad(\uart_tx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004;
+defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[4]~21_combout  = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20  & VCC))
+// \uart_tx_inst|baud_cnt[4]~22  = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_tx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N11
+dffeas \uart_tx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N30
+cycloneive_lcell_comb \uart_tx_inst|Equal1~2 (
+// Equation(s):
+// \uart_tx_inst|Equal1~2_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Equal1~3 (
+// Equation(s):
+// \uart_tx_inst|Equal1~3_combout  = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12])
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(\uart_tx_inst|baud_cnt [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0;
+defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|always1~0 (
+// Equation(s):
+// \uart_tx_inst|always1~0_combout  = ((\uart_tx_inst|Equal1~1_combout  & (\uart_tx_inst|Equal1~2_combout  & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|Equal1~1_combout ),
+	.datac(\uart_tx_inst|Equal1~2_combout ),
+	.datad(\uart_tx_inst|Equal1~3_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555;
+defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N3
+dffeas \uart_tx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[1]~15_combout  = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_tx_inst|baud_cnt[1]~16  = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_tx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N5
+dffeas \uart_tx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[3]~19_combout  = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_tx_inst|baud_cnt[3]~20  = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_tx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N9
+dffeas \uart_tx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[6]~25_combout  = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24  & VCC))
+// \uart_tx_inst|baud_cnt[6]~26  = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_tx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N15
+dffeas \uart_tx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[7]~27_combout  = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_tx_inst|baud_cnt[7]~28  = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_tx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N17
+dffeas \uart_tx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[8]~29_combout  = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28  & VCC))
+// \uart_tx_inst|baud_cnt[8]~30  = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_tx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N19
+dffeas \uart_tx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[9]~31_combout  = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_tx_inst|baud_cnt[9]~32  = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_tx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N21
+dffeas \uart_tx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[11]~35_combout  = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_tx_inst|baud_cnt[11]~36  = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_tx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N25
+dffeas \uart_tx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N26
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[12]~37_combout  = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_tx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_tx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N27
+dffeas \uart_tx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N28
+cycloneive_lcell_comb \uart_tx_inst|Equal2~0 (
+// Equation(s):
+// \uart_tx_inst|Equal2~0_combout  = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Equal2~1 (
+// Equation(s):
+// \uart_tx_inst|Equal2~1_combout  = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout  & \uart_tx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(\uart_tx_inst|baud_cnt [12]),
+	.datac(\uart_tx_inst|Equal2~0_combout ),
+	.datad(\uart_tx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N25
+dffeas \uart_tx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|Equal2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N18
+cycloneive_lcell_comb \uart_tx_inst|always3~0 (
+// Equation(s):
+// \uart_tx_inst|always3~0_combout  = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_tx_inst|bit_flag~q ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF;
+defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneive_lcell_comb \uart_tx_inst|always0~1 (
+// Equation(s):
+// \uart_tx_inst|always0~1_combout  = (\uart_tx_inst|always0~0_combout  & (\uart_tx_inst|bit_flag~q  & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3])))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[0]~5_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q  & \uart_tx_inst|bit_flag~q )))))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078;
+defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N5
+dffeas \uart_tx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[1]~4_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [1]),
+	.datad(\uart_tx_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014;
+defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N1
+dffeas \uart_tx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Add1~0 (
+// Equation(s):
+// \uart_tx_inst|Add1~0_combout  = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))))
+
+	.dataa(\uart_tx_inst|bit_cnt [2]),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC;
+defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[3]~2_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|Add1~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [3]),
+	.datad(\uart_tx_inst|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140;
+defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N3
+dffeas \uart_tx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[0]~16_combout  = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC)
+// \data_rw_ctrl_inst|cnt_wait[0]~17  = CARRY(\data_rw_ctrl_inst|cnt_wait [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[0]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[3]~22_combout  = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[3]~23  = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[3]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[4]~24_combout  = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[4]~25  = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[4]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N9
+dffeas \data_rw_ctrl_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~0_combout  = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5])
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5;
+defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N15
+dffeas \data_rw_ctrl_inst|rd_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[0]~12_combout  = \data_rw_ctrl_inst|send_data_num [0] $ (VCC)
+// \data_rw_ctrl_inst|send_data_num[0]~13  = CARRY(\data_rw_ctrl_inst|send_data_num [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[0]~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N1
+dffeas \data_rw_ctrl_inst|send_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[1]~14_combout  = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[1]~15  = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[0]~13 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[1]~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N3
+dffeas \data_rw_ctrl_inst|send_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[2]~16_combout  = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15  & VCC))
+// \data_rw_ctrl_inst|send_data_num[2]~17  = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[1]~15 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[2]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N5
+dffeas \data_rw_ctrl_inst|send_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~0_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(\data_rw_ctrl_inst|send_data_num [2]),
+	.datad(\data_rw_ctrl_inst|send_data_num [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[4]~20_combout  = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19  & VCC))
+// \data_rw_ctrl_inst|send_data_num[4]~21  = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[3]~19 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[4]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N9
+dffeas \data_rw_ctrl_inst|send_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[5]~22_combout  = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[5]~23  = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[4]~21 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[5]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N15
+dffeas \data_rw_ctrl_inst|send_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N11
+dffeas \data_rw_ctrl_inst|send_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~1_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(\data_rw_ctrl_inst|send_data_num [4]),
+	.datad(\data_rw_ctrl_inst|send_data_num [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~3_combout  = (\data_rw_ctrl_inst|always3~2_combout  & (\data_rw_ctrl_inst|always3~0_combout  & (\data_rw_ctrl_inst|always3~1_combout  & \data_rw_ctrl_inst|Equal2~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|always3~2_combout ),
+	.datab(\data_rw_ctrl_inst|always3~0_combout ),
+	.datac(\data_rw_ctrl_inst|always3~1_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_en~0_combout  = (!\data_rw_ctrl_inst|always3~3_combout  & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & \data_rw_ctrl_inst|rd_busy_dly~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datab(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4;
+defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N23
+dffeas \data_rw_ctrl_inst|send_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~1_combout  = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~26_combout  = ((\data_rw_ctrl_inst|Equal2~2_combout  & (!\data_rw_ctrl_inst|Equal3~0_combout  & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q )
+
+	.dataa(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.datab(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N1
+dffeas \data_rw_ctrl_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[1]~18_combout  = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[1]~19  = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[1]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N3
+dffeas \data_rw_ctrl_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[2]~20_combout  = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[2]~21  = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[2]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N5
+dffeas \data_rw_ctrl_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N7
+dffeas \data_rw_ctrl_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~3_combout  = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[6]~29_combout  = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[6]~30  = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 ))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[6]~30 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[7]~31_combout  = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[7]~32  = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[7]~32 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N15
+dffeas \data_rw_ctrl_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[8]~33_combout  = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[8]~34  = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[8]~34 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N17
+dffeas \data_rw_ctrl_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[9]~35_combout  = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[9]~36  = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[9]~36 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N19
+dffeas \data_rw_ctrl_inst|cnt_wait[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[10]~37_combout  = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[10]~38  = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[10]~38 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N21
+dffeas \data_rw_ctrl_inst|cnt_wait[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[11]~39_combout  = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[11]~40  = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[11]~40 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[12]~41_combout  = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[12]~42  = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[12]~42 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N25
+dffeas \data_rw_ctrl_inst|cnt_wait[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~43_combout  = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[13]~44  = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[13]~44 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[14]~45_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[14]~46  = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[14]~46 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N29
+dffeas \data_rw_ctrl_inst|cnt_wait[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[15]~47_combout  = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 )
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N31
+dffeas \data_rw_ctrl_inst|cnt_wait[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N13
+dffeas \data_rw_ctrl_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~0_combout  = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N27
+dffeas \data_rw_ctrl_inst|cnt_wait[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N23
+dffeas \data_rw_ctrl_inst|cnt_wait[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~1_combout  = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [11]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~2_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout  & \data_rw_ctrl_inst|Equal2~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datac(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~4_combout  = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout  & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000;
+defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N7
+dffeas \data_rw_ctrl_inst|rd_fifo_rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\data_rw_ctrl_inst|rd_fifo_rd_en~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q  $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (\data_rw_ctrl_inst|rd_fifo_rd_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout  = (\sd_miso~input_o  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|Mux0~0 (
+// Equation(s):
+// \uart_tx_inst|Mux0~0_combout  = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout )))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4;
+defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N8
+cycloneive_lcell_comb \uart_tx_inst|tx~0 (
+// Equation(s):
+// \uart_tx_inst|tx~0_combout  = (\uart_tx_inst|bit_flag~q  & (!\uart_tx_inst|Mux0~5_combout  & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q  & (((\uart_tx_inst|tx~q ))))
+
+	.dataa(\uart_tx_inst|Mux0~5_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|tx~q ),
+	.datad(\uart_tx_inst|Mux0~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|tx~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074;
+defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N9
+dffeas \uart_tx_inst|tx (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|tx~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|tx~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|tx .is_wysiwyg = "true";
+defparam \uart_tx_inst|tx .power_up = "low";
+// synopsys translate_on
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo
new file mode 100644
index 0000000..273365b
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo
@@ -0,0 +1,19061 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE15F23C8,
+// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "uart_sd")
+  (DATE "06/02/2023 04:03:14")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_pll")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1)
+    (DELAY
+      (ABSOLUTE
+        (PORT areset (3924:3924:3924) (3924:3924:3924))
+        (PORT inclk[0] (2063:2063:2063) (2063:2063:2063))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (907:907:907) (825:825:825))
+        (PORT datab (786:786:786) (701:701:701))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (784:784:784) (715:715:715))
+        (PORT datab (1205:1205:1205) (1035:1035:1035))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (530:530:530) (510:510:510))
+        (PORT datab (318:318:318) (372:372:372))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (2620:2620:2620) (2938:2938:2938))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1351:1351:1351) (1246:1246:1246))
+        (PORT d[1] (1315:1315:1315) (1212:1212:1212))
+        (PORT d[2] (1409:1409:1409) (1283:1283:1283))
+        (PORT d[3] (1520:1520:1520) (1415:1415:1415))
+        (PORT d[4] (1344:1344:1344) (1239:1239:1239))
+        (PORT d[5] (1527:1527:1527) (1423:1423:1423))
+        (PORT d[6] (1371:1371:1371) (1259:1259:1259))
+        (PORT d[7] (1368:1368:1368) (1248:1248:1248))
+        (PORT clk (2015:2015:2015) (2062:2062:2062))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (968:968:968) (912:912:912))
+        (PORT d[1] (1018:1018:1018) (953:953:953))
+        (PORT d[2] (1244:1244:1244) (1117:1117:1117))
+        (PORT d[3] (1112:1112:1112) (982:982:982))
+        (PORT d[4] (963:963:963) (912:912:912))
+        (PORT d[5] (1701:1701:1701) (1533:1533:1533))
+        (PORT d[6] (1351:1351:1351) (1225:1225:1225))
+        (PORT d[7] (1689:1689:1689) (1491:1491:1491))
+        (PORT d[8] (991:991:991) (934:934:934))
+        (PORT d[9] (900:900:900) (797:797:797))
+        (PORT clk (2012:2012:2012) (2058:2058:2058))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1186:1186:1186) (1045:1045:1045))
+        (PORT clk (2012:2012:2012) (2058:2058:2058))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2015:2015:2015) (2062:2062:2062))
+        (PORT d[0] (1808:1808:1808) (1677:1677:1677))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2016:2016:2016) (2063:2063:2063))
+        (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2016:2016:2016) (2063:2063:2063))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2016:2016:2016) (2063:2063:2063))
+        (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2016:2016:2016) (2063:2063:2063))
+        (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1305:1305:1305) (1132:1132:1132))
+        (PORT d[1] (993:993:993) (932:932:932))
+        (PORT d[2] (1709:1709:1709) (1550:1550:1550))
+        (PORT d[3] (1702:1702:1702) (1564:1564:1564))
+        (PORT d[4] (1550:1550:1550) (1467:1467:1467))
+        (PORT d[5] (1790:1790:1790) (1643:1643:1643))
+        (PORT d[6] (1307:1307:1307) (1204:1204:1204))
+        (PORT d[7] (1388:1388:1388) (1291:1291:1291))
+        (PORT d[8] (948:948:948) (832:832:832))
+        (PORT clk (1968:1968:1968) (1970:1970:1970))
+        (PORT stall (1428:1428:1428) (1622:1622:1622))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+      (HOLD stall (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1968:1968:1968) (1970:1970:1970))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1969:1969:1969) (1971:1971:1971))
+        (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1969:1969:1969) (1971:1971:1971))
+        (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1969:1969:1969) (1971:1971:1971))
+        (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1959:1959:1959) (1963:1963:1963))
+        (PORT ena (1982:1982:1982) (1809:1809:1809))
+        (IOPATH (posedge clk) q (353:353:353) (353:353:353))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (56:56:56))
+      (SETUP ena (posedge clk) (56:56:56))
+      (HOLD d (posedge clk) (190:190:190))
+      (HOLD ena (posedge clk) (190:190:190))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1178:1178:1178) (1038:1038:1038))
+        (PORT d[1] (1142:1142:1142) (1014:1014:1014))
+        (PORT d[2] (1158:1158:1158) (1032:1032:1032))
+        (PORT d[3] (1542:1542:1542) (1346:1346:1346))
+        (PORT d[4] (1177:1177:1177) (1035:1035:1035))
+        (PORT d[5] (1138:1138:1138) (1014:1014:1014))
+        (PORT d[6] (1182:1182:1182) (1044:1044:1044))
+        (PORT d[7] (1174:1174:1174) (1037:1037:1037))
+        (PORT d[9] (1145:1145:1145) (1019:1019:1019))
+        (PORT d[10] (1231:1231:1231) (1107:1107:1107))
+        (PORT d[11] (1219:1219:1219) (1088:1088:1088))
+        (PORT d[12] (1181:1181:1181) (1042:1042:1042))
+        (PORT d[13] (1473:1473:1473) (1295:1295:1295))
+        (PORT d[14] (1142:1142:1142) (1016:1016:1016))
+        (PORT d[15] (1528:1528:1528) (1325:1325:1325))
+        (PORT d[16] (1536:1536:1536) (1333:1333:1333))
+        (PORT clk (2030:2030:2030) (2071:2071:2071))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1301:1301:1301) (1179:1179:1179))
+        (PORT d[1] (1266:1266:1266) (1130:1130:1130))
+        (PORT d[2] (1619:1619:1619) (1420:1420:1420))
+        (PORT d[3] (1163:1163:1163) (1043:1043:1043))
+        (PORT d[4] (971:971:971) (897:897:897))
+        (PORT d[5] (1757:1757:1757) (1503:1503:1503))
+        (PORT d[6] (1632:1632:1632) (1440:1440:1440))
+        (PORT d[7] (919:919:919) (863:863:863))
+        (PORT d[8] (1531:1531:1531) (1279:1279:1279))
+        (PORT clk (2027:2027:2027) (2067:2067:2067))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1207:1207:1207) (1072:1072:1072))
+        (PORT clk (2027:2027:2027) (2067:2067:2067))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2030:2030:2030) (2071:2071:2071))
+        (PORT d[0] (1829:1829:1829) (1704:1704:1704))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2031:2031:2031) (2072:2072:2072))
+        (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2031:2031:2031) (2072:2072:2072))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2031:2031:2031) (2072:2072:2072))
+        (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2031:2031:2031) (2072:2072:2072))
+        (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1276:1276:1276) (1087:1087:1087))
+        (PORT d[1] (1734:1734:1734) (1574:1574:1574))
+        (PORT d[2] (1396:1396:1396) (1305:1305:1305))
+        (PORT d[3] (989:989:989) (923:923:923))
+        (PORT d[4] (1025:1025:1025) (949:949:949))
+        (PORT d[5] (1508:1508:1508) (1409:1409:1409))
+        (PORT d[6] (973:973:973) (898:898:898))
+        (PORT d[7] (1281:1281:1281) (1179:1179:1179))
+        (PORT d[8] (1263:1263:1263) (1150:1150:1150))
+        (PORT d[9] (1574:1574:1574) (1365:1365:1365))
+        (PORT clk (1983:1983:1983) (1979:1979:1979))
+        (PORT stall (1126:1126:1126) (1286:1286:1286))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (230:230:230))
+      (HOLD stall (posedge clk) (230:230:230))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1983:1983:1983) (1979:1979:1979))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1984:1984:1984) (1980:1980:1980))
+        (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1984:1984:1984) (1980:1980:1980))
+        (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1984:1984:1984) (1980:1980:1980))
+        (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1974:1974:1974) (1972:1972:1972))
+        (PORT ena (1647:1647:1647) (1507:1507:1507))
+        (IOPATH (posedge clk) q (353:353:353) (353:353:353))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (56:56:56))
+      (SETUP ena (posedge clk) (56:56:56))
+      (HOLD d (posedge clk) (190:190:190))
+      (HOLD ena (posedge clk) (190:190:190))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (550:550:550) (545:545:545))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (358:358:358) (435:435:435))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (392:392:392))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (389:389:389))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (420:420:420))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (414:414:414))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (393:393:393))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (404:404:404))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (393:393:393))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (325:325:325) (382:382:382))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (390:390:390))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (418:418:418))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (393:393:393))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (336:336:336) (404:404:404))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (393:393:393))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (326:326:326) (388:388:388))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (392:392:392))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (407:407:407))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (391:391:391))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (393:393:393))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (385:385:385))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (393:393:393))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (782:782:782) (713:713:713))
+        (PORT datad (293:293:293) (356:356:356))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (611:611:611) (566:566:566))
+        (PORT datac (561:561:561) (533:533:533))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (390:390:390))
+        (PORT datab (546:546:546) (532:532:532))
+        (PORT datac (282:282:282) (348:348:348))
+        (PORT datad (285:285:285) (344:344:344))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (552:552:552) (542:542:542))
+        (PORT datab (326:326:326) (384:384:384))
+        (PORT datac (283:283:283) (349:349:349))
+        (PORT datad (225:225:225) (232:232:232))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (508:508:508) (498:498:498))
+        (PORT datad (472:472:472) (393:393:393))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (295:295:295))
+        (PORT datab (624:624:624) (581:581:581))
+        (PORT datac (1899:1899:1899) (1688:1688:1688))
+        (PORT datad (1100:1100:1100) (900:900:900))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (419:419:419))
+        (PORT datab (344:344:344) (407:407:407))
+        (PORT datac (300:300:300) (371:371:371))
+        (PORT datad (300:300:300) (365:365:365))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (561:561:561))
+        (PORT datab (377:377:377) (452:452:452))
+        (PORT datac (893:893:893) (774:774:774))
+        (PORT datad (487:487:487) (427:427:427))
+        (IOPATH dataa combout (420:420:420) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (920:920:920) (813:813:813))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (488:488:488) (436:436:436))
+        (PORT datad (339:339:339) (417:417:417))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (601:601:601) (513:513:513))
+        (PORT datab (365:365:365) (428:428:428))
+        (PORT datac (545:545:545) (478:478:478))
+        (PORT datad (340:340:340) (418:418:418))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (273:273:273) (285:285:285))
+        (PORT datab (366:366:366) (430:430:430))
+        (PORT datac (1608:1608:1608) (1382:1382:1382))
+        (PORT datad (897:897:897) (786:786:786))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (561:561:561))
+        (PORT datab (371:371:371) (447:447:447))
+        (PORT datac (878:878:878) (758:758:758))
+        (PORT datad (492:492:492) (434:434:434))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (431:431:431))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (955:955:955) (821:821:821))
+        (PORT datab (366:366:366) (429:429:429))
+        (PORT datac (441:441:441) (378:378:378))
+        (PORT datad (909:909:909) (787:787:787))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (282:282:282))
+        (PORT datab (347:347:347) (412:412:412))
+        (PORT datac (322:322:322) (395:395:395))
+        (PORT datad (228:228:228) (236:236:236))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (925:925:925) (821:821:821))
+        (PORT datab (365:365:365) (429:429:429))
+        (PORT datac (538:538:538) (469:469:469))
+        (PORT datad (337:337:337) (415:415:415))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (431:431:431))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (911:911:911) (804:804:804))
+        (PORT datab (380:380:380) (456:456:456))
+        (PORT datac (536:536:536) (468:468:468))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (283:283:283))
+        (PORT datab (350:350:350) (417:417:417))
+        (PORT datac (227:227:227) (242:242:242))
+        (PORT datad (229:229:229) (236:236:236))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (296:296:296))
+        (PORT datab (624:624:624) (581:581:581))
+        (PORT datac (555:555:555) (526:526:526))
+        (PORT datad (847:847:847) (734:734:734))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (921:921:921))
+        (PORT datab (1067:1067:1067) (988:988:988))
+        (PORT datac (945:945:945) (896:896:896))
+        (PORT datad (975:975:975) (912:912:912))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (968:968:968) (905:905:905))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (944:944:944) (895:895:895))
+        (PORT datad (946:946:946) (869:869:869))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (973:973:973) (921:921:921))
+        (PORT datab (989:989:989) (928:928:928))
+        (PORT datac (1008:1008:1008) (949:949:949))
+        (PORT datad (973:973:973) (909:909:909))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (431:431:431))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (268:268:268) (274:274:274))
+        (PORT datac (926:926:926) (867:867:867))
+        (PORT datad (870:870:870) (810:810:810))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (921:921:921))
+        (PORT datab (1063:1063:1063) (983:983:983))
+        (PORT datac (928:928:928) (879:879:879))
+        (PORT datad (973:973:973) (910:910:910))
+        (IOPATH dataa combout (420:420:420) (377:377:377))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (974:974:974) (921:921:921))
+        (PORT datab (988:988:988) (927:927:927))
+        (PORT datac (924:924:924) (866:866:866))
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (921:921:921))
+        (PORT datab (990:990:990) (930:930:930))
+        (PORT datac (926:926:926) (877:877:877))
+        (PORT datad (974:974:974) (911:911:911))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (967:967:967) (904:904:904))
+        (PORT datab (1066:1066:1066) (987:987:987))
+        (PORT datac (945:945:945) (895:895:895))
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH dataa combout (351:351:351) (377:377:377))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (921:921:921))
+        (PORT datab (1069:1069:1069) (991:991:991))
+        (PORT datac (946:946:946) (897:897:897))
+        (PORT datad (976:976:976) (913:913:913))
+        (IOPATH dataa combout (420:420:420) (444:444:444))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (966:966:966) (903:903:903))
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (924:924:924) (875:875:875))
+        (PORT datad (870:870:870) (805:805:805))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (284:284:284))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (225:225:225) (240:240:240))
+        (PORT datad (876:876:876) (811:811:811))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1024:1024:1024) (928:928:928))
+        (PORT datab (269:269:269) (276:276:276))
+        (PORT datac (226:226:226) (241:241:241))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1666:1666:1666) (1684:1684:1684))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1698:1698:1698) (1649:1649:1649))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (313:313:313) (382:382:382))
+        (PORT datad (320:320:320) (396:396:396))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (929:929:929) (777:777:777))
+        (PORT datab (371:371:371) (443:443:443))
+        (PORT datac (338:338:338) (424:424:424))
+        (PORT datad (844:844:844) (708:708:708))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (281:281:281))
+        (PORT datab (368:368:368) (441:441:441))
+        (PORT datac (832:832:832) (701:701:701))
+        (PORT datad (853:853:853) (720:720:720))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (839:839:839) (719:719:719))
+        (PORT datab (383:383:383) (458:458:458))
+        (PORT datac (786:786:786) (667:667:667))
+        (PORT datad (328:328:328) (404:404:404))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (384:384:384) (459:459:459))
+        (PORT datac (788:788:788) (669:669:669))
+        (PORT datad (328:328:328) (405:405:405))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datab (268:268:268) (274:274:274))
+        (PORT datac (314:314:314) (384:384:384))
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (390:390:390))
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datad (513:513:513) (499:499:499))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (576:576:576) (562:562:562))
+        (PORT datab (342:342:342) (404:404:404))
+        (PORT datac (300:300:300) (372:372:372))
+        (PORT datad (248:248:248) (255:255:255))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (599:599:599) (549:549:549))
+        (PORT datac (548:548:548) (515:515:515))
+        (PORT datad (502:502:502) (482:482:482))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT asdata (1620:1620:1620) (1493:1493:1493))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (882:882:882) (803:803:803))
+        (PORT datab (1189:1189:1189) (1061:1061:1061))
+        (PORT datac (318:318:318) (388:388:388))
+        (PORT datad (243:243:243) (258:258:258))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datac (330:330:330) (397:397:397))
+        (PORT datad (257:257:257) (269:269:269))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (576:576:576) (562:562:562))
+        (PORT datad (243:243:243) (258:258:258))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (864:864:864) (756:756:756))
+        (PORT datac (781:781:781) (705:705:705))
+        (PORT datad (749:749:749) (622:622:622))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (781:781:781) (705:705:705))
+        (PORT datad (749:749:749) (622:622:622))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1236:1236:1236) (1101:1101:1101))
+        (PORT datad (1166:1166:1166) (1029:1029:1029))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (395:395:395))
+        (PORT datac (293:293:293) (363:363:363))
+        (PORT datad (300:300:300) (365:365:365))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (426:426:426))
+        (PORT datab (337:337:337) (398:398:398))
+        (PORT datac (314:314:314) (384:384:384))
+        (PORT datad (294:294:294) (356:356:356))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (335:335:335) (401:401:401))
+        (PORT datab (286:286:286) (299:299:299))
+        (PORT datac (826:826:826) (743:743:743))
+        (PORT datad (243:243:243) (257:257:257))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (877:877:877) (821:821:821))
+        (PORT datab (580:580:580) (502:502:502))
+        (PORT datac (1072:1072:1072) (898:898:898))
+        (PORT datad (315:315:315) (378:378:378))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datad (281:281:281) (339:339:339))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (955:955:955) (812:812:812))
+        (PORT datac (765:765:765) (639:639:639))
+        (PORT datad (320:320:320) (385:385:385))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (337:337:337) (403:403:403))
+        (PORT datab (286:286:286) (299:299:299))
+        (PORT datac (826:826:826) (743:743:743))
+        (PORT datad (242:242:242) (257:257:257))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1162:1162:1162) (978:978:978))
+        (PORT datab (346:346:346) (408:408:408))
+        (PORT datac (302:302:302) (374:374:374))
+        (PORT datad (472:472:472) (419:419:419))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (284:284:284))
+        (PORT datab (270:270:270) (276:276:276))
+        (PORT datac (489:489:489) (416:416:416))
+        (PORT datad (811:811:811) (671:671:671))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (437:437:437))
+        (PORT datab (277:277:277) (286:286:286))
+        (PORT datac (481:481:481) (425:425:425))
+        (PORT datad (939:939:939) (859:859:859))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (389:389:389))
+        (PORT datab (323:323:323) (379:379:379))
+        (PORT datad (298:298:298) (354:354:354))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (416:416:416))
+        (PORT datab (326:326:326) (384:384:384))
+        (PORT datac (285:285:285) (352:352:352))
+        (PORT datad (302:302:302) (367:367:367))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (419:419:419))
+        (PORT datab (267:267:267) (273:273:273))
+        (PORT datad (236:236:236) (248:248:248))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (507:507:507) (444:444:444))
+        (PORT datac (471:471:471) (413:413:413))
+        (PORT datad (307:307:307) (366:366:366))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (562:562:562) (540:540:540))
+        (PORT datab (379:379:379) (455:455:455))
+        (PORT datad (309:309:309) (378:378:378))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1271:1271:1271) (1205:1205:1205))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (905:905:905) (829:829:829))
+        (PORT datab (847:847:847) (774:774:774))
+        (PORT datad (873:873:873) (797:797:797))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (926:926:926) (836:836:836))
+        (PORT datab (922:922:922) (835:835:835))
+        (PORT datad (276:276:276) (330:330:330))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (959:959:959) (850:850:850))
+        (PORT datab (865:865:865) (786:786:786))
+        (PORT datad (853:853:853) (782:782:782))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (917:917:917) (899:899:899))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1162:1162:1162) (980:980:980))
+        (PORT datab (877:877:877) (797:797:797))
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (487:487:487) (418:418:418))
+        (PORT datab (269:269:269) (275:275:275))
+        (PORT datac (225:225:225) (240:240:240))
+        (PORT datad (476:476:476) (401:401:401))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (905:905:905) (834:834:834))
+        (PORT datab (1298:1298:1298) (1148:1148:1148))
+        (PORT datad (293:293:293) (355:355:355))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1561:1561:1561) (1345:1345:1345))
+        (PORT datab (890:890:890) (808:808:808))
+        (PORT datad (531:531:531) (515:515:515))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT asdata (710:710:710) (774:774:774))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT asdata (713:713:713) (778:778:778))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1621:1621:1621) (1512:1512:1512))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (1268:1268:1268) (1171:1171:1171))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (806:806:806))
+        (PORT datab (602:602:602) (564:564:564))
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1275:1275:1275) (1180:1180:1180))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (702:702:702) (763:763:763))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (604:604:604) (555:555:555))
+        (PORT datab (802:802:802) (730:730:730))
+        (PORT datad (276:276:276) (331:331:331))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (377:377:377) (451:451:451))
+        (PORT datac (314:314:314) (383:383:383))
+        (PORT datad (319:319:319) (395:395:395))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (283:283:283))
+        (PORT datab (285:285:285) (298:298:298))
+        (PORT datad (276:276:276) (297:297:297))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (912:912:912) (842:842:842))
+        (PORT datab (325:325:325) (381:381:381))
+        (PORT datac (287:287:287) (354:354:354))
+        (PORT datad (284:284:284) (344:344:344))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1331:1331:1331) (1219:1219:1219))
+        (PORT datad (272:272:272) (290:290:290))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (506:506:506) (444:444:444))
+        (PORT datac (472:472:472) (413:413:413))
+        (PORT datad (307:307:307) (366:366:366))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1954:1954:1954) (1640:1640:1640))
+        (PORT datac (308:308:308) (375:375:375))
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1648:1648:1648) (1549:1549:1549))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1726:1726:1726) (1621:1621:1621))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (731:731:731) (796:796:796))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT asdata (712:712:712) (776:776:776))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT ena (1034:1034:1034) (1005:1005:1005))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT asdata (712:712:712) (777:777:777))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1627:1627:1627) (1478:1478:1478))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (323:323:323) (383:383:383))
+        (PORT datad (1104:1104:1104) (901:901:901))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT asdata (709:709:709) (774:774:774))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (703:703:703) (764:764:764))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1286:1286:1286) (1095:1095:1095))
+        (PORT datab (953:953:953) (837:837:837))
+        (PORT datac (339:339:339) (408:408:408))
+        (PORT datad (264:264:264) (278:278:278))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (405:405:405) (481:481:481))
+        (PORT datac (285:285:285) (351:351:351))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (404:404:404) (481:481:481))
+        (PORT datac (288:288:288) (355:355:355))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (919:919:919) (849:849:849))
+        (PORT datac (359:359:359) (446:446:446))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3765:3765:3765) (3815:3815:3815))
+        (PORT datad (879:879:879) (812:812:812))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (726:726:726) (788:788:788))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3339:3339:3339) (3439:3439:3439))
+        (PORT datab (337:337:337) (397:397:397))
+        (PORT datac (561:561:561) (533:533:533))
+        (PORT datad (889:889:889) (823:823:823))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (424:424:424))
+        (PORT datab (338:338:338) (398:398:398))
+        (PORT datac (517:517:517) (501:501:501))
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (432:432:432))
+        (PORT datab (292:292:292) (306:306:306))
+        (PORT datac (316:316:316) (387:387:387))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT asdata (2039:2039:2039) (1871:1871:1871))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT asdata (971:971:971) (978:978:978))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1632:1632:1632) (1472:1472:1472))
+        (PORT datab (1270:1270:1270) (1090:1090:1090))
+        (PORT datac (290:290:290) (359:359:359))
+        (PORT datad (1169:1169:1169) (1007:1007:1007))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1617:1617:1617) (1456:1456:1456))
+        (PORT datab (1266:1266:1266) (1085:1085:1085))
+        (PORT datac (284:284:284) (351:351:351))
+        (PORT datad (1175:1175:1175) (1013:1013:1013))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1341:1341:1341) (1233:1233:1233))
+        (PORT datab (871:871:871) (768:768:768))
+        (PORT datac (1097:1097:1097) (949:949:949))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1243:1243:1243) (1063:1063:1063))
+        (PORT datab (1266:1266:1266) (1085:1085:1085))
+        (PORT datac (1566:1566:1566) (1407:1407:1407))
+        (PORT datad (288:288:288) (347:347:347))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (421:421:421))
+        (PORT datab (353:353:353) (419:419:419))
+        (PORT datac (293:293:293) (362:362:362))
+        (PORT datad (291:291:291) (352:352:352))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1332:1332:1332) (1220:1220:1220))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (620:620:620) (572:572:572))
+        (PORT datab (828:828:828) (757:757:757))
+        (PORT datac (516:516:516) (501:501:501))
+        (PORT datad (509:509:509) (492:492:492))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1514:1514:1514) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1644:1644:1644) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1676:1676:1676) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (555:555:555) (535:535:535))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (284:284:284) (351:351:351))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (405:405:405))
+        (PORT datab (334:334:334) (394:394:394))
+        (PORT datac (293:293:293) (362:362:362))
+        (PORT datad (292:292:292) (354:354:354))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (400:400:400))
+        (PORT datad (302:302:302) (358:358:358))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1644:1644:1644) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1676:1676:1676) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|start_nedge)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (333:333:333) (395:395:395))
+        (PORT datac (1609:1609:1609) (1442:1442:1442))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (288:288:288) (355:355:355))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (284:284:284) (351:351:351))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3250:3250:3250) (3300:3300:3300))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (325:325:325) (391:391:391))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE rx\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (778:778:778) (803:803:803))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (530:530:530) (517:517:517))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (934:934:934) (865:865:865))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1197:1197:1197) (1078:1078:1078))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (360:360:360))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (517:517:517) (507:507:507))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1434:1434:1434) (1189:1189:1189))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (359:359:359))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (872:872:872) (799:799:799))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (345:345:345))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (283:283:283) (341:341:341))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (285:285:285) (343:343:343))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (284:284:284) (342:342:342))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (345:345:345))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (879:879:879) (812:812:812))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (877:877:877) (810:810:810))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (285:285:285) (343:343:343))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (285:285:285) (343:343:343))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (856:856:856) (784:784:784))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (792:792:792) (695:695:695))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg2\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_clk\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1459:1459:1459) (1377:1377:1377))
+        (IOPATH i o (2882:2882:2882) (2802:2802:2802))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_cs_n\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1830:1830:1830) (1575:1575:1575))
+        (IOPATH i o (2882:2882:2882) (2802:2802:2802))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_mosi\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1773:1773:1773) (1522:1522:1522))
+        (IOPATH i o (2882:2882:2882) (2802:2802:2802))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE tx\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2595:2595:2595) (2962:2962:2962))
+        (IOPATH i o (2961:2961:2961) (3013:3013:3013))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_clk\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (788:788:788) (813:813:813))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2044:2044:2044) (2012:2012:2012))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (354:354:354) (414:414:414))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_rst_n\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (748:748:748) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (3317:3317:3317) (3784:3784:3784))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (4032:4032:4032) (3954:3954:3954))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE rst_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2706:2706:2706) (3154:3154:3154))
+        (PORT datab (3372:3372:3372) (3373:3373:3373))
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE rst_n\~0clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2513:2513:2513) (2225:2225:2225))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (332:332:332) (392:392:392))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sd_miso\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (717:717:717) (741:741:741))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT asdata (4129:4129:4129) (4194:4194:4194))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3765:3765:3765) (3815:3815:3815))
+        (PORT datab (328:328:328) (386:386:386))
+        (PORT datad (512:512:512) (496:496:496))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (614:614:614) (569:569:569))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (823:823:823) (727:727:727))
+        (PORT datad (530:530:530) (512:512:512))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (551:551:551) (538:538:538))
+        (PORT datab (866:866:866) (764:764:764))
+        (PORT datac (821:821:821) (725:725:725))
+        (PORT datad (529:529:529) (512:512:512))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (559:559:559) (466:466:466))
+        (PORT datab (483:483:483) (424:424:424))
+        (PORT datad (243:243:243) (258:258:258))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (392:392:392))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1650:1650:1650) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1635:1635:1635))
+        (PORT sclr (1119:1119:1119) (1185:1185:1185))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (558:558:558) (539:539:539))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (286:286:286) (353:353:353))
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (572:572:572) (556:556:556))
+        (PORT datac (500:500:500) (424:424:424))
+        (PORT datad (298:298:298) (353:353:353))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT asdata (1592:1592:1592) (1474:1474:1474))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT asdata (710:710:710) (775:775:775))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT asdata (934:934:934) (925:925:925))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT asdata (723:723:723) (785:785:785))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT asdata (710:710:710) (775:775:775))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT ena (1566:1566:1566) (1407:1407:1407))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (389:389:389))
+        (PORT datab (325:325:325) (381:381:381))
+        (PORT datad (507:507:507) (492:492:492))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (806:806:806) (682:682:682))
+        (PORT datac (439:439:439) (373:373:373))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (331:331:331) (391:391:391))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (332:332:332) (392:392:392))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (414:414:414))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (364:364:364) (427:427:427))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (432:432:432))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3409:3409:3409) (3573:3573:3573))
+        (PORT datab (916:916:916) (847:847:847))
+        (PORT datac (326:326:326) (399:399:399))
+        (PORT datad (325:325:325) (393:393:393))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (556:556:556) (460:460:460))
+        (PORT datab (269:269:269) (276:276:276))
+        (PORT datad (236:236:236) (247:247:247))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (329:329:329) (389:389:389))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datac (292:292:292) (361:361:361))
+        (PORT datad (305:305:305) (375:375:375))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (275:275:275) (285:285:285))
+        (PORT datac (326:326:326) (399:399:399))
+        (PORT datad (325:325:325) (393:393:393))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (417:417:417))
+        (PORT datab (325:325:325) (382:382:382))
+        (PORT datac (323:323:323) (396:396:396))
+        (PORT datad (323:323:323) (390:390:390))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (426:426:426))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (420:420:420))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT sclr (960:960:960) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (315:315:315) (385:385:385))
+        (PORT datad (318:318:318) (384:384:384))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (1192:1192:1192) (1121:1121:1121))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (703:703:703) (765:765:765))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (281:281:281) (337:337:337))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (700:700:700) (761:761:761))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (702:702:702) (763:763:763))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (702:702:702) (763:763:763))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (700:700:700) (761:761:761))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (287:287:287) (345:345:345))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (287:287:287) (346:346:346))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT asdata (934:934:934) (930:930:930))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (335:335:335))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1671:1671:1671))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1636:1636:1636))
+        (PORT ena (1852:1852:1852) (1626:1626:1626))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (865:865:865) (795:795:795))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (701:701:701) (763:763:763))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (703:703:703) (764:764:764))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (701:701:701) (762:762:762))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (336:336:336))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (703:703:703) (764:764:764))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (704:704:704) (765:765:765))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT asdata (701:701:701) (762:762:762))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (335:335:335))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1647:1647:1647) (1667:1667:1667))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1691:1691:1691) (1644:1644:1644))
+        (PORT ena (1515:1515:1515) (1335:1335:1335))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT asdata (1188:1188:1188) (1101:1101:1101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (363:363:363))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (495:495:495) (478:478:478))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT asdata (928:928:928) (911:911:911))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (544:544:544) (525:525:525))
+        (PORT datad (494:494:494) (477:477:477))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT asdata (916:916:916) (897:897:897))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (283:283:283) (341:341:341))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1666:1666:1666))
+        (PORT asdata (711:711:711) (776:776:776))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (PORT ena (1269:1269:1269) (1167:1167:1167))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (389:389:389))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (286:286:286) (299:299:299))
+        (PORT datad (243:243:243) (257:257:257))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datab (869:869:869) (708:708:708))
+        (PORT datac (304:304:304) (378:378:378))
+        (PORT datad (471:471:471) (418:418:418))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (389:389:389))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (391:391:391))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (337:337:337) (403:403:403))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (555:555:555) (536:536:536))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (283:283:283) (350:350:350))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (275:275:275) (285:285:285))
+        (PORT datac (295:295:295) (366:366:366))
+        (PORT datad (236:236:236) (247:247:247))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (PORT sload (985:985:985) (1051:1051:1051))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sload (posedge clk) (195:195:195))
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (391:391:391))
+        (PORT datab (326:326:326) (384:384:384))
+        (PORT datac (283:283:283) (349:349:349))
+        (PORT datad (285:285:285) (344:344:344))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (408:408:408))
+        (PORT datab (277:277:277) (287:287:287))
+        (PORT datad (237:237:237) (248:248:248))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1646:1646:1646) (1665:1665:1665))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1678:1678:1678) (1631:1631:1631))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (824:824:824) (696:696:696))
+        (PORT datad (779:779:779) (624:624:624))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (520:520:520) (464:464:464))
+        (PORT datac (289:289:289) (357:357:357))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (406:406:406))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (385:385:385))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (393:393:393))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (549:549:549) (543:543:543))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (284:284:284) (350:350:350))
+        (PORT datad (307:307:307) (366:366:366))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (934:934:934) (844:844:844))
+        (PORT datac (837:837:837) (729:729:729))
+        (PORT datad (269:269:269) (284:284:284))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (845:845:845) (900:900:900))
+        (PORT ena (973:973:973) (947:947:947))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (921:921:921))
+        (PORT datab (1068:1068:1068) (990:990:990))
+        (PORT datac (946:946:946) (897:897:897))
+        (PORT datad (975:975:975) (913:913:913))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (830:830:830) (722:722:722))
+        (PORT datad (263:263:263) (277:277:277))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (775:775:775) (648:648:648))
+        (PORT datab (358:358:358) (418:418:418))
+        (PORT datad (518:518:518) (462:462:462))
+        (IOPATH dataa combout (392:392:392) (419:419:419))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1163:1163:1163) (979:979:979))
+        (PORT datab (344:344:344) (407:407:407))
+        (PORT datac (305:305:305) (379:379:379))
+        (PORT datad (469:469:469) (416:416:416))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (777:777:777) (649:649:649))
+        (PORT datab (269:269:269) (276:276:276))
+        (PORT datad (519:519:519) (464:464:464))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (778:778:778) (651:651:651))
+        (PORT datab (351:351:351) (410:410:410))
+        (PORT datad (520:520:520) (465:465:465))
+        (IOPATH dataa combout (392:392:392) (419:419:419))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (427:427:427))
+        (PORT datab (584:584:584) (507:507:507))
+        (PORT datad (812:812:812) (671:671:671))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (416:416:416))
+        (PORT datab (580:580:580) (503:503:503))
+        (PORT datad (806:806:806) (665:665:665))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (416:416:416))
+        (PORT datab (343:343:343) (406:406:406))
+        (PORT datac (299:299:299) (371:371:371))
+        (PORT datad (300:300:300) (355:355:355))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (959:959:959) (817:817:817))
+        (PORT datac (770:770:770) (645:645:645))
+        (PORT datad (308:308:308) (368:368:368))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (512:512:512) (460:460:460))
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (301:301:301) (373:373:373))
+        (PORT datad (810:810:810) (669:669:669))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (358:358:358) (424:424:424))
+        (PORT datab (350:350:350) (409:409:409))
+        (PORT datac (513:513:513) (513:513:513))
+        (PORT datad (315:315:315) (378:378:378))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (880:880:880) (766:766:766))
+        (PORT datab (308:308:308) (321:321:321))
+        (PORT datac (512:512:512) (441:441:441))
+        (IOPATH dataa combout (392:392:392) (419:419:419))
+        (IOPATH datab combout (393:393:393) (431:431:431))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (335:335:335) (398:398:398))
+        (PORT datab (520:520:520) (464:464:464))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (393:393:393) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1678:1678:1678))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (336:336:336) (401:401:401))
+        (PORT datac (781:781:781) (713:713:713))
+        (PORT datad (315:315:315) (377:377:377))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (829:829:829) (727:727:727))
+        (PORT datab (814:814:814) (683:683:683))
+        (PORT datac (227:227:227) (242:242:242))
+        (PORT datad (1154:1154:1154) (971:971:971))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (398:398:398))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (406:406:406))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (337:337:337) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (406:406:406))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (385:385:385))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (555:555:555) (535:535:535))
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datac (301:301:301) (373:373:373))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (335:335:335) (401:401:401))
+        (PORT datac (305:305:305) (371:371:371))
+        (PORT datad (291:291:291) (353:353:353))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (437:437:437))
+        (PORT datab (276:276:276) (286:286:286))
+        (PORT datac (482:482:482) (425:425:425))
+        (PORT datad (939:939:939) (860:860:860))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (468:468:468))
+        (PORT datab (1176:1176:1176) (960:960:960))
+        (PORT datad (243:243:243) (259:259:259))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (286:286:286) (303:303:303))
+        (PORT datab (329:329:329) (387:387:387))
+        (PORT datac (506:506:506) (430:430:430))
+        (IOPATH dataa combout (394:394:394) (400:400:400))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (807:807:807) (694:694:694))
+        (PORT datab (835:835:835) (730:730:730))
+        (PORT datad (1154:1154:1154) (971:971:971))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (576:576:576) (561:561:561))
+        (PORT datab (344:344:344) (407:407:407))
+        (PORT datac (316:316:316) (386:386:386))
+        (PORT datad (300:300:300) (365:365:365))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (389:389:389))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (391:391:391))
+        (PORT datab (547:547:547) (533:533:533))
+        (PORT datac (283:283:283) (348:348:348))
+        (PORT datad (285:285:285) (344:344:344))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (309:309:309))
+        (PORT datab (528:528:528) (432:432:432))
+        (PORT datac (499:499:499) (425:425:425))
+        (PORT datad (555:555:555) (529:529:529))
+        (IOPATH dataa combout (394:394:394) (400:400:400))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (420:420:420))
+        (PORT datab (1597:1597:1597) (1427:1427:1427))
+        (PORT datad (272:272:272) (289:289:289))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (425:425:425))
+        (PORT datac (296:296:296) (366:366:366))
+        (PORT datad (292:292:292) (353:353:353))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1334:1334:1334) (1222:1222:1222))
+        (PORT datac (226:226:226) (241:241:241))
+        (PORT datad (272:272:272) (290:290:290))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (420:420:420))
+        (PORT datac (291:291:291) (361:361:361))
+        (PORT datad (291:291:291) (352:352:352))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (408:408:408))
+        (PORT datad (582:582:582) (583:583:583))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (623:623:623) (626:626:626))
+        (PORT datac (283:283:283) (351:351:351))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (623:623:623) (626:626:626))
+        (PORT datad (495:495:495) (479:479:479))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (624:624:624))
+        (PORT datac (285:285:285) (351:351:351))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (394:394:394))
+        (PORT datab (539:539:539) (522:522:522))
+        (PORT datac (286:286:286) (352:352:352))
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (597:597:597) (550:550:550))
+        (PORT datad (580:580:580) (582:582:582))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (620:620:620) (622:622:622))
+        (PORT datac (287:287:287) (354:354:354))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (621:621:621) (623:623:623))
+        (PORT datac (284:284:284) (350:350:350))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (404:404:404) (481:481:481))
+        (PORT datac (284:284:284) (350:350:350))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (388:388:388))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (515:515:515) (496:496:496))
+        (PORT datad (526:526:526) (498:498:498))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (468:468:468))
+        (PORT datab (278:278:278) (288:288:288))
+        (PORT datac (500:500:500) (432:432:432))
+        (PORT datad (482:482:482) (411:411:411))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (487:487:487) (420:420:420))
+        (PORT datab (871:871:871) (706:706:706))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (393:393:393))
+        (PORT datab (405:405:405) (482:482:482))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (405:405:405) (481:481:481))
+        (PORT datac (286:286:286) (352:352:352))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (393:393:393))
+        (PORT datab (405:405:405) (481:481:481))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (405:405:405) (481:481:481))
+        (PORT datac (287:287:287) (355:355:355))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (390:390:390))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (282:282:282) (348:348:348))
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (559:559:559) (467:467:467))
+        (PORT datab (278:278:278) (288:288:288))
+        (PORT datac (498:498:498) (431:431:431))
+        (PORT datad (482:482:482) (411:411:411))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1330:1330:1330) (1218:1218:1218))
+        (PORT datab (310:310:310) (323:323:323))
+        (PORT datad (272:272:272) (290:290:290))
+        (IOPATH dataa combout (420:420:420) (425:425:425))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1334:1334:1334) (1222:1222:1222))
+        (PORT datab (309:309:309) (323:323:323))
+        (PORT datac (437:437:437) (383:383:383))
+        (PORT datad (314:314:314) (384:384:384))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (407:407:407))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (404:404:404))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (PORT sclr (1465:1465:1465) (1586:1586:1586))
+        (PORT ena (1210:1210:1210) (1105:1105:1105))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (291:291:291) (312:312:312))
+        (PORT datab (308:308:308) (322:322:322))
+        (PORT datac (502:502:502) (492:492:492))
+        (PORT datad (314:314:314) (383:383:383))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (536:536:536) (437:437:437))
+        (PORT datab (615:615:615) (570:570:570))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (502:502:502) (447:447:447))
+        (PORT datab (834:834:834) (730:730:730))
+        (PORT datad (501:501:501) (493:493:493))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (514:514:514) (499:499:499))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datad (513:513:513) (498:498:498))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (322:322:322) (382:382:382))
+        (PORT datac (286:286:286) (353:353:353))
+        (PORT datad (294:294:294) (356:356:356))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (283:283:283))
+        (PORT datab (299:299:299) (310:310:310))
+        (PORT datad (516:516:516) (501:501:501))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (394:394:394))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (534:534:534) (510:510:510))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (331:331:331) (390:390:390))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (553:553:553) (528:528:528))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (332:332:332) (392:392:392))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (390:390:390))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (329:329:329) (387:387:387))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (PORT sclr (959:959:959) (953:953:953))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (393:393:393))
+        (PORT datab (326:326:326) (384:384:384))
+        (PORT datac (284:284:284) (350:350:350))
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (421:421:421))
+        (PORT datab (557:557:557) (533:533:533))
+        (PORT datac (292:292:292) (362:362:362))
+        (PORT datad (295:295:295) (357:357:357))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (282:282:282))
+        (PORT datab (300:300:300) (310:310:310))
+        (PORT datad (251:251:251) (259:259:259))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1681:1681:1681) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (423:423:423))
+        (PORT datab (325:325:325) (382:382:382))
+        (PORT datad (259:259:259) (271:271:271))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT asdata (710:710:710) (775:775:775))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT asdata (931:931:931) (921:921:921))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (390:390:390))
+        (PORT datab (323:323:323) (380:380:380))
+        (PORT datad (299:299:299) (354:354:354))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT asdata (723:723:723) (785:785:785))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (285:285:285) (344:344:344))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT asdata (714:714:714) (781:781:781))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (PORT ena (1522:1522:1522) (1364:1364:1364))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (395:395:395))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datad (511:511:511) (496:496:496))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (873:873:873) (738:738:738))
+        (PORT datad (813:813:813) (687:687:687))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (295:295:295))
+        (PORT datab (1862:1862:1862) (1592:1592:1592))
+        (PORT datad (230:230:230) (237:237:237))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2280:2280:2280) (2002:2002:2002))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (368:368:368) (431:431:431))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (2620:2620:2620) (2938:2938:2938))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (368:368:368) (431:431:431))
+        (PORT datad (311:311:311) (381:381:381))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1689:1689:1689) (1644:1644:1644))
+        (PORT sclr (2620:2620:2620) (2938:2938:2938))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (561:561:561))
+        (PORT datab (371:371:371) (446:446:446))
+        (PORT datac (321:321:321) (394:394:394))
+        (PORT datad (308:308:308) (377:377:377))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1892:1892:1892) (1670:1670:1670))
+        (PORT datad (1100:1100:1100) (900:900:900))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (404:404:404))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (PORT sclr (2461:2461:2461) (2829:2829:2829))
+        (PORT ena (1213:1213:1213) (1111:1111:1111))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1140:1140:1140) (942:942:942))
+        (PORT datab (605:605:605) (557:557:557))
+        (PORT datac (556:556:556) (528:528:528))
+        (PORT datad (514:514:514) (497:497:497))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (543:543:543) (447:447:447))
+        (PORT datab (623:623:623) (580:580:580))
+        (PORT datac (511:511:511) (501:501:501))
+        (PORT datad (250:250:250) (259:259:259))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1189:1189:1189) (1031:1031:1031))
+        (PORT datab (1595:1595:1595) (1376:1376:1376))
+        (PORT datad (458:458:458) (393:393:393))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3810:3810:3810) (3892:3892:3892))
+        (PORT datad (352:352:352) (428:428:428))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (287:287:287) (354:354:354))
+        (PORT datad (352:352:352) (429:429:429))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (288:288:288) (356:356:356))
+        (PORT datad (352:352:352) (428:428:428))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (286:286:286) (352:352:352))
+        (PORT datad (352:352:352) (429:429:429))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (326:326:326) (387:387:387))
+        (PORT datab (328:328:328) (386:386:386))
+        (PORT datac (280:280:280) (346:346:346))
+        (PORT datad (287:287:287) (347:347:347))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (394:394:394))
+        (PORT datad (352:352:352) (428:428:428))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (399:399:399))
+        (PORT datad (352:352:352) (429:429:429))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (286:286:286) (352:352:352))
+        (PORT datad (352:352:352) (429:429:429))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (286:286:286) (352:352:352))
+        (PORT datad (352:352:352) (429:429:429))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1663:1663:1663))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1628:1628:1628))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (558:558:558) (539:539:539))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (282:282:282) (348:348:348))
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (268:268:268) (274:274:274))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1245:1245:1245) (1099:1099:1099))
+        (PORT datab (1160:1160:1160) (964:964:964))
+        (PORT datad (246:246:246) (260:260:260))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (407:407:407))
+        (PORT datad (513:513:513) (505:505:505))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (514:514:514) (506:506:506))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (339:339:339) (406:406:406))
+        (PORT datab (329:329:329) (387:387:387))
+        (PORT datad (516:516:516) (508:508:508))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (328:328:328) (385:385:385))
+        (PORT datac (294:294:294) (366:366:366))
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1627:1627:1627) (1454:1454:1454))
+        (PORT datad (246:246:246) (261:261:261))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1625:1625:1625) (1452:1452:1452))
+        (PORT datab (286:286:286) (299:299:299))
+        (PORT datad (510:510:510) (502:502:502))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (815:815:815) (722:722:722))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (321:321:321) (376:376:376))
+        (PORT datad (814:814:814) (721:721:721))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (824:824:824) (749:749:749))
+        (PORT datab (301:301:301) (312:312:312))
+        (PORT datad (295:295:295) (359:359:359))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1648:1648:1648) (1668:1668:1668))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1680:1680:1680) (1633:1633:1633))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (878:878:878) (767:767:767))
+        (PORT datab (351:351:351) (411:411:411))
+        (PORT datac (784:784:784) (682:682:682))
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (413:413:413))
+        (PORT datab (344:344:344) (406:406:406))
+        (PORT datac (302:302:302) (373:373:373))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (418:418:418))
+        (PORT datab (338:338:338) (398:398:398))
+        (PORT datac (293:293:293) (362:362:362))
+        (PORT datad (294:294:294) (356:356:356))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (881:881:881) (782:782:782))
+        (PORT datab (567:567:567) (553:553:553))
+        (PORT datac (568:568:568) (544:544:544))
+        (PORT datad (481:481:481) (410:410:410))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (284:284:284) (301:301:301))
+        (PORT datab (566:566:566) (551:551:551))
+        (PORT datac (566:566:566) (542:542:542))
+        (PORT datad (485:485:485) (414:414:414))
+        (IOPATH dataa combout (349:349:349) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (295:295:295))
+        (PORT datab (532:532:532) (436:436:436))
+        (PORT datac (226:226:226) (241:241:241))
+        (PORT datad (250:250:250) (259:259:259))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (556:556:556) (461:461:461))
+        (PORT datab (745:745:745) (628:628:628))
+        (PORT datad (227:227:227) (235:235:235))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1690:1690:1690) (1644:1644:1644))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1195:1195:1195) (970:970:970))
+        (PORT datac (275:275:275) (338:338:338))
+        (PORT datad (796:796:796) (716:716:716))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datab (909:909:909) (778:778:778))
+        (PORT datad (850:850:850) (728:728:728))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1694:1694:1694) (1647:1647:1647))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (550:550:550) (542:542:542))
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datac (301:301:301) (373:373:373))
+        (PORT datad (294:294:294) (356:356:356))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (PORT sclr (1475:1475:1475) (1597:1597:1597))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (437:437:437))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (302:302:302) (374:374:374))
+        (PORT datad (296:296:296) (360:360:360))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (436:436:436))
+        (PORT datab (291:291:291) (298:298:298))
+        (PORT datac (228:228:228) (244:244:244))
+        (PORT datad (936:936:936) (855:855:855))
+        (IOPATH dataa combout (377:377:377) (380:380:380))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1675:1675:1675) (1627:1627:1627))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (228:228:228) (244:244:244))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (358:358:358) (434:434:434))
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (388:388:388))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (357:357:357) (419:419:419))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (438:438:438))
+        (PORT datab (269:269:269) (276:276:276))
+        (PORT datad (254:254:254) (271:271:271))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (357:357:357) (433:433:433))
+        (PORT datab (362:362:362) (423:423:423))
+        (PORT datac (228:228:228) (244:244:244))
+        (PORT datad (252:252:252) (269:269:269))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (393:393:393))
+        (PORT datab (325:325:325) (383:383:383))
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (556:556:556) (534:534:534))
+        (PORT datab (324:324:324) (380:380:380))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (554:554:554) (543:543:543))
+        (PORT datab (327:327:327) (385:385:385))
+        (PORT datac (282:282:282) (348:348:348))
+        (PORT datad (283:283:283) (341:341:341))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (401:401:401))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (619:619:619) (571:571:571))
+        (PORT datab (827:827:827) (756:756:756))
+        (PORT datac (516:516:516) (500:500:500))
+        (PORT datad (509:509:509) (491:491:491))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (552:552:552) (461:461:461))
+        (PORT datab (620:620:620) (581:581:581))
+        (PORT datac (494:494:494) (425:425:425))
+        (PORT datad (732:732:732) (582:582:582))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (323:323:323) (383:383:383))
+        (PORT datad (228:228:228) (236:236:236))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (271:271:271) (279:279:279))
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (325:325:325) (382:382:382))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (394:394:394))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (335:335:335) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (334:334:334) (393:393:393))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (396:396:396))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (404:404:404))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1687:1687:1687))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1652:1652:1652))
+        (PORT sclr (1077:1077:1077) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (407:407:407))
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datac (294:294:294) (364:364:364))
+        (PORT datad (293:293:293) (355:355:355))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (806:806:806) (641:641:641))
+        (PORT datab (619:619:619) (579:579:579))
+        (PORT datac (499:499:499) (431:431:431))
+        (PORT datad (441:441:441) (379:379:379))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (295:295:295) (310:310:310))
+        (PORT datac (318:318:318) (398:398:398))
+        (PORT datad (507:507:507) (493:493:493))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1665:1665:1665) (1686:1686:1686))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1697:1697:1697) (1651:1651:1651))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1371:1371:1371) (1289:1289:1289))
+        (PORT clrn (1684:1684:1684) (1640:1640:1640))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (1254:1254:1254) (1155:1155:1155))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1431:1431:1431) (1276:1276:1276))
+        (PORT datab (1310:1310:1310) (1200:1200:1200))
+        (PORT datac (840:840:840) (739:739:739))
+        (PORT datad (1403:1403:1403) (1299:1299:1299))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (311:311:311) (329:329:329))
+        (PORT datad (324:324:324) (391:391:391))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1430:1430:1430) (1276:1276:1276))
+        (PORT datab (1308:1308:1308) (1198:1198:1198))
+        (PORT datac (841:841:841) (739:739:739))
+        (PORT datad (1401:1401:1401) (1297:1297:1297))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (436:436:436))
+        (PORT datab (569:569:569) (549:549:549))
+        (PORT datad (457:457:457) (393:393:393))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (417:417:417))
+        (PORT datab (367:367:367) (430:430:430))
+        (PORT datac (265:265:265) (288:288:288))
+        (PORT datad (324:324:324) (390:390:390))
+        (IOPATH dataa combout (392:392:392) (419:419:419))
+        (IOPATH datab combout (393:393:393) (431:431:431))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (434:434:434))
+        (PORT datad (241:241:241) (255:255:255))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (430:430:430))
+        (PORT datac (326:326:326) (399:399:399))
+        (PORT datad (241:241:241) (254:254:254))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (437:437:437))
+        (PORT datad (235:235:235) (246:246:246))
+        (IOPATH dataa combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1273:1273:1273) (1176:1176:1176))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (276:276:276) (290:290:290))
+        (PORT datad (519:519:519) (509:509:509))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (518:518:518) (502:502:502))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1272:1272:1272) (1121:1121:1121))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (335:335:335))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1232:1232:1232) (1086:1086:1086))
+        (PORT datab (953:953:953) (862:862:862))
+        (PORT datad (295:295:295) (359:359:359))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (527:527:527))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1269:1269:1269) (1114:1114:1114))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (531:531:531) (508:508:508))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (335:335:335))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (294:294:294) (313:313:313))
+        (PORT datab (357:357:357) (418:418:418))
+        (PORT datad (525:525:525) (500:500:500))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (534:534:534) (513:513:513))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT asdata (1298:1298:1298) (1219:1219:1219))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (782:782:782) (682:682:682))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT asdata (701:701:701) (763:763:763))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT asdata (750:750:750) (821:821:821))
+        (PORT ena (1589:1589:1589) (1445:1445:1445))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (946:946:946) (886:886:886))
+        (PORT datab (346:346:346) (404:404:404))
+        (PORT datad (930:930:930) (879:879:879))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT asdata (747:747:747) (819:819:819))
+        (PORT ena (1589:1589:1589) (1445:1445:1445))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (969:969:969) (944:944:944))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (827:827:827) (771:771:771))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (491:491:491) (478:478:478))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (920:920:920) (901:901:901))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (576:576:576) (547:547:547))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1637:1637:1637) (1503:1503:1503))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (644:644:644) (601:601:601))
+        (PORT datab (976:976:976) (891:891:891))
+        (PORT datad (284:284:284) (342:342:342))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (280:280:280))
+        (PORT datab (848:848:848) (703:703:703))
+        (PORT datac (433:433:433) (378:378:378))
+        (PORT datad (794:794:794) (667:667:667))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (283:283:283))
+        (PORT datab (1398:1398:1398) (1257:1257:1257))
+        (PORT datac (1225:1225:1225) (1065:1065:1065))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (558:558:558))
+        (PORT datab (367:367:367) (431:431:431))
+        (PORT datad (861:861:861) (755:755:755))
+        (IOPATH dataa combout (377:377:377) (377:377:377))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1410:1410:1410) (1273:1273:1273))
+        (PORT datab (367:367:367) (431:431:431))
+        (PORT datac (322:322:322) (386:386:386))
+        (PORT datad (1253:1253:1253) (1147:1147:1147))
+        (IOPATH dataa combout (420:420:420) (450:450:450))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (432:432:432))
+        (PORT datad (233:233:233) (244:244:244))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1333:1333:1333) (1216:1216:1216))
+        (PORT datad (1237:1237:1237) (1116:1116:1116))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (415:415:415))
+        (PORT datab (365:365:365) (428:428:428))
+        (PORT datac (268:268:268) (291:291:291))
+        (PORT datad (324:324:324) (391:391:391))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (229:229:229) (237:237:237))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (433:433:433))
+        (PORT datab (368:368:368) (431:431:431))
+        (PORT datac (325:325:325) (398:398:398))
+        (PORT datad (548:548:548) (549:549:549))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1589:1589:1589) (1445:1445:1445))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (320:320:320) (375:375:375))
+        (PORT datac (278:278:278) (341:341:341))
+        (PORT datad (1258:1258:1258) (1143:1143:1143))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (368:368:368) (431:431:431))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1145:1145:1145) (1018:1018:1018))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (916:916:916) (909:909:909))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1369:1369:1369) (1281:1281:1281))
+        (PORT ena (1663:1663:1663) (1506:1506:1506))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (739:739:739) (808:808:808))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (529:529:529) (503:503:503))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (969:969:969) (866:866:866))
+        (PORT datab (904:904:904) (823:823:823))
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (295:295:295))
+        (PORT datab (318:318:318) (372:372:372))
+        (PORT datad (235:235:235) (245:245:245))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (278:278:278) (294:294:294))
+        (PORT datab (885:885:885) (726:726:726))
+        (PORT datad (234:234:234) (244:244:244))
+        (IOPATH dataa combout (394:394:394) (400:400:400))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (892:892:892) (785:785:785))
+        (PORT datab (865:865:865) (774:774:774))
+        (PORT datac (727:727:727) (605:605:605))
+        (PORT datad (492:492:492) (475:475:475))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (553:553:553))
+        (PORT datab (358:358:358) (419:419:419))
+        (PORT datac (530:530:530) (519:519:519))
+        (PORT datad (250:250:250) (268:268:268))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (370:370:370) (434:434:434))
+        (PORT datad (241:241:241) (254:254:254))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (553:553:553))
+        (PORT datab (369:369:369) (432:432:432))
+        (PORT datac (331:331:331) (398:398:398))
+        (PORT datad (513:513:513) (503:503:503))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1514:1514:1514) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (896:896:896) (789:789:789))
+        (PORT datab (360:360:360) (422:422:422))
+        (PORT datac (827:827:827) (745:745:745))
+        (PORT datad (315:315:315) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (450:450:450))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1514:1514:1514) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (324:324:324) (383:383:383))
+        (PORT datab (321:321:321) (376:376:376))
+        (PORT datac (279:279:279) (342:342:342))
+        (IOPATH dataa combout (420:420:420) (450:450:450))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1514:1514:1514) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (833:833:833) (769:769:769))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1313:1313:1313) (1211:1211:1211))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (PORT datab (348:348:348) (405:405:405))
+        (PORT datac (529:529:529) (459:459:459))
+        (PORT datad (832:832:832) (768:768:768))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (693:693:693) (573:573:573))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (420:420:420))
+        (PORT datad (250:250:250) (269:269:269))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (553:553:553))
+        (PORT datab (359:359:359) (421:421:421))
+        (PORT datac (530:530:530) (518:518:518))
+        (PORT datad (251:251:251) (270:270:270))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (234:234:234))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (571:571:571))
+        (PORT datab (368:368:368) (432:432:432))
+        (PORT datad (242:242:242) (256:256:256))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (368:368:368) (432:432:432))
+        (PORT datac (327:327:327) (394:394:394))
+        (PORT datad (241:241:241) (254:254:254))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (561:561:561) (549:549:549))
+        (PORT datad (235:235:235) (247:247:247))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (991:991:991) (961:961:961))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1576:1576:1576) (1444:1444:1444))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (704:704:704) (766:766:766))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (700:700:700) (761:761:761))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (296:296:296) (365:365:365))
+        (PORT datad (301:301:301) (366:366:366))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (429:429:429))
+        (PORT datab (372:372:372) (436:436:436))
+        (PORT datad (240:240:240) (254:254:254))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1657:1657:1657) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT asdata (1390:1390:1390) (1327:1327:1327))
+        (PORT ena (1495:1495:1495) (1350:1350:1350))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1239:1239:1239) (1118:1118:1118))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1662:1662:1662))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1594:1594:1594) (1459:1459:1459))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1293:1293:1293) (1143:1143:1143))
+        (PORT datac (332:332:332) (400:400:400))
+        (PORT datad (1165:1165:1165) (1028:1028:1028))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (393:393:393))
+        (PORT datab (324:324:324) (380:380:380))
+        (PORT datac (289:289:289) (357:357:357))
+        (PORT datad (296:296:296) (360:360:360))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1363:1363:1363) (1245:1245:1245))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1663:1663:1663) (1506:1506:1506))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1290:1290:1290) (1141:1141:1141))
+        (PORT datab (1204:1204:1204) (1064:1064:1064))
+        (PORT datac (329:329:329) (397:397:397))
+        (PORT datad (910:910:910) (843:843:843))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (307:307:307) (374:374:374))
+        (PORT datad (803:803:803) (701:701:701))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1401:1401:1401) (1273:1273:1273))
+        (PORT datac (310:310:310) (377:377:377))
+        (PORT datad (801:801:801) (698:698:698))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1754:1754:1754) (1626:1626:1626))
+        (PORT ena (1663:1663:1663) (1506:1506:1506))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1401:1401:1401) (1273:1273:1273))
+        (PORT datab (1599:1599:1599) (1414:1414:1414))
+        (PORT datac (306:306:306) (372:372:372))
+        (PORT datad (801:801:801) (699:699:699))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (521:521:521) (512:512:512))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT asdata (1251:1251:1251) (1193:1193:1193))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (788:788:788) (688:688:688))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (331:331:331))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT asdata (993:993:993) (965:965:965))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT asdata (1599:1599:1599) (1451:1451:1451))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (836:836:836) (715:715:715))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT asdata (703:703:703) (765:765:765))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (PORT datab (534:534:534) (519:519:519))
+        (PORT datac (305:305:305) (372:372:372))
+        (PORT datad (1531:1531:1531) (1264:1264:1264))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (870:870:870) (765:765:765))
+        (PORT datad (717:717:717) (597:597:597))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT asdata (1676:1676:1676) (1573:1573:1573))
+        (PORT ena (1663:1663:1663) (1506:1506:1506))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (285:285:285) (302:302:302))
+        (PORT datac (316:316:316) (387:387:387))
+        (PORT datad (534:534:534) (521:521:521))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (589:589:589) (503:503:503))
+        (PORT datab (351:351:351) (409:409:409))
+        (PORT datad (834:834:834) (770:770:770))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (809:809:809) (720:720:720))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1676:1676:1676))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1513:1513:1513) (1328:1328:1328))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1136:1136:1136) (1003:1003:1003))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1675:1675:1675))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT asdata (1233:1233:1233) (1119:1119:1119))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (843:843:843) (736:736:736))
+        (PORT datab (337:337:337) (397:397:397))
+        (PORT datac (334:334:334) (401:401:401))
+        (PORT datad (255:255:255) (266:266:266))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (840:840:840) (737:737:737))
+        (PORT datab (1170:1170:1170) (1026:1026:1026))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (874:874:874) (804:804:804))
+        (PORT datab (589:589:589) (544:544:544))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (539:539:539) (531:531:531))
+        (PORT datab (931:931:931) (827:827:827))
+        (IOPATH dataa combout (420:420:420) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (599:599:599) (554:554:554))
+        (PORT datab (857:857:857) (791:791:791))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (320:320:320) (379:379:379))
+        (PORT datab (520:520:520) (499:499:499))
+        (IOPATH dataa combout (414:414:414) (450:450:450))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (321:321:321) (381:381:381))
+        (PORT datad (516:516:516) (487:487:487))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (480:480:480) (425:425:425))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (226:226:226) (242:242:242))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datab (1912:1912:1912) (1696:1696:1696))
+        (PORT datac (226:226:226) (241:241:241))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (284:284:284))
+        (PORT datab (270:270:270) (277:277:277))
+        (PORT datac (224:224:224) (239:239:239))
+        (PORT datad (225:225:225) (232:232:232))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1957:1957:1957) (1644:1644:1644))
+        (PORT datab (350:350:350) (408:408:408))
+        (PORT datac (1576:1576:1576) (1408:1408:1408))
+        (PORT datad (814:814:814) (699:699:699))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (296:296:296))
+        (PORT datab (874:874:874) (739:739:739))
+        (PORT datac (225:225:225) (240:240:240))
+        (PORT datad (815:815:815) (690:690:690))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1649:1649:1649) (1669:1669:1669))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1682:1682:1682) (1634:1634:1634))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (406:406:406))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (407:407:407))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (403:403:403))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (419:419:419))
+        (PORT datab (345:345:345) (408:408:408))
+        (PORT datac (300:300:300) (371:371:371))
+        (PORT datad (301:301:301) (366:366:366))
+        (IOPATH dataa combout (420:420:420) (425:425:425))
+        (IOPATH datab combout (423:423:423) (425:425:425))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (403:403:403))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (PORT sclr (2316:2316:2316) (2582:2582:2582))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (303:303:303) (377:377:377))
+        (PORT datad (301:301:301) (367:367:367))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (405:405:405))
+        (PORT datac (300:300:300) (371:371:371))
+        (PORT datad (298:298:298) (362:362:362))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (270:270:270) (281:281:281))
+        (PORT datab (342:342:342) (405:405:405))
+        (PORT datac (303:303:303) (378:378:378))
+        (PORT datad (236:236:236) (247:247:247))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (283:283:283))
+        (PORT datab (484:484:484) (425:425:425))
+        (PORT datac (1901:1901:1901) (1690:1690:1690))
+        (PORT datad (772:772:772) (643:643:643))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (880:880:880) (801:801:801))
+        (PORT datab (1942:1942:1942) (1721:1721:1721))
+        (PORT datac (1892:1892:1892) (1670:1670:1670))
+        (PORT datad (517:517:517) (500:500:500))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (281:281:281))
+        (PORT datab (1944:1944:1944) (1723:1723:1723))
+        (PORT datac (225:225:225) (240:240:240))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1664:1664:1664) (1685:1685:1685))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1696:1696:1696) (1650:1650:1650))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (878:878:878) (767:767:767))
+        (PORT datab (914:914:914) (824:824:824))
+        (PORT datac (1643:1643:1643) (1466:1466:1466))
+        (PORT datad (312:312:312) (374:374:374))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (826:826:826) (752:752:752))
+        (PORT datac (863:863:863) (794:794:794))
+        (PORT datad (226:226:226) (232:232:232))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2044:2044:2044) (2012:2012:2012))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (881:881:881) (827:827:827))
+        (PORT datab (324:324:324) (380:380:380))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (392:392:392))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (283:283:283) (348:348:348))
+        (PORT datad (283:283:283) (341:341:341))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (857:857:857) (793:793:793))
+        (PORT datab (859:859:859) (679:679:679))
+        (PORT datac (871:871:871) (791:791:791))
+        (PORT datad (903:903:903) (802:802:802))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (399:399:399))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (410:410:410))
+        (PORT datab (337:337:337) (397:397:397))
+        (PORT datac (295:295:295) (364:364:364))
+        (PORT datad (295:295:295) (358:358:358))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (938:938:938) (840:840:840))
+        (PORT datac (879:879:879) (803:803:803))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (908:908:908) (824:824:824))
+        (PORT datab (278:278:278) (289:289:289))
+        (PORT datac (797:797:797) (670:670:670))
+        (PORT datad (228:228:228) (235:235:235))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (332:332:332) (391:391:391))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (335:335:335) (396:396:396))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (396:396:396))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (404:404:404))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1426:1426:1426) (1369:1369:1369))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (409:409:409))
+        (PORT datab (336:336:336) (397:397:397))
+        (PORT datac (295:295:295) (364:364:364))
+        (PORT datad (295:295:295) (358:358:358))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (939:939:939) (841:841:841))
+        (PORT datab (932:932:932) (838:838:838))
+        (PORT datac (1099:1099:1099) (885:885:885))
+        (PORT datad (238:238:238) (250:250:250))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1152:1152:1152) (1026:1026:1026))
+        (PORT datad (1147:1147:1147) (1004:1004:1004))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (296:296:296))
+        (PORT datab (1210:1210:1210) (1047:1047:1047))
+        (PORT datac (332:332:332) (417:417:417))
+        (PORT datad (292:292:292) (355:355:355))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1153:1153:1153) (1026:1026:1026))
+        (PORT datab (1213:1213:1213) (1051:1051:1051))
+        (PORT datad (276:276:276) (297:297:297))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1666:1666:1666) (1684:1684:1684))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1698:1698:1698) (1649:1649:1649))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (318:318:318) (340:340:340))
+        (PORT datab (376:376:376) (451:451:451))
+        (PORT datad (247:247:247) (262:262:262))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1666:1666:1666) (1684:1684:1684))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1698:1698:1698) (1649:1649:1649))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (538:538:538))
+        (PORT datab (336:336:336) (396:396:396))
+        (PORT datac (335:335:335) (421:421:421))
+        (PORT datad (325:325:325) (401:401:401))
+        (IOPATH dataa combout (377:377:377) (392:392:392))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (318:318:318) (340:340:340))
+        (PORT datab (287:287:287) (300:300:300))
+        (PORT datad (229:229:229) (236:236:236))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH datab combout (423:423:423) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1666:1666:1666) (1684:1684:1684))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1698:1698:1698) (1649:1649:1649))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (338:338:338) (393:393:393))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (401:401:401))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (394:394:394))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (620:620:620) (575:575:575))
+        (PORT datac (829:829:829) (742:742:742))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT asdata (1594:1594:1594) (1462:1462:1462))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (322:322:322) (379:379:379))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (323:323:323) (380:380:380))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (324:324:324) (380:380:380))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (393:393:393))
+        (PORT datab (328:328:328) (385:385:385))
+        (PORT datac (284:284:284) (350:350:350))
+        (PORT datad (287:287:287) (345:345:345))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (325:325:325) (382:382:382))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (389:389:389))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1653:1653:1653) (1673:1673:1673))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1685:1685:1685) (1638:1638:1638))
+        (PORT sclr (1443:1443:1443) (1567:1567:1567))
+        (PORT ena (1557:1557:1557) (1415:1415:1415))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (394:394:394))
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (284:284:284) (350:350:350))
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (488:488:488) (420:420:420))
+        (PORT datab (268:268:268) (275:275:275))
+        (PORT datac (225:225:225) (240:240:240))
+        (PORT datad (820:820:820) (697:697:697))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1274:1274:1274) (1139:1139:1139))
+        (PORT datab (321:321:321) (376:376:376))
+        (PORT datad (1015:1015:1015) (839:839:839))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (618:618:618) (570:570:570))
+        (PORT datab (560:560:560) (536:536:536))
+        (PORT datac (511:511:511) (501:501:501))
+        (PORT datad (543:543:543) (514:514:514))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (293:293:293))
+        (PORT datab (270:270:270) (277:277:277))
+        (PORT datac (298:298:298) (361:361:361))
+        (PORT datad (227:227:227) (235:235:235))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (338:338:338) (393:393:393))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (393:393:393))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (614:614:614) (565:565:565))
+        (PORT datab (557:557:557) (533:533:533))
+        (PORT datac (507:507:507) (497:497:497))
+        (PORT datad (539:539:539) (511:511:511))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (395:395:395))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (402:402:402))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (394:394:394))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (553:553:553) (534:534:534))
+        (PORT datab (543:543:543) (522:522:522))
+        (PORT datac (510:510:510) (491:491:491))
+        (PORT datad (536:536:536) (506:506:506))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1654:1654:1654) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT sclr (1064:1064:1064) (1056:1056:1056))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (811:811:811) (730:730:730))
+        (PORT datab (601:601:601) (551:551:551))
+        (PORT datac (761:761:761) (685:685:685))
+        (PORT datad (503:503:503) (484:484:484))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1483:1483:1483) (1295:1295:1295))
+        (PORT datab (542:542:542) (521:521:521))
+        (PORT datac (227:227:227) (242:242:242))
+        (PORT datad (226:226:226) (233:233:233))
+        (IOPATH dataa combout (351:351:351) (371:371:371))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (620:620:620) (575:575:575))
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (829:829:829) (742:742:742))
+        (PORT datad (235:235:235) (246:246:246))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (281:281:281))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (419:419:419))
+        (PORT datac (329:329:329) (406:406:406))
+        (PORT datad (240:240:240) (254:254:254))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (419:419:419))
+        (PORT datad (233:233:233) (243:243:243))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (769:769:769))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1275:1275:1275) (1180:1180:1180))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (793:793:793))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (883:883:883) (815:815:815))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1065:1065:1065) (1040:1040:1040))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (1255:1255:1255) (1180:1180:1180))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT asdata (1332:1332:1332) (1263:1263:1263))
+        (PORT ena (1320:1320:1320) (1212:1212:1212))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (847:847:847) (759:759:759))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1231:1231:1231) (1088:1088:1088))
+        (PORT datab (341:341:341) (397:397:397))
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (576:576:576) (561:561:561))
+        (PORT datab (345:345:345) (407:407:407))
+        (PORT datac (317:317:317) (387:387:387))
+        (PORT datad (300:300:300) (365:365:365))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (290:290:290) (311:311:311))
+        (PORT datab (469:469:469) (403:403:403))
+        (PORT datac (501:501:501) (428:428:428))
+        (PORT datad (554:554:554) (528:528:528))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datab combout (357:357:357) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1332:1332:1332) (1220:1220:1220))
+        (PORT datab (351:351:351) (417:417:417))
+        (PORT datac (473:473:473) (410:410:410))
+        (PORT datad (259:259:259) (270:270:270))
+        (IOPATH dataa combout (394:394:394) (400:400:400))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1652:1652:1652) (1672:1672:1672))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1684:1684:1684) (1637:1637:1637))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (1372:1372:1372) (1285:1285:1285))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (703:703:703) (764:764:764))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (831:831:831) (764:764:764))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1599:1599:1599) (1424:1424:1424))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT asdata (726:726:726) (788:788:788))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (539:539:539) (512:512:512))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (565:565:565) (561:561:561))
+        (PORT datab (612:612:612) (568:568:568))
+        (PORT datad (276:276:276) (331:331:331))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (905:905:905) (825:825:825))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT asdata (1797:1797:1797) (1601:1601:1601))
+        (PORT ena (1275:1275:1275) (1180:1180:1180))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (355:355:355))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT asdata (1346:1346:1346) (1253:1253:1253))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (417:417:417))
+        (PORT datab (357:357:357) (418:418:418))
+        (PORT datac (497:497:497) (424:424:424))
+        (PORT datad (313:313:313) (376:376:376))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1285:1285:1285) (1094:1094:1094))
+        (PORT datab (956:956:956) (840:840:840))
+        (PORT datad (264:264:264) (278:278:278))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (577:577:577) (549:549:549))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1063:1063:1063) (1037:1037:1037))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (819:819:819) (734:734:734))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (911:911:911) (822:822:822))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (927:927:927) (838:838:838))
+        (PORT datab (535:535:535) (525:525:525))
+        (PORT datad (276:276:276) (331:331:331))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (787:787:787) (723:723:723))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT asdata (723:723:723) (785:785:785))
+        (PORT ena (1320:1320:1320) (1212:1212:1212))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (301:301:301) (357:357:357))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (311:311:311) (370:370:370))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1320:1320:1320) (1212:1212:1212))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (354:354:354))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (335:335:335))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (539:539:539) (532:532:532))
+        (PORT datab (862:862:862) (796:796:796))
+        (PORT datad (276:276:276) (331:331:331))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (281:281:281))
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (226:226:226) (241:241:241))
+        (PORT datad (819:819:819) (676:676:676))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (278:278:278) (288:288:288))
+        (PORT datac (1784:1784:1784) (1562:1562:1562))
+        (PORT datad (235:235:235) (246:246:246))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (793:793:793))
+        (PORT datab (360:360:360) (421:421:421))
+        (PORT datad (759:759:759) (646:646:646))
+        (IOPATH dataa combout (377:377:377) (377:377:377))
+        (IOPATH datab combout (380:380:380) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (925:925:925) (850:850:850))
+        (PORT datab (550:550:550) (538:538:538))
+        (PORT datac (281:281:281) (301:301:301))
+        (PORT datad (877:877:877) (808:808:808))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (927:927:927) (838:838:838))
+        (PORT datab (834:834:834) (767:767:767))
+        (PORT datad (770:770:770) (646:646:646))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (835:835:835) (768:768:768))
+        (PORT datad (771:771:771) (646:646:646))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (839:839:839) (738:738:738))
+        (PORT datab (931:931:931) (854:854:854))
+        (PORT datac (805:805:805) (739:739:739))
+        (PORT datad (448:448:448) (385:385:385))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (966:966:966) (863:863:863))
+        (PORT datad (239:239:239) (252:252:252))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (889:889:889) (825:825:825))
+        (PORT datab (347:347:347) (410:410:410))
+        (PORT datac (307:307:307) (381:381:381))
+        (PORT datad (907:907:907) (827:827:827))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (968:968:968) (867:867:867))
+        (PORT datac (306:306:306) (379:379:379))
+        (PORT datad (243:243:243) (256:256:256))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (407:407:407))
+        (PORT datad (235:235:235) (246:246:246))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (497:497:497) (490:490:490))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (926:926:926) (837:837:837))
+        (PORT datab (360:360:360) (421:421:421))
+        (PORT datac (302:302:302) (366:366:366))
+        (PORT datad (794:794:794) (731:731:731))
+        (IOPATH dataa combout (420:420:420) (450:450:450))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (320:320:320) (374:374:374))
+        (PORT datac (278:278:278) (342:342:342))
+        (PORT datad (839:839:839) (766:766:766))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1829:1829:1829) (1602:1602:1602))
+        (PORT datab (279:279:279) (290:290:290))
+        (PORT datac (506:506:506) (503:503:503))
+        (PORT datad (236:236:236) (247:247:247))
+        (IOPATH dataa combout (408:408:408) (425:425:425))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (925:925:925) (849:849:849))
+        (PORT datab (942:942:942) (853:853:853))
+        (PORT datad (227:227:227) (235:235:235))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (415:415:415))
+        (PORT datab (830:830:830) (762:762:762))
+        (PORT datac (775:775:775) (635:635:635))
+        (PORT datad (859:859:859) (787:787:787))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (226:226:226) (234:234:234))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (413:413:413))
+        (PORT datab (965:965:965) (864:864:864))
+        (PORT datad (239:239:239) (252:252:252))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (408:408:408))
+        (PORT datad (235:235:235) (245:245:245))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT asdata (923:923:923) (913:913:913))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT asdata (723:723:723) (785:785:785))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (1178:1178:1178) (1090:1090:1090))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (700:700:700) (761:761:761))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (288:288:288) (346:346:346))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (779:779:779) (698:698:698))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (281:281:281) (336:336:336))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (280:280:280) (336:336:336))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (808:808:808) (737:737:737))
+        (PORT datab (598:598:598) (547:547:547))
+        (PORT datad (771:771:771) (679:679:679))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT asdata (1263:1263:1263) (1184:1184:1184))
+        (PORT ena (1275:1275:1275) (1180:1180:1180))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (302:302:302) (368:368:368))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (808:808:808) (719:719:719))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT asdata (702:702:702) (763:763:763))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1663:1663:1663) (1680:1680:1680))
+        (PORT asdata (729:729:729) (800:800:800))
+        (PORT ena (1214:1214:1214) (1110:1110:1110))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (810:810:810) (714:714:714))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT asdata (701:701:701) (762:762:762))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (278:278:278) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1694:1694:1694))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (327:327:327) (388:388:388))
+        (PORT datab (556:556:556) (529:529:529))
+        (PORT datad (276:276:276) (331:331:331))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (431:431:431))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (518:518:518) (507:507:507))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (929:929:929) (856:856:856))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1682:1682:1682))
+        (PORT asdata (703:703:703) (765:765:765))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (859:859:859) (787:787:787))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1682:1682:1682))
+        (PORT asdata (1526:1526:1526) (1374:1374:1374))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (277:277:277) (332:332:332))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1658:1658:1658) (1682:1682:1682))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (888:888:888) (791:791:791))
+        (PORT datab (1149:1149:1149) (984:984:984))
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (282:282:282))
+        (PORT datab (267:267:267) (274:274:274))
+        (PORT datac (439:439:439) (375:375:375))
+        (PORT datad (758:758:758) (625:625:625))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1096:1096:1096) (897:897:897))
+        (PORT datab (1772:1772:1772) (1505:1505:1505))
+        (PORT datac (232:232:232) (250:250:250))
+        (PORT datad (235:235:235) (246:246:246))
+        (IOPATH dataa combout (394:394:394) (400:400:400))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1359:1359:1359) (1260:1260:1260))
+        (PORT datab (956:956:956) (871:871:871))
+        (PORT datac (1153:1153:1153) (1031:1031:1031))
+        (PORT datad (809:809:809) (683:683:683))
+        (IOPATH dataa combout (377:377:377) (371:371:371))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (229:229:229) (237:237:237))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (845:845:845) (744:744:744))
+        (PORT datad (305:305:305) (364:364:364))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1284:1284:1284) (1093:1093:1093))
+        (PORT datab (956:956:956) (840:840:840))
+        (PORT datac (335:335:335) (404:404:404))
+        (PORT datad (263:263:263) (278:278:278))
+        (IOPATH dataa combout (349:349:349) (377:377:377))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (445:445:445))
+        (PORT datad (242:242:242) (256:256:256))
+        (IOPATH dataa combout (375:375:375) (392:392:392))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (377:377:377) (450:450:450))
+        (PORT datab (360:360:360) (421:421:421))
+        (PORT datad (239:239:239) (252:252:252))
+        (IOPATH dataa combout (373:373:373) (380:380:380))
+        (IOPATH datab combout (377:377:377) (380:380:380))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (423:423:423))
+        (PORT datad (234:234:234) (244:244:244))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (404:404:404))
+        (PORT datad (299:299:299) (354:354:354))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1230:1230:1230) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (446:446:446))
+        (PORT datab (359:359:359) (421:421:421))
+        (PORT datac (339:339:339) (408:408:408))
+        (PORT datad (317:317:317) (381:381:381))
+        (IOPATH dataa combout (435:435:435) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1230:1230:1230) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (416:416:416))
+        (PORT datab (953:953:953) (837:837:837))
+        (PORT datac (318:318:318) (390:390:390))
+        (PORT datad (1219:1219:1219) (1046:1046:1046))
+        (IOPATH dataa combout (420:420:420) (450:450:450))
+        (IOPATH datab combout (423:423:423) (453:453:453))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1230:1230:1230) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (320:320:320) (375:375:375))
+        (PORT datac (278:278:278) (341:341:341))
+        (PORT datad (487:487:487) (469:469:469))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1230:1230:1230) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (315:315:315) (377:377:377))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1230:1230:1230) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (560:560:560) (471:471:471))
+        (PORT datab (362:362:362) (423:423:423))
+        (PORT datad (313:313:313) (376:376:376))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1671:1671:1671) (1692:1692:1692))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1662:1662:1662) (1680:1680:1680))
+        (PORT asdata (1738:1738:1738) (1642:1642:1642))
+        (PORT ena (1320:1320:1320) (1212:1212:1212))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (421:421:421))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT asdata (702:702:702) (763:763:763))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (1232:1232:1232) (1134:1134:1134))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (1208:1208:1208) (1127:1127:1127))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT asdata (913:913:913) (902:902:902))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (279:279:279) (334:334:334))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1672:1672:1672) (1693:1693:1693))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (887:887:887) (771:771:771))
+        (PORT datab (918:918:918) (788:788:788))
+        (PORT datad (275:275:275) (330:330:330))
+        (IOPATH dataa combout (435:435:435) (419:419:419))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1771:1771:1771) (1503:1503:1503))
+        (PORT datac (236:236:236) (254:254:254))
+        (PORT datad (233:233:233) (243:243:243))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3766:3766:3766) (3815:3815:3815))
+        (PORT datab (1188:1188:1188) (1017:1017:1017))
+        (PORT datac (1223:1223:1223) (1112:1112:1112))
+        (PORT datad (858:858:858) (759:759:759))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1290:1290:1290) (1184:1184:1184))
+        (PORT datad (897:897:897) (826:826:826))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1329:1329:1329) (1217:1217:1217))
+        (PORT datab (347:347:347) (413:413:413))
+        (PORT datac (472:472:472) (410:410:410))
+        (PORT datad (259:259:259) (271:271:271))
+        (IOPATH dataa combout (428:428:428) (450:450:450))
+        (IOPATH datab combout (400:400:400) (391:391:391))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1270:1270:1270) (1155:1155:1155))
+        (PORT datab (901:901:901) (798:798:798))
+        (PORT datac (1135:1135:1135) (983:983:983))
+        (PORT datad (300:300:300) (355:355:355))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1268:1268:1268) (1152:1152:1152))
+        (PORT datab (899:899:899) (796:796:796))
+        (PORT datac (1138:1138:1138) (986:986:986))
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1267:1267:1267) (1151:1151:1151))
+        (PORT datab (898:898:898) (795:795:795))
+        (PORT datac (1140:1140:1140) (989:989:989))
+        (PORT datad (301:301:301) (357:357:357))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1267:1267:1267) (1151:1151:1151))
+        (PORT datab (899:899:899) (795:795:795))
+        (PORT datac (1140:1140:1140) (989:989:989))
+        (PORT datad (300:300:300) (356:356:356))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1266:1266:1266) (1150:1150:1150))
+        (PORT datab (898:898:898) (795:795:795))
+        (PORT datac (1141:1141:1141) (990:990:990))
+        (PORT datad (301:301:301) (356:356:356))
+        (IOPATH dataa combout (375:375:375) (371:371:371))
+        (IOPATH datab combout (384:384:384) (386:386:386))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1651:1651:1651) (1670:1670:1670))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1683:1683:1683) (1635:1635:1635))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1242:1242:1242) (1061:1061:1061))
+        (PORT datab (1267:1267:1267) (1087:1087:1087))
+        (PORT datac (1572:1572:1572) (1413:1413:1413))
+        (PORT datad (882:882:882) (811:811:811))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1242:1242:1242) (1061:1061:1061))
+        (PORT datab (1267:1267:1267) (1087:1087:1087))
+        (PORT datac (1571:1571:1571) (1412:1412:1412))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1622:1622:1622) (1461:1461:1461))
+        (PORT datab (1267:1267:1267) (1087:1087:1087))
+        (PORT datac (286:286:286) (354:354:354))
+        (PORT datad (1173:1173:1173) (1011:1011:1011))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1582:1582:1582) (1424:1424:1424))
+        (PORT datad (287:287:287) (345:345:345))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (310:310:310) (371:371:371))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1661:1661:1661) (1679:1679:1679))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1506:1506:1506) (1346:1346:1346))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (353:353:353))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (229:229:229) (236:236:236))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1673:1673:1673) (1695:1695:1695))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT ena (1599:1599:1599) (1424:1424:1424))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (286:286:286) (346:346:346))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (957:957:957) (867:867:867))
+        (PORT datac (1296:1296:1296) (1191:1191:1191))
+        (IOPATH datab combout (423:423:423) (391:391:391))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1291:1291:1291) (1185:1185:1185))
+        (PORT datad (857:857:857) (794:794:794))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1305:1305:1305) (1200:1200:1200))
+        (PORT datad (897:897:897) (825:825:825))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1303:1303:1303) (1198:1198:1198))
+        (PORT datad (909:909:909) (836:836:836))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1572:1572:1572) (1414:1414:1414))
+        (PORT datad (882:882:882) (811:811:811))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1580:1580:1580) (1422:1422:1422))
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (392:392:392))
+        (PORT datac (1570:1570:1570) (1411:1411:1411))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1239:1239:1239) (1058:1058:1058))
+        (PORT datab (1269:1269:1269) (1089:1089:1089))
+        (PORT datac (1578:1578:1578) (1420:1420:1420))
+        (PORT datad (286:286:286) (345:345:345))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1567:1567:1567) (1409:1409:1409))
+        (PORT datad (288:288:288) (347:347:347))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (395:395:395))
+        (PORT datac (1579:1579:1579) (1421:1421:1421))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (397:397:397))
+        (PORT datac (1581:1581:1581) (1423:1423:1423))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1656:1656:1656) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1688:1688:1688) (1639:1639:1639))
+        (PORT ena (1854:1854:1854) (1632:1632:1632))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (908:908:908) (803:803:803))
+        (PORT datac (1302:1302:1302) (1197:1197:1197))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (911:911:911) (806:806:806))
+        (PORT datab (1139:1139:1139) (982:982:982))
+        (PORT datac (1294:1294:1294) (1189:1189:1189))
+        (PORT datad (831:831:831) (730:730:730))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1300:1300:1300) (1195:1195:1195))
+        (PORT datad (286:286:286) (344:344:344))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (398:398:398))
+        (PORT datac (1304:1304:1304) (1199:1199:1199))
+        (IOPATH dataa combout (420:420:420) (400:400:400))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (395:395:395))
+        (PORT datab (1139:1139:1139) (982:982:982))
+        (PORT datac (1295:1295:1295) (1190:1190:1190))
+        (PORT datad (831:831:831) (730:730:730))
+        (IOPATH dataa combout (420:420:420) (371:371:371))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1293:1293:1293) (1187:1187:1187))
+        (PORT datad (278:278:278) (333:333:333))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1655:1655:1655) (1674:1674:1674))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1687:1687:1687) (1639:1639:1639))
+        (PORT ena (1544:1544:1544) (1395:1395:1395))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD ena (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (297:297:297))
+        (PORT datab (336:336:336) (397:397:397))
+        (PORT datac (336:336:336) (422:422:422))
+        (PORT datad (821:821:821) (696:696:696))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|tx\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (283:283:283))
+        (PORT datab (1212:1212:1212) (1049:1049:1049))
+        (PORT datad (228:228:228) (236:236:236))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (437:437:437) (451:451:451))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|tx)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1666:1666:1666) (1684:1684:1684))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT clrn (1698:1698:1698) (1649:1649:1649))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+)
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo
new file mode 100644
index 0000000..74d0a72
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo
@@ -0,0 +1,24509 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "06/02/2023 04:03:14"
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module uart_sd (
+	sys_clk,
+	sys_rst_n,
+	rx,
+	sd_miso,
+	sd_clk,
+	sd_cs_n,
+	sd_mosi,
+	tx);
+input 	sys_clk;
+input 	sys_rst_n;
+input 	rx;
+input 	sd_miso;
+output 	sd_clk;
+output 	sd_cs_n;
+output 	sd_mosi;
+output 	tx;
+
+// Design Ports Information
+// sd_clk	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_cs_n	=>  Location: PIN_E7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_mosi	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// tx	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_rst_n	=>  Location: PIN_U20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_clk	=>  Location: PIN_T22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_miso	=>  Location: PIN_E9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// rx	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("uart_sd_8_1200mv_85c_v_slow.sdo");
+// synopsys translate_on
+
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ;
+wire \uart_tx_inst|baud_cnt[2]~17_combout ;
+wire \uart_tx_inst|baud_cnt[5]~23_combout ;
+wire \uart_tx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ;
+wire \uart_rx_inst|Add1~4_combout ;
+wire \uart_rx_inst|baud_cnt[4]~21_combout ;
+wire \uart_rx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ;
+wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ;
+wire \data_rw_ctrl_inst|send_data_num[7]~27 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~29 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ;
+wire \data_rw_ctrl_inst|send_data_num[9]~31 ;
+wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ;
+wire \data_rw_ctrl_inst|send_data_num[10]~33 ;
+wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ;
+wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ;
+wire \uart_tx_inst|always0~0_combout ;
+wire \uart_tx_inst|Mux0~1_combout ;
+wire \uart_tx_inst|Mux0~2_combout ;
+wire \uart_tx_inst|Mux0~3_combout ;
+wire \uart_tx_inst|Mux0~4_combout ;
+wire \uart_tx_inst|Mux0~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \uart_tx_inst|work_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \uart_tx_inst|Add1~1_combout ;
+wire \uart_tx_inst|bit_cnt[2]~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ;
+wire \data_rw_ctrl_inst|tx_flag~q ;
+wire \uart_tx_inst|work_en~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ;
+wire \uart_rx_inst|always8~0_combout ;
+wire \uart_rx_inst|rx_reg3~q ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ;
+wire \uart_rx_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ;
+wire \uart_rx_inst|rx_reg2~q ;
+wire \data_rw_ctrl_inst|always3~2_combout ;
+wire \uart_rx_inst|Equal1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ;
+wire \uart_rx_inst|rx_reg1~q ;
+wire \uart_rx_inst|start_nedge~q ;
+wire \uart_rx_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \uart_rx_inst|rx_data[7]~0_combout ;
+wire \uart_rx_inst|rx_reg1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ;
+wire \rx~input_o ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|tx_flag~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ;
+wire \uart_rx_inst|po_data[1]~feeder_combout ;
+wire \uart_rx_inst|rx_data[0]~feeder_combout ;
+wire \uart_rx_inst|po_data[5]~feeder_combout ;
+wire \uart_rx_inst|rx_data[4]~feeder_combout ;
+wire \uart_rx_inst|po_data[6]~feeder_combout ;
+wire \uart_rx_inst|rx_data[5]~feeder_combout ;
+wire \uart_rx_inst|po_data[7]~feeder_combout ;
+wire \uart_rx_inst|rx_data[6]~feeder_combout ;
+wire \uart_rx_inst|po_data[3]~feeder_combout ;
+wire \uart_rx_inst|rx_data[2]~feeder_combout ;
+wire \uart_rx_inst|po_data[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ;
+wire \uart_rx_inst|rx_reg2~feeder_combout ;
+wire \sys_clk~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ;
+wire \sys_rst_n~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ;
+wire \rst_n~0_combout ;
+wire \rst_n~0clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_miso~input_o ;
+wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|init_end~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ;
+wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ;
+wire \data_rw_ctrl_inst|wr_busy_dly~q ;
+wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ;
+wire \data_rw_ctrl_inst|rd_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \uart_rx_inst|Add1~1 ;
+wire \uart_rx_inst|Add1~3 ;
+wire \uart_rx_inst|Add1~5 ;
+wire \uart_rx_inst|Add1~6_combout ;
+wire \uart_rx_inst|bit_cnt~0_combout ;
+wire \uart_rx_inst|Add1~0_combout ;
+wire \uart_rx_inst|bit_cnt~1_combout ;
+wire \uart_rx_inst|Add1~2_combout ;
+wire \uart_rx_inst|always4~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~13_combout ;
+wire \uart_rx_inst|Equal1~0_combout ;
+wire \uart_rx_inst|baud_cnt[5]~23_combout ;
+wire \uart_rx_inst|baud_cnt[2]~17_combout ;
+wire \uart_rx_inst|Equal1~1_combout ;
+wire \uart_rx_inst|Equal1~3_combout ;
+wire \uart_rx_inst|work_en~0_combout ;
+wire \uart_rx_inst|work_en~q ;
+wire \uart_rx_inst|always5~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~14 ;
+wire \uart_rx_inst|baud_cnt[1]~15_combout ;
+wire \uart_rx_inst|baud_cnt[1]~16 ;
+wire \uart_rx_inst|baud_cnt[2]~18 ;
+wire \uart_rx_inst|baud_cnt[3]~19_combout ;
+wire \uart_rx_inst|baud_cnt[3]~20 ;
+wire \uart_rx_inst|baud_cnt[4]~22 ;
+wire \uart_rx_inst|baud_cnt[5]~24 ;
+wire \uart_rx_inst|baud_cnt[6]~25_combout ;
+wire \uart_rx_inst|baud_cnt[6]~26 ;
+wire \uart_rx_inst|baud_cnt[7]~27_combout ;
+wire \uart_rx_inst|baud_cnt[7]~28 ;
+wire \uart_rx_inst|baud_cnt[8]~29_combout ;
+wire \uart_rx_inst|baud_cnt[8]~30 ;
+wire \uart_rx_inst|baud_cnt[9]~31_combout ;
+wire \uart_rx_inst|baud_cnt[9]~32 ;
+wire \uart_rx_inst|baud_cnt[10]~34 ;
+wire \uart_rx_inst|baud_cnt[11]~35_combout ;
+wire \uart_rx_inst|baud_cnt[11]~36 ;
+wire \uart_rx_inst|baud_cnt[12]~37_combout ;
+wire \uart_rx_inst|Equal2~1_combout ;
+wire \uart_rx_inst|Equal2~2_combout ;
+wire \uart_rx_inst|bit_flag~q ;
+wire \uart_rx_inst|always4~1_combout ;
+wire \uart_rx_inst|rx_flag~q ;
+wire \uart_rx_inst|po_flag~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ;
+wire \sd_ctrl_inst|comb~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ;
+wire \sd_ctrl_inst|comb~0_combout ;
+wire \sd_ctrl_inst|comb~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_mosi~0_combout ;
+wire \sd_ctrl_inst|sd_mosi~1_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
+wire \uart_tx_inst|baud_cnt[0]~13_combout ;
+wire \uart_tx_inst|Equal1~0_combout ;
+wire \uart_tx_inst|Equal1~1_combout ;
+wire \uart_tx_inst|baud_cnt[4]~21_combout ;
+wire \uart_tx_inst|Equal1~2_combout ;
+wire \uart_tx_inst|Equal1~3_combout ;
+wire \uart_tx_inst|always1~0_combout ;
+wire \uart_tx_inst|baud_cnt[0]~14 ;
+wire \uart_tx_inst|baud_cnt[1]~15_combout ;
+wire \uart_tx_inst|baud_cnt[1]~16 ;
+wire \uart_tx_inst|baud_cnt[2]~18 ;
+wire \uart_tx_inst|baud_cnt[3]~19_combout ;
+wire \uart_tx_inst|baud_cnt[3]~20 ;
+wire \uart_tx_inst|baud_cnt[4]~22 ;
+wire \uart_tx_inst|baud_cnt[5]~24 ;
+wire \uart_tx_inst|baud_cnt[6]~25_combout ;
+wire \uart_tx_inst|baud_cnt[6]~26 ;
+wire \uart_tx_inst|baud_cnt[7]~27_combout ;
+wire \uart_tx_inst|baud_cnt[7]~28 ;
+wire \uart_tx_inst|baud_cnt[8]~29_combout ;
+wire \uart_tx_inst|baud_cnt[8]~30 ;
+wire \uart_tx_inst|baud_cnt[9]~31_combout ;
+wire \uart_tx_inst|baud_cnt[9]~32 ;
+wire \uart_tx_inst|baud_cnt[10]~34 ;
+wire \uart_tx_inst|baud_cnt[11]~35_combout ;
+wire \uart_tx_inst|baud_cnt[11]~36 ;
+wire \uart_tx_inst|baud_cnt[12]~37_combout ;
+wire \uart_tx_inst|Equal2~0_combout ;
+wire \uart_tx_inst|Equal2~1_combout ;
+wire \uart_tx_inst|bit_flag~q ;
+wire \uart_tx_inst|always3~0_combout ;
+wire \uart_tx_inst|always0~1_combout ;
+wire \uart_tx_inst|bit_cnt[0]~5_combout ;
+wire \uart_tx_inst|bit_cnt[1]~4_combout ;
+wire \uart_tx_inst|Add1~0_combout ;
+wire \uart_tx_inst|bit_cnt[3]~2_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~23 ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ;
+wire \data_rw_ctrl_inst|Equal3~0_combout ;
+wire \data_rw_ctrl_inst|rd_busy_dly~q ;
+wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ;
+wire \data_rw_ctrl_inst|send_data_num[0]~13 ;
+wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ;
+wire \data_rw_ctrl_inst|send_data_num[1]~15 ;
+wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ;
+wire \data_rw_ctrl_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|send_data_num[2]~17 ;
+wire \data_rw_ctrl_inst|send_data_num[3]~19 ;
+wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ;
+wire \data_rw_ctrl_inst|send_data_num[4]~21 ;
+wire \data_rw_ctrl_inst|send_data_num[5]~23 ;
+wire \data_rw_ctrl_inst|send_data_num[6]~25 ;
+wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ;
+wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ;
+wire \data_rw_ctrl_inst|always3~1_combout ;
+wire \data_rw_ctrl_inst|always3~3_combout ;
+wire \data_rw_ctrl_inst|send_data_en~0_combout ;
+wire \data_rw_ctrl_inst|send_data_en~q ;
+wire \data_rw_ctrl_inst|Equal3~1_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~17 ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~19 ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~21 ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ;
+wire \data_rw_ctrl_inst|Equal2~3_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~25 ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~28 ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~30 ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~32 ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~34 ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~36 ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~38 ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~40 ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~42 ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~44 ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~46 ;
+wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ;
+wire \data_rw_ctrl_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ;
+wire \data_rw_ctrl_inst|Equal2~1_combout ;
+wire \data_rw_ctrl_inst|Equal2~2_combout ;
+wire \data_rw_ctrl_inst|Equal2~4_combout ;
+wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ;
+wire \uart_tx_inst|Mux0~0_combout ;
+wire \uart_tx_inst|tx~0_combout ;
+wire \uart_tx_inst|tx~q ;
+wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ;
+wire [12:0] \uart_tx_inst|baud_cnt ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ;
+wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ;
+wire [3:0] \uart_tx_inst|bit_cnt ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ;
+wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ;
+wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ;
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ;
+wire [7:0] \uart_rx_inst|rx_data ;
+wire [7:0] \uart_rx_inst|po_data ;
+wire [3:0] \uart_rx_inst|bit_cnt ;
+wire [12:0] \uart_rx_inst|baud_cnt ;
+wire [11:0] \data_rw_ctrl_inst|send_data_num ;
+wire [15:0] \data_rw_ctrl_inst|cnt_wait ;
+wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ;
+wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ;
+wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ;
+wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ;
+wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ;
+wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ;
+wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ;
+wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ;
+
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ;
+wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4];
+
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16];
+
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+
+// Location: PLL_2
+cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 (
+	.areset(!\sys_rst_n~input_o ),
+	.pfdena(vcc),
+	.fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.phaseupdown(gnd),
+	.phasestep(gnd),
+	.scandata(gnd),
+	.scanclk(gnd),
+	.scanclkena(vcc),
+	.configupdate(gnd),
+	.clkswitch(gnd),
+	.inclk({gnd,\sys_clk~input_o }),
+	.phasecounterselect(3'b000),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.activeclock(),
+	.locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.vcooverrange(),
+	.vcounderrange(),
+	.fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ),
+	.clkbad());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND)))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: M9K_X13_Y13_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(18'b000000000000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y27_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9],
+\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2],
+\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(9'b000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0])
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N13
+dffeas \uart_tx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N7
+dffeas \uart_tx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N23
+dffeas \uart_tx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[2]~17_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16  & VCC))
+// \uart_tx_inst|baud_cnt[2]~18  = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_tx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[5]~23_combout  = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_tx_inst|baud_cnt[5]~24  = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5]))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_tx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[10]~33_combout  = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32  & VCC))
+// \uart_tx_inst|baud_cnt[10]~34  = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_tx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N11
+dffeas \data_rw_ctrl_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[5]~27_combout  = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[5]~28  = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[5]~28 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|Add1~4 (
+// Equation(s):
+// \uart_rx_inst|Add1~4_combout  = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3  $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3  & VCC))
+// \uart_rx_inst|Add1~5  = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 ))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~3 ),
+	.combout(\uart_rx_inst|Add1~4_combout ),
+	.cout(\uart_rx_inst|Add1~5 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N11
+dffeas \uart_rx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N23
+dffeas \uart_rx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N7
+dffeas \data_rw_ctrl_inst|send_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N13
+dffeas \data_rw_ctrl_inst|send_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N17
+dffeas \data_rw_ctrl_inst|send_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N19
+dffeas \data_rw_ctrl_inst|send_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N21
+dffeas \data_rw_ctrl_inst|send_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N23
+dffeas \data_rw_ctrl_inst|send_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[4]~21_combout  = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20  & VCC))
+// \uart_rx_inst|baud_cnt[4]~22  = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_rx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[10]~33_combout  = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32  & VCC))
+// \uart_rx_inst|baud_cnt[10]~34  = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_rx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[3]~18_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[3]~19  = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[2]~17 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[3]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[6]~24_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23  & VCC))
+// \data_rw_ctrl_inst|send_data_num[6]~25  = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 ))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[5]~23 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[6]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[7]~26_combout  = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[7]~27  = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[6]~25 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[7]~27 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[8]~28_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27  & VCC))
+// \data_rw_ctrl_inst|send_data_num[8]~29  = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[7]~27 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[8]~29 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[9]~30_combout  = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[9]~31  = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[8]~29 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[9]~31 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[10]~32_combout  = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31  & VCC))
+// \data_rw_ctrl_inst|send_data_num[10]~33  = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[9]~31 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[10]~33 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[11]~34_combout  = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 )
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|send_data_num[10]~33 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~1_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [14])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [15]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & 
+// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~6_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # 
+// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & 
+// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & 
+// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout  = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout  & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout  = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout  & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N15
+dffeas \uart_tx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneive_lcell_comb \uart_tx_inst|always0~0 (
+// Equation(s):
+// \uart_tx_inst|always0~0_combout  = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F;
+defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N30
+cycloneive_lcell_comb \uart_tx_inst|Mux0~1 (
+// Equation(s):
+// \uart_tx_inst|Mux0~1_combout  = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2;
+defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Mux0~2 (
+// Equation(s):
+// \uart_tx_inst|Mux0~2_combout  = (\uart_tx_inst|Mux0~1_combout  & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout  & 
+// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))
+
+	.dataa(\uart_tx_inst|Mux0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62;
+defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|Mux0~3 (
+// Equation(s):
+// \uart_tx_inst|Mux0~3_combout  = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0;
+defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneive_lcell_comb \uart_tx_inst|Mux0~4 (
+// Equation(s):
+// \uart_tx_inst|Mux0~4_combout  = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000;
+defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneive_lcell_comb \uart_tx_inst|Mux0~5 (
+// Equation(s):
+// \uart_tx_inst|Mux0~5_combout  = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout ))))
+
+	.dataa(\uart_tx_inst|Mux0~3_combout ),
+	.datab(\uart_tx_inst|Mux0~4_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|Mux0~2_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E;
+defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003;
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout  = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout  = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~0_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N17
+dffeas \uart_rx_inst|po_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N19
+dffeas \uart_rx_inst|po_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N21
+dffeas \uart_rx_inst|po_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N15
+dffeas \uart_rx_inst|po_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N9
+dffeas \uart_rx_inst|po_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N27
+dffeas \uart_rx_inst|po_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N13
+dffeas \uart_rx_inst|po_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N31
+dffeas \uart_rx_inst|po_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N21
+dffeas \uart_tx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_tx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneive_lcell_comb \uart_tx_inst|Add1~1 (
+// Equation(s):
+// \uart_tx_inst|Add1~1_combout  = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0;
+defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N14
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[2]~3_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|Add1~1_combout ))))
+
+	.dataa(\uart_tx_inst|Add1~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2;
+defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N1
+dffeas \uart_rx_inst|rx_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N11
+dffeas \uart_rx_inst|rx_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N29
+dffeas \uart_rx_inst|rx_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N23
+dffeas \uart_rx_inst|rx_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N27
+dffeas \uart_rx_inst|rx_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[7]~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N25
+dffeas \uart_rx_inst|rx_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N3
+dffeas \uart_rx_inst|rx_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N5
+dffeas \uart_rx_inst|rx_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N13
+dffeas \data_rw_ctrl_inst|tx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|tx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|tx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|work_en~0 (
+// Equation(s):
+// \uart_tx_inst|work_en~0_combout  = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q  & !\uart_tx_inst|always0~1_combout ))
+
+	.dataa(\data_rw_ctrl_inst|tx_flag~q ),
+	.datab(gnd),
+	.datac(\uart_tx_inst|work_en~q ),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N27
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [2])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & \sd_ctrl_inst|sd_init_inst|miso_dly~q )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N13
+dffeas \uart_rx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|always8~0 (
+// Equation(s):
+// \uart_rx_inst|always8~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|always4~0_combout  $ (!\uart_rx_inst|bit_cnt [3])))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282;
+defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N31
+dffeas \uart_rx_inst|rx_reg3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_reg2~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg3 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Equal2~0 (
+// Equation(s):
+// \uart_rx_inst|Equal2~0_combout  = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N1
+dffeas \uart_rx_inst|rx_reg2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~2_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [8]),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(\data_rw_ctrl_inst|send_data_num [11]),
+	.datad(\data_rw_ctrl_inst|send_data_num [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002;
+defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N30
+cycloneive_lcell_comb \uart_rx_inst|Equal1~2 (
+// Equation(s):
+// \uart_rx_inst|Equal1~2_combout  = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N3
+dffeas \uart_rx_inst|rx_reg1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg1~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg1 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N7
+dffeas \uart_rx_inst|start_nedge (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|start_nedge~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true";
+defparam \uart_rx_inst|start_nedge .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|always3~0 (
+// Equation(s):
+// \uart_rx_inst|always3~0_combout  = (!\uart_rx_inst|rx_reg3~q  & \uart_rx_inst|rx_reg2~q )
+
+	.dataa(\uart_rx_inst|rx_reg3~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg2~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050;
+defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 (
+// Equation(s):
+// \uart_rx_inst|rx_data[7]~0_combout  = !\uart_rx_inst|rx_reg3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg3~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F;
+defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 (
+// Equation(s):
+// \uart_rx_inst|rx_reg1~0_combout  = !\rx~input_o 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\rx~input_o ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF;
+defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneive_io_ibuf \rx~input (
+	.i(rx),
+	.ibar(gnd),
+	.o(\rx~input_o ));
+// synopsys translate_off
+defparam \rx~input .bus_hold = "false";
+defparam \rx~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|tx_flag~feeder_combout  = \data_rw_ctrl_inst|rd_fifo_rd_en~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N16
+cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[1]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[0]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N18
+cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[5]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N4
+cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[4]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N20
+cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[6]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N10
+cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[5]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N8
+cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[7]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N28
+cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[6]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N26
+cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[3]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N22
+cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[2]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N12
+cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[0]~feeder_combout  = \uart_rx_inst|rx_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N0
+cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_reg2~feeder_combout  = \uart_rx_inst|rx_reg1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_reg1~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOOBUF_X5_Y29_N23
+cycloneive_io_obuf \sd_clk~output (
+	.i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_clk),
+	.obar());
+// synopsys translate_off
+defparam \sd_clk~output .bus_hold = "false";
+defparam \sd_clk~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y29_N23
+cycloneive_io_obuf \sd_cs_n~output (
+	.i(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_cs_n),
+	.obar());
+// synopsys translate_off
+defparam \sd_cs_n~output .bus_hold = "false";
+defparam \sd_cs_n~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X1_Y29_N9
+cycloneive_io_obuf \sd_mosi~output (
+	.i(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_mosi),
+	.obar());
+// synopsys translate_off
+defparam \sd_mosi~output .bus_hold = "false";
+defparam \sd_mosi~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N16
+cycloneive_io_obuf \tx~output (
+	.i(!\uart_tx_inst|tx~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(tx),
+	.obar());
+// synopsys translate_off
+defparam \tx~output .bus_hold = "false";
+defparam \tx~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N22
+cycloneive_io_ibuf \sys_clk~input (
+	.i(sys_clk),
+	.ibar(gnd),
+	.o(\sys_clk~input_o ));
+// synopsys translate_off
+defparam \sys_clk~input .bus_hold = "false";
+defparam \sys_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y4_N1
+cycloneive_io_ibuf \sys_rst_n~input (
+	.i(sys_rst_n),
+	.ibar(gnd),
+	.o(\sys_rst_n~input_o ));
+// synopsys translate_off
+defparam \sys_rst_n~input .bus_hold = "false";
+defparam \sys_rst_n~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N0
+cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder (
+// Equation(s):
+// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout  = VCC
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y1_N1
+dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.asdata(vcc),
+	.clrn(\sys_rst_n~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N26
+cycloneive_lcell_comb \rst_n~0 (
+// Equation(s):
+// \rst_n~0_combout  = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )
+
+	.dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.datab(\sys_rst_n~input_o ),
+	.datac(gnd),
+	.datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.cin(gnd),
+	.combout(\rst_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \rst_n~0 .lut_mask = 16'h77FF;
+defparam \rst_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G16
+cycloneive_clkctrl \rst_n~0clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\rst_n~0_combout }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\rst_n~0clkctrl_outclk ));
+// synopsys translate_off
+defparam \rst_n~0clkctrl .clock_type = "global clock";
+defparam \rst_n~0clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X11_Y29_N29
+cycloneive_io_ibuf \sd_miso~input (
+	.i(sd_miso),
+	.ibar(gnd),
+	.o(\sd_miso~input_o ));
+// synopsys translate_off
+defparam \sd_miso~input .bus_hold = "false";
+defparam \sd_miso~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|miso_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_miso~input_o ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout  & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (((\sd_ctrl_inst|sd_read_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N3
+dffeas \sd_ctrl_inst|sd_read_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & \sd_ctrl_inst|sd_read_inst|ack_en~q ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N19
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout  & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  = (\sd_ctrl_inst|sd_init_inst|ack_en~q  & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout  = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [11]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [12]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [13]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [14]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [15]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [17]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [18]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [19]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [29]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [30]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [32]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [33]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [36]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [37]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N27
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2;
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N9
+dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0;
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr18~combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout  & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout  = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout  & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|init_end (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout  = (\data_rw_ctrl_inst|rd_en~q  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))
+
+	.dataa(\data_rw_ctrl_inst|rd_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout  & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Add3~0_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0;
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [12])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N29
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [13])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [14])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [9])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [10])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [7])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N3
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout  = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout  & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [4])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N1
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~3_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~4_combout  = (\sd_ctrl_inst|sd_read_inst|always3~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~4_combout  & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & 
+// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout  & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout 
+//  & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N3
+dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|miso_dly~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (((\sd_ctrl_inst|sd_write_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q  & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N23
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N19
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N25
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N31
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N21
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N27
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N1
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) 
+// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~2_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~1_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit 
+// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~3_combout  = (\sd_ctrl_inst|sd_write_inst|always4~1_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N17
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N27
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N9
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N31
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N13
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N25
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N15
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N5
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N19
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1])))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout  = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout  & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q )))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA;
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout  = (\sd_ctrl_inst|comb~2_combout  & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout  = \sd_ctrl_inst|sd_write_inst|state.IDLE~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N19
+dffeas \data_rw_ctrl_inst|wr_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_fall~0_combout  = (\data_rw_ctrl_inst|wr_busy_dly~q  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC;
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N11
+dffeas \data_rw_ctrl_inst|rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout  = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230;
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) 
+// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout  = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F;
+defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & (((\sd_ctrl_inst|sd_init_inst|mosi~q  & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~1_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout )))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N1
+dffeas \sd_ctrl_inst|sd_read_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Add1~0 (
+// Equation(s):
+// \uart_rx_inst|Add1~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] & VCC))
+// \uart_rx_inst|Add1~1  = CARRY((\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [0]))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Add1~0_combout ),
+	.cout(\uart_rx_inst|Add1~1 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Add1~2 (
+// Equation(s):
+// \uart_rx_inst|Add1~2_combout  = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND)))
+// \uart_rx_inst|Add1~3  = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~1 ),
+	.combout(\uart_rx_inst|Add1~2_combout ),
+	.cout(\uart_rx_inst|Add1~3 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|Add1~6 (
+// Equation(s):
+// \uart_rx_inst|Add1~6_combout  = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|Add1~5 ),
+	.combout(\uart_rx_inst|Add1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C;
+defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~0_combout  = (\uart_rx_inst|Add1~6_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|Add1~6_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC;
+defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N5
+dffeas \uart_rx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~1_combout  = (\uart_rx_inst|Add1~0_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(\uart_rx_inst|Add1~0_combout ),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0;
+defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N25
+dffeas \uart_rx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N11
+dffeas \uart_rx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|always4~0 (
+// Equation(s):
+// \uart_rx_inst|always4~0_combout  = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(\uart_rx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011;
+defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[0]~13_combout  = (\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] & VCC))
+// \uart_rx_inst|baud_cnt[0]~14  = CARRY((\uart_rx_inst|work_en~q  & \uart_rx_inst|baud_cnt [0]))
+
+	.dataa(\uart_rx_inst|work_en~q ),
+	.datab(\uart_rx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_rx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|Equal1~0 (
+// Equation(s):
+// \uart_rx_inst|Equal1~0_combout  = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0])))
+
+	.dataa(\uart_rx_inst|baud_cnt [8]),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(\uart_rx_inst|baud_cnt [1]),
+	.datad(\uart_rx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000;
+defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[5]~23_combout  = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_rx_inst|baud_cnt[5]~24  = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5]))
+
+	.dataa(\uart_rx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_rx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N13
+dffeas \uart_rx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[2]~17_combout  = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16  & VCC))
+// \uart_rx_inst|baud_cnt[2]~18  = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_rx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N7
+dffeas \uart_rx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Equal1~1 (
+// Equation(s):
+// \uart_rx_inst|Equal1~1_combout  = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|Equal1~3 (
+// Equation(s):
+// \uart_rx_inst|Equal1~3_combout  = (\uart_rx_inst|Equal1~2_combout  & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal1~2_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000;
+defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|work_en~0 (
+// Equation(s):
+// \uart_rx_inst|work_en~0_combout  = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q  & !\uart_rx_inst|always4~1_combout ))
+
+	.dataa(\uart_rx_inst|start_nedge~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|work_en~q ),
+	.datad(\uart_rx_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N17
+dffeas \uart_rx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_rx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|always5~0 (
+// Equation(s):
+// \uart_rx_inst|always5~0_combout  = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|Equal1~3_combout ),
+	.datac(gnd),
+	.datad(\uart_rx_inst|work_en~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF;
+defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N3
+dffeas \uart_rx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[1]~15_combout  = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_rx_inst|baud_cnt[1]~16  = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_rx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N5
+dffeas \uart_rx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[3]~19_combout  = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_rx_inst|baud_cnt[3]~20  = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_rx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N9
+dffeas \uart_rx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[6]~25_combout  = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24  & VCC))
+// \uart_rx_inst|baud_cnt[6]~26  = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_rx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N15
+dffeas \uart_rx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[7]~27_combout  = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_rx_inst|baud_cnt[7]~28  = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_rx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N17
+dffeas \uart_rx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[8]~29_combout  = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28  & VCC))
+// \uart_rx_inst|baud_cnt[8]~30  = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_rx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N19
+dffeas \uart_rx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[9]~31_combout  = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_rx_inst|baud_cnt[9]~32  = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_rx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N21
+dffeas \uart_rx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[11]~35_combout  = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_rx_inst|baud_cnt[11]~36  = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_rx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N25
+dffeas \uart_rx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[12]~37_combout  = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_rx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N27
+dffeas \uart_rx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|Equal2~1 (
+// Equation(s):
+// \uart_rx_inst|Equal2~1_combout  = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|Equal2~2 (
+// Equation(s):
+// \uart_rx_inst|Equal2~2_combout  = (\uart_rx_inst|Equal2~0_combout  & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal2~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal2~0_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000;
+defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N23
+dffeas \uart_rx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Equal2~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|always4~1 (
+// Equation(s):
+// \uart_rx_inst|always4~1_combout  = (\uart_rx_inst|always4~0_combout  & (\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_flag~q ),
+	.datad(\uart_rx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000;
+defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N1
+dffeas \uart_rx_inst|rx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always4~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N1
+dffeas \uart_rx_inst|po_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_flag~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\uart_rx_inst|po_flag~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datac(\uart_rx_inst|po_flag~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q  $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & 
+// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N4
+cycloneive_lcell_comb \sd_ctrl_inst|comb~1 (
+// Equation(s):
+// \sd_ctrl_inst|comb~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N0
+cycloneive_lcell_comb \sd_ctrl_inst|comb~0 (
+// Equation(s):
+// \sd_ctrl_inst|comb~0_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N2
+cycloneive_lcell_comb \sd_ctrl_inst|comb~2 (
+// Equation(s):
+// \sd_ctrl_inst|comb~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  & 
+// (\sd_ctrl_inst|comb~1_combout  & \sd_ctrl_inst|comb~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.datac(\sd_ctrl_inst|comb~1_combout ),
+	.datad(\sd_ctrl_inst|comb~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & (((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & 
+// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|comb~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~2_combout  = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~3_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~4_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~5_combout  = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~8_combout  = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout  & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout  & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X11_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|mosi~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & (!\sd_ctrl_inst|sd_init_inst|mosi~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05;
+defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G8
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N2
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[0]~13_combout  = (\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] & VCC))
+// \uart_tx_inst|baud_cnt[0]~14  = CARRY((\uart_tx_inst|work_en~q  & \uart_tx_inst|baud_cnt [0]))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_tx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N0
+cycloneive_lcell_comb \uart_tx_inst|Equal1~0 (
+// Equation(s):
+// \uart_tx_inst|Equal1~0_combout  = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0])))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(\uart_tx_inst|baud_cnt [3]),
+	.datad(\uart_tx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100;
+defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|Equal1~1 (
+// Equation(s):
+// \uart_tx_inst|Equal1~1_combout  = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout  & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9])))
+
+	.dataa(\uart_tx_inst|baud_cnt [8]),
+	.datab(\uart_tx_inst|Equal1~0_combout ),
+	.datac(\uart_tx_inst|baud_cnt [11]),
+	.datad(\uart_tx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004;
+defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[4]~21_combout  = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20  & VCC))
+// \uart_tx_inst|baud_cnt[4]~22  = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_tx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N11
+dffeas \uart_tx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N30
+cycloneive_lcell_comb \uart_tx_inst|Equal1~2 (
+// Equation(s):
+// \uart_tx_inst|Equal1~2_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Equal1~3 (
+// Equation(s):
+// \uart_tx_inst|Equal1~3_combout  = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12])
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(\uart_tx_inst|baud_cnt [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0;
+defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|always1~0 (
+// Equation(s):
+// \uart_tx_inst|always1~0_combout  = ((\uart_tx_inst|Equal1~1_combout  & (\uart_tx_inst|Equal1~2_combout  & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|Equal1~1_combout ),
+	.datac(\uart_tx_inst|Equal1~2_combout ),
+	.datad(\uart_tx_inst|Equal1~3_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555;
+defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N3
+dffeas \uart_tx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[1]~15_combout  = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_tx_inst|baud_cnt[1]~16  = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_tx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N5
+dffeas \uart_tx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[3]~19_combout  = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_tx_inst|baud_cnt[3]~20  = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_tx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N9
+dffeas \uart_tx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[6]~25_combout  = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24  & VCC))
+// \uart_tx_inst|baud_cnt[6]~26  = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_tx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N15
+dffeas \uart_tx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[7]~27_combout  = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_tx_inst|baud_cnt[7]~28  = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_tx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N17
+dffeas \uart_tx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[8]~29_combout  = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28  & VCC))
+// \uart_tx_inst|baud_cnt[8]~30  = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_tx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N19
+dffeas \uart_tx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[9]~31_combout  = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_tx_inst|baud_cnt[9]~32  = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_tx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N21
+dffeas \uart_tx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[11]~35_combout  = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_tx_inst|baud_cnt[11]~36  = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_tx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N25
+dffeas \uart_tx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N26
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[12]~37_combout  = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_tx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_tx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N27
+dffeas \uart_tx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N28
+cycloneive_lcell_comb \uart_tx_inst|Equal2~0 (
+// Equation(s):
+// \uart_tx_inst|Equal2~0_combout  = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Equal2~1 (
+// Equation(s):
+// \uart_tx_inst|Equal2~1_combout  = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout  & \uart_tx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(\uart_tx_inst|baud_cnt [12]),
+	.datac(\uart_tx_inst|Equal2~0_combout ),
+	.datad(\uart_tx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N25
+dffeas \uart_tx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|Equal2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N18
+cycloneive_lcell_comb \uart_tx_inst|always3~0 (
+// Equation(s):
+// \uart_tx_inst|always3~0_combout  = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_tx_inst|bit_flag~q ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF;
+defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneive_lcell_comb \uart_tx_inst|always0~1 (
+// Equation(s):
+// \uart_tx_inst|always0~1_combout  = (\uart_tx_inst|always0~0_combout  & (\uart_tx_inst|bit_flag~q  & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3])))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[0]~5_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q  & \uart_tx_inst|bit_flag~q )))))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078;
+defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N5
+dffeas \uart_tx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[1]~4_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [1]),
+	.datad(\uart_tx_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014;
+defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N1
+dffeas \uart_tx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Add1~0 (
+// Equation(s):
+// \uart_tx_inst|Add1~0_combout  = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))))
+
+	.dataa(\uart_tx_inst|bit_cnt [2]),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC;
+defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[3]~2_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|Add1~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [3]),
+	.datad(\uart_tx_inst|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140;
+defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N3
+dffeas \uart_tx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[0]~16_combout  = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC)
+// \data_rw_ctrl_inst|cnt_wait[0]~17  = CARRY(\data_rw_ctrl_inst|cnt_wait [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[0]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[3]~22_combout  = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[3]~23  = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[3]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[4]~24_combout  = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[4]~25  = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[4]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N9
+dffeas \data_rw_ctrl_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~0_combout  = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5])
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5;
+defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N15
+dffeas \data_rw_ctrl_inst|rd_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[0]~12_combout  = \data_rw_ctrl_inst|send_data_num [0] $ (VCC)
+// \data_rw_ctrl_inst|send_data_num[0]~13  = CARRY(\data_rw_ctrl_inst|send_data_num [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[0]~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N1
+dffeas \data_rw_ctrl_inst|send_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[1]~14_combout  = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[1]~15  = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[0]~13 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[1]~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N3
+dffeas \data_rw_ctrl_inst|send_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[2]~16_combout  = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15  & VCC))
+// \data_rw_ctrl_inst|send_data_num[2]~17  = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[1]~15 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[2]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N5
+dffeas \data_rw_ctrl_inst|send_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~0_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(\data_rw_ctrl_inst|send_data_num [2]),
+	.datad(\data_rw_ctrl_inst|send_data_num [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[4]~20_combout  = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19  & VCC))
+// \data_rw_ctrl_inst|send_data_num[4]~21  = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[3]~19 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[4]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N9
+dffeas \data_rw_ctrl_inst|send_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[5]~22_combout  = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[5]~23  = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[4]~21 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[5]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N15
+dffeas \data_rw_ctrl_inst|send_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N11
+dffeas \data_rw_ctrl_inst|send_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~1_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(\data_rw_ctrl_inst|send_data_num [4]),
+	.datad(\data_rw_ctrl_inst|send_data_num [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~3_combout  = (\data_rw_ctrl_inst|always3~2_combout  & (\data_rw_ctrl_inst|always3~0_combout  & (\data_rw_ctrl_inst|always3~1_combout  & \data_rw_ctrl_inst|Equal2~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|always3~2_combout ),
+	.datab(\data_rw_ctrl_inst|always3~0_combout ),
+	.datac(\data_rw_ctrl_inst|always3~1_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_en~0_combout  = (!\data_rw_ctrl_inst|always3~3_combout  & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & \data_rw_ctrl_inst|rd_busy_dly~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datab(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4;
+defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N23
+dffeas \data_rw_ctrl_inst|send_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~1_combout  = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~26_combout  = ((\data_rw_ctrl_inst|Equal2~2_combout  & (!\data_rw_ctrl_inst|Equal3~0_combout  & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q )
+
+	.dataa(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.datab(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N1
+dffeas \data_rw_ctrl_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[1]~18_combout  = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[1]~19  = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[1]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N3
+dffeas \data_rw_ctrl_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[2]~20_combout  = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[2]~21  = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[2]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N5
+dffeas \data_rw_ctrl_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N7
+dffeas \data_rw_ctrl_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~3_combout  = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[6]~29_combout  = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[6]~30  = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 ))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[6]~30 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[7]~31_combout  = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[7]~32  = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[7]~32 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N15
+dffeas \data_rw_ctrl_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[8]~33_combout  = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[8]~34  = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[8]~34 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N17
+dffeas \data_rw_ctrl_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[9]~35_combout  = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[9]~36  = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[9]~36 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N19
+dffeas \data_rw_ctrl_inst|cnt_wait[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[10]~37_combout  = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[10]~38  = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[10]~38 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N21
+dffeas \data_rw_ctrl_inst|cnt_wait[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[11]~39_combout  = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[11]~40  = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[11]~40 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[12]~41_combout  = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[12]~42  = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[12]~42 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N25
+dffeas \data_rw_ctrl_inst|cnt_wait[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~43_combout  = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[13]~44  = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[13]~44 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[14]~45_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[14]~46  = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[14]~46 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N29
+dffeas \data_rw_ctrl_inst|cnt_wait[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[15]~47_combout  = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 )
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N31
+dffeas \data_rw_ctrl_inst|cnt_wait[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N13
+dffeas \data_rw_ctrl_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~0_combout  = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N27
+dffeas \data_rw_ctrl_inst|cnt_wait[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N23
+dffeas \data_rw_ctrl_inst|cnt_wait[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~1_combout  = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [11]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~2_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout  & \data_rw_ctrl_inst|Equal2~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datac(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~4_combout  = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout  & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000;
+defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N7
+dffeas \data_rw_ctrl_inst|rd_fifo_rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\data_rw_ctrl_inst|rd_fifo_rd_en~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q  $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (\data_rw_ctrl_inst|rd_fifo_rd_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout  = (\sd_miso~input_o  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|Mux0~0 (
+// Equation(s):
+// \uart_tx_inst|Mux0~0_combout  = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout )))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4;
+defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N8
+cycloneive_lcell_comb \uart_tx_inst|tx~0 (
+// Equation(s):
+// \uart_tx_inst|tx~0_combout  = (\uart_tx_inst|bit_flag~q  & (!\uart_tx_inst|Mux0~5_combout  & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q  & (((\uart_tx_inst|tx~q ))))
+
+	.dataa(\uart_tx_inst|Mux0~5_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|tx~q ),
+	.datad(\uart_tx_inst|Mux0~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|tx~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074;
+defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N9
+dffeas \uart_tx_inst|tx (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|tx~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|tx~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|tx .is_wysiwyg = "true";
+defparam \uart_tx_inst|tx .power_up = "low";
+// synopsys translate_on
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo
new file mode 100644
index 0000000..079b0bf
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo
@@ -0,0 +1,19061 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE15F23C8,
+// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "uart_sd")
+  (DATE "06/02/2023 04:03:14")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_pll")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1)
+    (DELAY
+      (ABSOLUTE
+        (PORT areset (4506:4506:4506) (4506:4506:4506))
+        (PORT inclk[0] (2340:2340:2340) (2340:2340:2340))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (931:931:931) (923:923:923))
+        (PORT datab (808:808:808) (785:785:785))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (804:804:804) (804:804:804))
+        (PORT datab (1238:1238:1238) (1164:1164:1164))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (544:544:544) (574:574:574))
+        (PORT datab (334:334:334) (410:410:410))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1396:1396:1396) (1367:1367:1367))
+        (PORT d[1] (1359:1359:1359) (1335:1335:1335))
+        (PORT d[2] (1452:1452:1452) (1414:1414:1414))
+        (PORT d[3] (1585:1585:1585) (1553:1553:1553))
+        (PORT d[4] (1387:1387:1387) (1364:1364:1364))
+        (PORT d[5] (1594:1594:1594) (1561:1561:1561))
+        (PORT d[6] (1414:1414:1414) (1386:1386:1386))
+        (PORT d[7] (1413:1413:1413) (1374:1374:1374))
+        (PORT clk (2265:2265:2265) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1000:1000:1000) (1004:1004:1004))
+        (PORT d[1] (1057:1057:1057) (1051:1051:1051))
+        (PORT d[2] (1285:1285:1285) (1234:1234:1234))
+        (PORT d[3] (1146:1146:1146) (1091:1091:1091))
+        (PORT d[4] (998:998:998) (1003:1003:1003))
+        (PORT d[5] (1764:1764:1764) (1697:1697:1697))
+        (PORT d[6] (1395:1395:1395) (1356:1356:1356))
+        (PORT d[7] (1735:1735:1735) (1651:1651:1651))
+        (PORT d[8] (1021:1021:1021) (1025:1025:1025))
+        (PORT d[9] (923:923:923) (875:875:875))
+        (PORT clk (2261:2261:2261) (2297:2297:2297))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1263:1263:1263) (1151:1151:1151))
+        (PORT clk (2261:2261:2261) (2297:2297:2297))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2265:2265:2265) (2302:2302:2302))
+        (PORT d[0] (1970:1970:1970) (1865:1865:1865))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1346:1346:1346) (1254:1254:1254))
+        (PORT d[1] (1033:1033:1033) (1026:1026:1026))
+        (PORT d[2] (1785:1785:1785) (1710:1710:1710))
+        (PORT d[3] (1782:1782:1782) (1727:1727:1727))
+        (PORT d[4] (1630:1630:1630) (1616:1616:1616))
+        (PORT d[5] (1873:1873:1873) (1814:1814:1814))
+        (PORT d[6] (1365:1365:1365) (1328:1328:1328))
+        (PORT d[7] (1459:1459:1459) (1427:1427:1427))
+        (PORT d[8] (974:974:974) (920:920:920))
+        (PORT clk (2215:2215:2215) (2211:2211:2211))
+        (PORT stall (1591:1591:1591) (1712:1712:1712))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+      (HOLD stall (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2215:2215:2215) (2211:2211:2211))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2207:2207:2207) (2207:2207:2207))
+        (PORT ena (2140:2140:2140) (2024:2024:2024))
+        (IOPATH (posedge clk) q (392:392:392) (392:392:392))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (64:64:64))
+      (SETUP ena (posedge clk) (64:64:64))
+      (HOLD d (posedge clk) (211:211:211))
+      (HOLD ena (posedge clk) (211:211:211))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1219:1219:1219) (1143:1143:1143))
+        (PORT d[1] (1184:1184:1184) (1118:1118:1118))
+        (PORT d[2] (1203:1203:1203) (1138:1138:1138))
+        (PORT d[3] (1598:1598:1598) (1487:1487:1487))
+        (PORT d[4] (1213:1213:1213) (1146:1146:1146))
+        (PORT d[5] (1177:1177:1177) (1117:1117:1117))
+        (PORT d[6] (1221:1221:1221) (1147:1147:1147))
+        (PORT d[7] (1211:1211:1211) (1142:1142:1142))
+        (PORT d[9] (1185:1185:1185) (1123:1123:1123))
+        (PORT d[10] (1282:1282:1282) (1216:1216:1216))
+        (PORT d[11] (1267:1267:1267) (1194:1194:1194))
+        (PORT d[12] (1220:1220:1220) (1147:1147:1147))
+        (PORT d[13] (1532:1532:1532) (1431:1431:1431))
+        (PORT d[14] (1183:1183:1183) (1121:1121:1121))
+        (PORT d[15] (1589:1589:1589) (1459:1459:1459))
+        (PORT d[16] (1587:1587:1587) (1473:1473:1473))
+        (PORT clk (2277:2277:2277) (2307:2307:2307))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1343:1343:1343) (1305:1305:1305))
+        (PORT d[1] (1319:1319:1319) (1250:1250:1250))
+        (PORT d[2] (1673:1673:1673) (1575:1575:1575))
+        (PORT d[3] (1201:1201:1201) (1154:1154:1154))
+        (PORT d[4] (1004:1004:1004) (992:992:992))
+        (PORT d[5] (1807:1807:1807) (1681:1681:1681))
+        (PORT d[6] (1680:1680:1680) (1599:1599:1599))
+        (PORT d[7] (949:949:949) (949:949:949))
+        (PORT d[8] (1566:1566:1566) (1421:1421:1421))
+        (PORT clk (2273:2273:2273) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1282:1282:1282) (1174:1174:1174))
+        (PORT clk (2273:2273:2273) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2277:2277:2277) (2307:2307:2307))
+        (PORT d[0] (1989:1989:1989) (1888:1888:1888))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1309:1309:1309) (1203:1203:1203))
+        (PORT d[1] (1804:1804:1804) (1740:1740:1740))
+        (PORT d[2] (1461:1461:1461) (1445:1445:1445))
+        (PORT d[3] (1021:1021:1021) (1013:1013:1013))
+        (PORT d[4] (1060:1060:1060) (1047:1047:1047))
+        (PORT d[5] (1578:1578:1578) (1553:1553:1553))
+        (PORT d[6] (1006:1006:1006) (992:992:992))
+        (PORT d[7] (1333:1333:1333) (1307:1307:1307))
+        (PORT d[8] (1312:1312:1312) (1273:1273:1273))
+        (PORT d[9] (1627:1627:1627) (1511:1511:1511))
+        (PORT clk (2227:2227:2227) (2216:2216:2216))
+        (PORT stall (1248:1248:1248) (1359:1359:1359))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+      (HOLD stall (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2227:2227:2227) (2216:2216:2216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2219:2219:2219) (2212:2212:2212))
+        (PORT ena (1788:1788:1788) (1681:1681:1681))
+        (IOPATH (posedge clk) q (392:392:392) (392:392:392))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (64:64:64))
+      (SETUP ena (posedge clk) (64:64:64))
+      (HOLD d (posedge clk) (211:211:211))
+      (HOLD ena (posedge clk) (211:211:211))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (567:567:567) (610:610:610))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (481:481:481))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (449:449:449))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (462:462:462))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (430:430:430))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (450:450:450))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (432:432:432))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (435:435:435))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (438:438:438))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (805:805:805) (798:798:798))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (628:628:628) (632:632:632))
+        (PORT datac (580:580:580) (595:595:595))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (432:432:432))
+        (PORT datab (565:565:565) (593:593:593))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (605:605:605))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (524:524:524) (558:558:558))
+        (PORT datad (474:474:474) (446:446:446))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (326:326:326))
+        (PORT datab (642:642:642) (657:657:657))
+        (PORT datac (1966:1966:1966) (1886:1886:1886))
+        (PORT datad (1111:1111:1111) (1012:1012:1012))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (463:463:463))
+        (PORT datab (359:359:359) (454:454:454))
+        (PORT datac (317:317:317) (411:411:411))
+        (PORT datad (321:321:321) (404:404:404))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (627:627:627))
+        (PORT datab (394:394:394) (508:508:508))
+        (PORT datac (924:924:924) (871:871:871))
+        (PORT datad (508:508:508) (485:485:485))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (953:953:953) (919:919:919))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (508:508:508) (494:494:494))
+        (PORT datad (355:355:355) (466:466:466))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (619:619:619) (585:585:585))
+        (PORT datab (383:383:383) (479:479:479))
+        (PORT datac (566:566:566) (543:543:543))
+        (PORT datad (356:356:356) (467:467:467))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (283:283:283) (315:315:315))
+        (PORT datab (385:385:385) (481:481:481))
+        (PORT datac (1679:1679:1679) (1549:1549:1549))
+        (PORT datad (928:928:928) (884:884:884))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (628:628:628))
+        (PORT datab (389:389:389) (503:503:503))
+        (PORT datac (906:906:906) (851:851:851))
+        (PORT datad (513:513:513) (492:492:492))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (925:925:925))
+        (PORT datab (384:384:384) (480:480:480))
+        (PORT datac (449:449:449) (425:425:425))
+        (PORT datad (943:943:943) (885:885:885))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (366:366:366) (458:458:458))
+        (PORT datac (343:343:343) (439:439:439))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (960:960:960) (926:926:926))
+        (PORT datab (384:384:384) (480:480:480))
+        (PORT datac (559:559:559) (534:534:534))
+        (PORT datad (354:354:354) (464:464:464))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (946:946:946) (905:905:905))
+        (PORT datab (398:398:398) (513:513:513))
+        (PORT datac (558:558:558) (533:533:533))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (370:370:370) (462:462:462))
+        (PORT datac (238:238:238) (265:265:265))
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (641:641:641) (656:656:656))
+        (PORT datac (573:573:573) (592:592:592))
+        (PORT datad (868:868:868) (822:822:822))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1097:1097:1097) (1105:1105:1105))
+        (PORT datac (975:975:975) (1007:1007:1007))
+        (PORT datad (1014:1014:1014) (1020:1020:1020))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (996:996:996) (1013:1013:1013))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (974:974:974) (1005:1005:1005))
+        (PORT datad (978:978:978) (973:973:973))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1026:1026:1026))
+        (PORT datab (1018:1018:1018) (1046:1046:1046))
+        (PORT datac (1038:1038:1038) (1061:1061:1061))
+        (PORT datad (1012:1012:1012) (1018:1018:1018))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (954:954:954) (967:967:967))
+        (PORT datad (898:898:898) (902:902:902))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1093:1093:1093) (1100:1100:1100))
+        (PORT datac (958:958:958) (977:977:977))
+        (PORT datad (1013:1013:1013) (1018:1018:1018))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1027:1027:1027))
+        (PORT datab (1017:1017:1017) (1045:1045:1045))
+        (PORT datac (953:953:953) (966:966:966))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1019:1019:1019) (1048:1048:1048))
+        (PORT datac (956:956:956) (975:975:975))
+        (PORT datad (1014:1014:1014) (1019:1019:1019))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1012:1012:1012))
+        (PORT datab (1097:1097:1097) (1104:1104:1104))
+        (PORT datac (974:974:974) (1006:1006:1006))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1026:1026:1026))
+        (PORT datab (1099:1099:1099) (1107:1107:1107))
+        (PORT datac (975:975:975) (1008:1008:1008))
+        (PORT datad (1015:1015:1015) (1021:1021:1021))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1011:1011:1011))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (955:955:955) (974:974:974))
+        (PORT datad (900:900:900) (898:898:898))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (906:906:906) (904:904:904))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1056:1056:1056) (1042:1042:1042))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (335:335:335) (423:423:423))
+        (PORT datad (341:341:341) (440:440:440))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (951:951:951) (877:877:877))
+        (PORT datab (392:392:392) (494:494:494))
+        (PORT datac (353:353:353) (473:473:473))
+        (PORT datad (867:867:867) (797:797:797))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (310:310:310))
+        (PORT datab (390:390:390) (492:492:492))
+        (PORT datac (851:851:851) (786:786:786))
+        (PORT datad (878:878:878) (811:811:811))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (862:862:862) (811:811:811))
+        (PORT datab (397:397:397) (515:515:515))
+        (PORT datac (809:809:809) (750:750:750))
+        (PORT datad (348:348:348) (449:449:449))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (398:398:398) (515:515:515))
+        (PORT datac (811:811:811) (754:754:754))
+        (PORT datad (349:349:349) (450:450:450))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (337:337:337) (424:424:424))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datad (531:531:531) (559:559:559))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (591:591:591) (628:628:628))
+        (PORT datab (360:360:360) (449:449:449))
+        (PORT datac (316:316:316) (413:413:413))
+        (PORT datad (263:263:263) (280:280:280))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (615:615:615) (619:619:619))
+        (PORT datac (564:564:564) (579:579:579))
+        (PORT datad (521:521:521) (540:540:540))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (1696:1696:1696) (1660:1660:1660))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (912:912:912) (907:907:907))
+        (PORT datab (1228:1228:1228) (1188:1188:1188))
+        (PORT datac (341:341:341) (430:430:430))
+        (PORT datad (254:254:254) (283:283:283))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datac (354:354:354) (438:438:438))
+        (PORT datad (274:274:274) (295:295:295))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (595:595:595) (631:631:631))
+        (PORT datad (254:254:254) (283:283:283))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (883:883:883) (842:842:842))
+        (PORT datac (810:810:810) (790:790:790))
+        (PORT datad (764:764:764) (700:700:700))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (810:810:810) (790:790:790))
+        (PORT datad (764:764:764) (700:700:700))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1269:1269:1269) (1235:1235:1235))
+        (PORT datad (1212:1212:1212) (1150:1150:1150))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (437:437:437))
+        (PORT datac (312:312:312) (400:400:400))
+        (PORT datad (323:323:323) (402:402:402))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (473:473:473))
+        (PORT datab (352:352:352) (442:442:442))
+        (PORT datac (336:336:336) (426:426:426))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (445:445:445))
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datac (845:845:845) (833:833:833))
+        (PORT datad (256:256:256) (282:282:282))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (903:903:903) (919:919:919))
+        (PORT datab (590:590:590) (574:574:574))
+        (PORT datac (1103:1103:1103) (1004:1004:1004))
+        (PORT datad (338:338:338) (419:419:419))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datad (300:300:300) (373:373:373))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (976:976:976) (910:910:910))
+        (PORT datac (788:788:788) (717:717:717))
+        (PORT datad (340:340:340) (424:424:424))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (446:446:446))
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datac (845:845:845) (833:833:833))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1181:1181:1181) (1102:1102:1102))
+        (PORT datab (362:362:362) (452:452:452))
+        (PORT datac (318:318:318) (416:416:416))
+        (PORT datad (482:482:482) (469:469:469))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (279:279:279) (304:304:304))
+        (PORT datac (494:494:494) (468:468:468))
+        (PORT datad (826:826:826) (758:758:758))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (285:285:285) (317:317:317))
+        (PORT datac (495:495:495) (475:475:475))
+        (PORT datad (972:972:972) (966:966:966))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (432:432:432))
+        (PORT datab (340:340:340) (419:419:419))
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (462:462:462))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (320:320:320) (407:407:407))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (276:276:276) (300:300:300))
+        (PORT datad (249:249:249) (271:271:271))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (515:515:515) (501:501:501))
+        (PORT datac (486:486:486) (463:463:463))
+        (PORT datad (330:330:330) (404:404:404))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (581:581:581) (603:603:603))
+        (PORT datab (397:397:397) (512:512:512))
+        (PORT datad (329:329:329) (420:420:420))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1341:1341:1341) (1329:1329:1329))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (933:933:933) (934:934:934))
+        (PORT datab (867:867:867) (869:869:869))
+        (PORT datad (903:903:903) (893:893:893))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (760:760:760) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (941:941:941))
+        (PORT datab (944:944:944) (930:930:930))
+        (PORT datad (293:293:293) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (959:959:959))
+        (PORT datab (888:888:888) (883:883:883))
+        (PORT datad (881:881:881) (876:876:876))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (973:973:973) (988:988:988))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1189:1189:1189) (1105:1105:1105))
+        (PORT datab (905:905:905) (896:896:896))
+        (PORT datad (296:296:296) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (492:492:492) (471:471:471))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (482:482:482) (450:450:450))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (934:934:934) (932:932:932))
+        (PORT datab (1342:1342:1342) (1281:1281:1281))
+        (PORT datad (310:310:310) (394:394:394))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1612:1612:1612) (1516:1516:1516))
+        (PORT datab (921:921:921) (910:910:910))
+        (PORT datad (549:549:549) (573:573:573))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (769:769:769) (844:844:844))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (772:772:772) (848:848:848))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1327:1327:1327) (1294:1294:1294))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (926:926:926) (912:912:912))
+        (PORT datab (617:617:617) (631:631:631))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (617:617:617) (626:626:626))
+        (PORT datab (827:827:827) (817:817:817))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (391:391:391) (507:507:507))
+        (PORT datac (336:336:336) (424:424:424))
+        (PORT datad (340:340:340) (439:439:439))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (295:295:295) (330:330:330))
+        (PORT datad (291:291:291) (325:325:325))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (936:936:936) (946:946:946))
+        (PORT datab (341:341:341) (421:421:421))
+        (PORT datac (305:305:305) (389:389:389))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1366:1366:1366) (1361:1361:1361))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (515:515:515) (501:501:501))
+        (PORT datac (487:487:487) (463:463:463))
+        (PORT datad (330:330:330) (404:404:404))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2013:2013:2013) (1835:1835:1835))
+        (PORT datac (330:330:330) (415:415:415))
+        (PORT datad (238:238:238) (256:256:256))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1740:1740:1740) (1706:1706:1706))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1825:1825:1825) (1791:1791:1791))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (794:794:794) (869:869:869))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (771:771:771) (846:846:846))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT ena (1107:1107:1107) (1090:1090:1090))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (771:771:771) (846:846:846))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datad (1118:1118:1118) (1013:1013:1013))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (768:768:768) (843:843:843))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (762:762:762) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1311:1311:1311) (1233:1233:1233))
+        (PORT datab (980:980:980) (943:943:943))
+        (PORT datac (362:362:362) (451:451:451))
+        (PORT datad (282:282:282) (306:306:306))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (303:303:303) (388:388:388))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (307:307:307) (391:391:391))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (942:942:942) (953:953:953))
+        (PORT datac (377:377:377) (502:502:502))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4197:4197:4197) (4406:4406:4406))
+        (PORT datad (917:917:917) (911:911:911))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (789:789:789) (859:859:859))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3759:3759:3759) (3988:3988:3988))
+        (PORT datab (354:354:354) (440:440:440))
+        (PORT datac (579:579:579) (595:595:595))
+        (PORT datad (922:922:922) (922:922:922))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (468:468:468))
+        (PORT datab (353:353:353) (441:441:441))
+        (PORT datac (531:531:531) (562:562:562))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (478:478:478))
+        (PORT datab (303:303:303) (340:340:340))
+        (PORT datac (337:337:337) (429:429:429))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT asdata (2143:2143:2143) (2068:2068:2068))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT asdata (1042:1042:1042) (1075:1075:1075))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1685:1685:1685) (1653:1653:1653))
+        (PORT datab (1310:1310:1310) (1222:1222:1222))
+        (PORT datac (307:307:307) (394:394:394))
+        (PORT datad (1199:1199:1199) (1130:1130:1130))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1672:1672:1672) (1637:1637:1637))
+        (PORT datab (1306:1306:1306) (1218:1218:1218))
+        (PORT datac (301:301:301) (386:386:386))
+        (PORT datad (1203:1203:1203) (1136:1136:1136))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1389:1389:1389) (1384:1384:1384))
+        (PORT datab (900:900:900) (861:861:861))
+        (PORT datac (1136:1136:1136) (1066:1066:1066))
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1275:1275:1275) (1196:1196:1196))
+        (PORT datab (1307:1307:1307) (1218:1218:1218))
+        (PORT datac (1621:1621:1621) (1577:1577:1577))
+        (PORT datad (307:307:307) (382:382:382))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (466:466:466))
+        (PORT datab (370:370:370) (466:466:466))
+        (PORT datac (311:311:311) (399:399:399))
+        (PORT datad (312:312:312) (388:388:388))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1367:1367:1367) (1362:1362:1362))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (645:645:645))
+        (PORT datab (856:856:856) (845:845:845))
+        (PORT datac (537:537:537) (560:560:560))
+        (PORT datad (527:527:527) (551:551:551))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1854:1854:1854))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1875:1875:1875) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (572:572:572) (599:599:599))
+        (PORT datab (341:341:341) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (449:449:449))
+        (PORT datab (349:349:349) (438:438:438))
+        (PORT datac (311:311:311) (401:401:401))
+        (PORT datad (311:311:311) (391:391:391))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (365:365:365) (442:442:442))
+        (PORT datad (324:324:324) (395:395:395))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1854:1854:1854))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1875:1875:1875) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|start_nedge)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datac (1672:1672:1672) (1604:1604:1604))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (306:306:306) (392:392:392))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (301:301:301) (386:386:386))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3662:3662:3662) (3834:3834:3834))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (346:346:346) (436:436:436))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE rx\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (796:796:796) (842:842:842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (581:581:581))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (971:971:971) (966:966:966))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1242:1242:1242) (1210:1210:1210))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (326:326:326) (397:397:397))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (536:536:536) (568:568:568))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1468:1468:1468) (1342:1342:1342))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (325:325:325) (396:396:396))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (904:904:904) (893:893:893))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (306:306:306) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (376:376:376))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (377:377:377))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (908:908:908) (909:909:909))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (906:906:906) (907:907:907))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (378:378:378))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (884:884:884) (878:878:878))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (809:809:809) (780:780:780))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg2\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_clk\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1609:1609:1609) (1559:1559:1559))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_cs_n\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1891:1891:1891) (1762:1762:1762))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_mosi\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1825:1825:1825) (1696:1696:1696))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE tx\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2904:2904:2904) (3042:3042:3042))
+        (IOPATH i o (3336:3336:3336) (3399:3399:3399))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_clk\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (806:806:806) (852:852:852))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2339:2339:2339) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (374:374:374) (460:460:460))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_rst_n\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (766:766:766) (812:812:812))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (3674:3674:3674) (3934:3934:3934))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (4634:4634:4634) (4434:4434:4434))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE rst_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3009:3009:3009) (3252:3252:3252))
+        (PORT datab (3770:3770:3770) (3925:3925:3925))
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE rst_n\~0clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2603:2603:2603) (2464:2464:2464))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sd_miso\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (734:734:734) (781:781:781))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT asdata (4598:4598:4598) (4812:4812:4812))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4196:4196:4196) (4405:4405:4405))
+        (PORT datab (344:344:344) (427:427:427))
+        (PORT datad (528:528:528) (555:555:555))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (643:643:643))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (846:846:846) (813:813:813))
+        (PORT datad (553:553:553) (574:574:574))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (568:568:568) (605:605:605))
+        (PORT datab (891:891:891) (857:857:857))
+        (PORT datac (844:844:844) (810:810:810))
+        (PORT datad (552:552:552) (573:573:573))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (529:529:529))
+        (PORT datab (491:491:491) (476:476:476))
+        (PORT datad (254:254:254) (282:282:282))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (603:603:603))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (303:303:303) (387:387:387))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (595:595:595) (626:626:626))
+        (PORT datac (499:499:499) (480:480:480))
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (1676:1676:1676) (1638:1638:1638))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (998:998:998) (1014:1014:1014))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (432:432:432))
+        (PORT datab (342:342:342) (421:421:421))
+        (PORT datad (523:523:523) (549:549:549))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (823:823:823) (774:774:774))
+        (PORT datac (446:446:446) (418:418:418))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (433:433:433))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (385:385:385) (476:476:476))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (388:388:388) (482:482:482))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3848:3848:3848) (4133:4133:4133))
+        (PORT datab (949:949:949) (947:947:947))
+        (PORT datac (347:347:347) (443:443:443))
+        (PORT datad (349:349:349) (434:434:434))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (521:521:521))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (246:246:246) (271:271:271))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (430:430:430))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datac (310:310:310) (399:399:399))
+        (PORT datad (320:320:320) (411:411:411))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (286:286:286) (314:314:314))
+        (PORT datac (347:347:347) (443:443:443))
+        (PORT datad (349:349:349) (433:433:433))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (462:462:462))
+        (PORT datab (343:343:343) (422:422:422))
+        (PORT datac (345:345:345) (440:440:440))
+        (PORT datad (347:347:347) (431:431:431))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (474:474:474))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (380:380:380) (466:466:466))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (337:337:337) (427:427:427))
+        (PORT datad (338:338:338) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (1262:1262:1262) (1239:1239:1239))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (762:762:762) (832:832:832))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (370:370:370))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (759:759:759) (828:828:828))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (306:306:306) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (998:998:998) (1021:1021:1021))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (894:894:894) (890:890:890))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (762:762:762) (832:832:832))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (762:762:762) (831:831:831))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (763:763:763) (833:833:833))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (1246:1246:1246) (1218:1218:1218))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (314:314:314) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (508:508:508) (535:535:535))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (982:982:982) (1002:1002:1002))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (556:556:556) (590:590:590))
+        (PORT datad (506:506:506) (534:534:534))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (971:971:971) (986:986:986))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (302:302:302) (375:375:375))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (770:770:770) (846:846:846))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datad (304:304:304) (376:376:376))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datad (256:256:256) (282:282:282))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (883:883:883) (802:802:802))
+        (PORT datac (320:320:320) (416:416:416))
+        (PORT datad (482:482:482) (469:469:469))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (447:447:447))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (600:600:600))
+        (PORT datab (341:341:341) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (284:284:284) (315:315:315))
+        (PORT datac (311:311:311) (402:402:402))
+        (PORT datad (248:248:248) (270:270:270))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (433:433:433))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (357:357:357) (452:452:452))
+        (PORT datab (286:286:286) (317:317:317))
+        (PORT datad (249:249:249) (271:271:271))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (836:836:836) (785:785:785))
+        (PORT datad (788:788:788) (706:706:706))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (531:531:531) (520:520:520))
+        (PORT datac (306:306:306) (392:392:392))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (449:449:449))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (566:566:566) (609:609:609))
+        (PORT datab (342:342:342) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (328:328:328) (405:405:405))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (959:959:959) (947:947:947))
+        (PORT datac (864:864:864) (812:812:812))
+        (PORT datad (285:285:285) (313:313:313))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1099:1099:1099) (1107:1107:1107))
+        (PORT datac (975:975:975) (1007:1007:1007))
+        (PORT datad (1015:1015:1015) (1021:1021:1021))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (858:858:858) (805:805:805))
+        (PORT datad (279:279:279) (306:306:306))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (782:782:782) (733:733:733))
+        (PORT datab (381:381:381) (464:464:464))
+        (PORT datad (530:530:530) (526:526:526))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1182:1182:1182) (1104:1104:1104))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (320:320:320) (416:416:416))
+        (PORT datad (479:479:479) (466:466:466))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (784:784:784) (734:734:734))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (531:531:531) (528:528:528))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (785:785:785) (736:736:736))
+        (PORT datab (371:371:371) (455:455:455))
+        (PORT datad (532:532:532) (529:529:529))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (381:381:381) (475:475:475))
+        (PORT datab (594:594:594) (578:578:578))
+        (PORT datad (826:826:826) (758:758:758))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (462:462:462))
+        (PORT datab (591:591:591) (574:574:574))
+        (PORT datad (820:820:820) (752:752:752))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (462:462:462))
+        (PORT datab (359:359:359) (452:452:452))
+        (PORT datac (316:316:316) (410:410:410))
+        (PORT datad (321:321:321) (392:392:392))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (980:980:980) (914:914:914))
+        (PORT datac (793:793:793) (723:723:723))
+        (PORT datad (329:329:329) (406:406:406))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (522:522:522) (519:519:519))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (319:319:319) (413:413:413))
+        (PORT datad (824:824:824) (756:756:756))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (379:379:379) (472:472:472))
+        (PORT datab (370:370:370) (454:454:454))
+        (PORT datac (538:538:538) (572:572:572))
+        (PORT datad (338:338:338) (419:419:419))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (907:907:907) (857:857:857))
+        (PORT datab (324:324:324) (355:355:355))
+        (PORT datac (522:522:522) (494:494:494))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (441:441:441))
+        (PORT datab (531:531:531) (520:520:520))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (445:445:445))
+        (PORT datac (805:805:805) (798:798:798))
+        (PORT datad (338:338:338) (418:418:418))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (850:850:850) (818:818:818))
+        (PORT datab (830:830:830) (770:770:770))
+        (PORT datac (238:238:238) (264:264:264))
+        (PORT datad (1185:1185:1185) (1096:1096:1096))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (442:442:442))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (450:450:450))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (450:450:450))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (438:438:438))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (571:571:571) (599:599:599))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (318:318:318) (413:413:413))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (444:444:444))
+        (PORT datac (326:326:326) (411:411:411))
+        (PORT datad (309:309:309) (389:389:389))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (285:285:285) (316:316:316))
+        (PORT datac (495:495:495) (475:475:475))
+        (PORT datad (972:972:972) (967:967:967))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (531:531:531))
+        (PORT datab (1201:1201:1201) (1076:1076:1076))
+        (PORT datad (255:255:255) (283:283:283))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (298:298:298) (336:336:336))
+        (PORT datab (345:345:345) (428:428:428))
+        (PORT datac (504:504:504) (486:486:486))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (822:822:822) (784:784:784))
+        (PORT datab (854:854:854) (816:816:816))
+        (PORT datad (1184:1184:1184) (1095:1095:1095))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (627:627:627))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (338:338:338) (428:428:428))
+        (PORT datad (318:318:318) (405:405:405))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (433:433:433))
+        (PORT datab (565:565:565) (594:594:594))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (296:296:296) (341:341:341))
+        (PORT datab (530:530:530) (492:492:492))
+        (PORT datac (509:509:509) (480:480:480))
+        (PORT datad (574:574:574) (595:595:595))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (1663:1663:1663) (1589:1589:1589))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (470:470:470))
+        (PORT datac (314:314:314) (403:403:403))
+        (PORT datad (312:312:312) (389:389:389))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1369:1369:1369) (1364:1364:1364))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (292:292:292) (319:319:319))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (465:465:465))
+        (PORT datac (310:310:310) (398:398:398))
+        (PORT datad (311:311:311) (388:388:388))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (453:453:453))
+        (PORT datad (601:601:601) (651:651:651))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (704:704:704))
+        (PORT datac (301:301:301) (385:385:385))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (704:704:704))
+        (PORT datad (506:506:506) (537:537:537))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (643:643:643) (702:702:702))
+        (PORT datac (303:303:303) (386:386:386))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (437:437:437))
+        (PORT datab (550:550:550) (585:585:585))
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (607:607:607) (622:622:622))
+        (PORT datad (600:600:600) (650:650:650))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (642:642:642) (700:700:700))
+        (PORT datac (304:304:304) (389:389:389))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (642:642:642) (701:701:701))
+        (PORT datac (302:302:302) (386:386:386))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (302:302:302) (387:387:387))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (431:431:431))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datac (535:535:535) (553:553:553))
+        (PORT datad (534:534:534) (560:560:560))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (558:558:558) (531:531:531))
+        (PORT datab (287:287:287) (319:319:319))
+        (PORT datac (506:506:506) (485:485:485))
+        (PORT datad (490:490:490) (461:461:461))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (495:495:495) (475:475:475))
+        (PORT datab (889:889:889) (798:798:798))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (436:436:436))
+        (PORT datab (422:422:422) (545:545:545))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (304:304:304) (388:388:388))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (435:435:435))
+        (PORT datab (422:422:422) (545:545:545))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (545:545:545))
+        (PORT datac (304:304:304) (389:389:389))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datac (300:300:300) (383:383:383))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (557:557:557) (530:530:530))
+        (PORT datab (286:286:286) (318:318:318))
+        (PORT datac (505:505:505) (484:484:484))
+        (PORT datad (490:490:490) (461:461:461))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1366:1366:1366) (1360:1360:1360))
+        (PORT datab (323:323:323) (360:360:360))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1369:1369:1369) (1364:1364:1364))
+        (PORT datab (322:322:322) (359:359:359))
+        (PORT datac (445:445:445) (427:427:427))
+        (PORT datad (333:333:333) (427:427:427))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (453:453:453))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (449:449:449))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (299:299:299) (344:344:344))
+        (PORT datab (321:321:321) (358:358:358))
+        (PORT datac (518:518:518) (550:550:550))
+        (PORT datad (332:332:332) (426:426:426))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (538:538:538) (498:498:498))
+        (PORT datab (634:634:634) (643:643:643))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (514:514:514) (499:499:499))
+        (PORT datab (854:854:854) (816:816:816))
+        (PORT datad (516:516:516) (550:550:550))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (531:531:531) (560:560:560))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datad (531:531:531) (559:559:559))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (339:339:339) (422:422:422))
+        (PORT datac (303:303:303) (388:388:388))
+        (PORT datad (311:311:311) (395:395:395))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (313:313:313) (343:343:343))
+        (PORT datad (533:533:533) (562:562:562))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (575:575:575))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (433:433:433))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (566:566:566) (593:593:593))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (432:432:432))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (428:428:428))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (301:301:301) (386:386:386))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (466:466:466))
+        (PORT datab (570:570:570) (598:598:598))
+        (PORT datac (309:309:309) (401:401:401))
+        (PORT datad (311:311:311) (395:395:395))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (315:315:315) (342:342:342))
+        (PORT datad (266:266:266) (283:283:283))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (467:467:467))
+        (PORT datab (343:343:343) (421:421:421))
+        (PORT datad (274:274:274) (298:298:298))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (994:994:994) (1010:1010:1010))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (432:432:432))
+        (PORT datab (341:341:341) (420:420:420))
+        (PORT datad (320:320:320) (391:391:391))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (772:772:772) (849:849:849))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datab (344:344:344) (424:424:424))
+        (PORT datad (527:527:527) (554:554:554))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (893:893:893) (833:833:833))
+        (PORT datad (833:833:833) (773:773:773))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (326:326:326))
+        (PORT datab (1925:1925:1925) (1777:1777:1777))
+        (PORT datad (240:240:240) (259:259:259))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2353:2353:2353) (2234:2234:2234))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (480:480:480))
+        (PORT datad (332:332:332) (423:423:423))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (628:628:628))
+        (PORT datab (388:388:388) (502:502:502))
+        (PORT datac (342:342:342) (438:438:438))
+        (PORT datad (328:328:328) (418:418:418))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1946:1946:1946) (1865:1865:1865))
+        (PORT datad (1111:1111:1111) (1012:1012:1012))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (449:449:449))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1152:1152:1152) (1063:1063:1063))
+        (PORT datab (622:622:622) (629:629:629))
+        (PORT datac (574:574:574) (593:593:593))
+        (PORT datad (536:536:536) (557:557:557))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (547:547:547) (509:509:509))
+        (PORT datab (641:641:641) (655:655:655))
+        (PORT datac (527:527:527) (561:561:561))
+        (PORT datad (265:265:265) (283:283:283))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1218:1218:1218) (1156:1156:1156))
+        (PORT datab (1653:1653:1653) (1531:1531:1531))
+        (PORT datad (466:466:466) (440:440:440))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4262:4262:4262) (4487:4487:4487))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (306:306:306) (392:392:392))
+        (PORT datad (381:381:381) (478:478:478))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (430:430:430))
+        (PORT datab (345:345:345) (426:426:426))
+        (PORT datac (299:299:299) (380:380:380))
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (437:437:437))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (364:364:364) (441:441:441))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (603:603:603))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datac (300:300:300) (382:382:382))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datad (239:239:239) (257:257:257))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1288:1288:1288) (1231:1231:1231))
+        (PORT datab (1192:1192:1192) (1083:1083:1083))
+        (PORT datad (257:257:257) (287:287:287))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (451:451:451))
+        (PORT datad (535:535:535) (565:565:565))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (536:536:536) (566:566:566))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (450:450:450))
+        (PORT datab (345:345:345) (428:428:428))
+        (PORT datad (537:537:537) (568:568:568))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (310:310:310) (402:402:402))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1680:1680:1680) (1629:1629:1629))
+        (PORT datad (258:258:258) (287:287:287))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1678:1678:1678) (1628:1628:1628))
+        (PORT datab (298:298:298) (330:330:330))
+        (PORT datad (532:532:532) (561:561:561))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (820:820:820) (814:814:814))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datad (819:819:819) (814:814:814))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (848:848:848) (843:843:843))
+        (PORT datab (315:315:315) (345:345:345))
+        (PORT datad (314:314:314) (394:394:394))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (868:868:868))
+        (PORT datab (374:374:374) (456:456:456))
+        (PORT datac (792:792:792) (770:770:770))
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (319:319:319) (413:413:413))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (463:463:463))
+        (PORT datab (353:353:353) (442:442:442))
+        (PORT datac (311:311:311) (400:400:400))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (904:904:904) (878:878:878))
+        (PORT datab (585:585:585) (616:616:616))
+        (PORT datac (588:588:588) (606:606:606))
+        (PORT datad (489:489:489) (460:460:460))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (292:292:292) (332:332:332))
+        (PORT datab (584:584:584) (615:615:615))
+        (PORT datac (586:586:586) (604:604:604))
+        (PORT datad (493:493:493) (465:465:465))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (327:327:327))
+        (PORT datab (534:534:534) (498:498:498))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (266:266:266) (283:283:283))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (522:522:522))
+        (PORT datab (760:760:760) (709:709:709))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1857:1857:1857) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1224:1224:1224) (1093:1093:1093))
+        (PORT datac (293:293:293) (370:370:370))
+        (PORT datad (822:822:822) (800:800:800))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (926:926:926) (876:876:876))
+        (PORT datad (868:868:868) (815:815:815))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1877:1877:1877))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1893:1893:1893) (1868:1868:1868))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (569:569:569) (605:605:605))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (319:319:319) (413:413:413))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (320:320:320) (414:414:414))
+        (PORT datad (312:312:312) (395:395:395))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (482:482:482))
+        (PORT datab (304:304:304) (328:328:328))
+        (PORT datac (239:239:239) (266:266:266))
+        (PORT datad (968:968:968) (962:962:962))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (239:239:239) (266:266:266))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (480:480:480))
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (430:430:430))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (377:377:377) (465:465:465))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (375:375:375) (485:485:485))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (265:265:265) (301:301:301))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (480:480:480))
+        (PORT datab (381:381:381) (470:470:470))
+        (PORT datac (239:239:239) (266:266:266))
+        (PORT datad (263:263:263) (298:298:298))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (435:435:435))
+        (PORT datab (341:341:341) (423:423:423))
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (600:600:600))
+        (PORT datab (341:341:341) (420:420:420))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (574:574:574) (606:606:606))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (377:377:377))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (629:629:629) (644:644:644))
+        (PORT datab (855:855:855) (844:844:844))
+        (PORT datac (536:536:536) (560:560:560))
+        (PORT datad (527:527:527) (551:551:551))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (557:557:557) (518:518:518))
+        (PORT datab (636:636:636) (650:650:650))
+        (PORT datac (501:501:501) (478:478:478))
+        (PORT datad (734:734:734) (661:661:661))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (280:280:280) (306:306:306))
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (351:351:351) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (352:352:352) (435:435:435))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (351:351:351) (440:440:440))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (449:449:449))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (451:451:451))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (811:811:811) (727:727:727))
+        (PORT datab (635:635:635) (648:648:648))
+        (PORT datac (506:506:506) (483:483:483))
+        (PORT datad (449:449:449) (422:422:422))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (306:306:306) (344:344:344))
+        (PORT datac (331:331:331) (437:437:437))
+        (PORT datad (527:527:527) (549:549:549))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1440:1440:1440) (1427:1427:1427))
+        (PORT clrn (1883:1883:1883) (1862:1862:1862))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1319:1319:1319) (1273:1273:1273))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1475:1475:1475) (1423:1423:1423))
+        (PORT datab (1359:1359:1359) (1341:1341:1341))
+        (PORT datac (864:864:864) (825:825:825))
+        (PORT datad (1466:1466:1466) (1446:1446:1446))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (238:238:238) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (324:324:324) (365:365:365))
+        (PORT datad (349:349:349) (433:433:433))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1475:1475:1475) (1423:1423:1423))
+        (PORT datab (1357:1357:1357) (1339:1339:1339))
+        (PORT datac (864:864:864) (825:825:825))
+        (PORT datad (1465:1465:1465) (1444:1444:1444))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (392:392:392) (485:485:485))
+        (PORT datab (591:591:591) (614:614:614))
+        (PORT datad (465:465:465) (440:440:440))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (463:463:463))
+        (PORT datab (387:387:387) (479:479:479))
+        (PORT datac (279:279:279) (316:316:316))
+        (PORT datad (348:348:348) (431:431:431))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (481:481:481))
+        (PORT datad (255:255:255) (279:279:279))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (477:477:477))
+        (PORT datac (346:346:346) (443:443:443))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (386:386:386) (485:485:485))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1326:1326:1326) (1309:1309:1309))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (322:322:322))
+        (PORT datad (534:534:534) (571:571:571))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (539:539:539) (558:558:558))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1319:1319:1319) (1260:1260:1260))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1271:1271:1271) (1218:1218:1218))
+        (PORT datab (984:984:984) (967:967:967))
+        (PORT datad (318:318:318) (396:396:396))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (569:569:569) (587:587:587))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1309:1309:1309) (1255:1255:1255))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (545:545:545) (568:568:568))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (307:307:307) (348:348:348))
+        (PORT datab (379:379:379) (465:465:465))
+        (PORT datad (548:548:548) (559:559:559))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (573:573:573))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1365:1365:1365) (1346:1346:1346))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (792:792:792) (771:771:771))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (761:761:761) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT asdata (812:812:812) (900:900:900))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (994:994:994))
+        (PORT datab (367:367:367) (447:447:447))
+        (PORT datad (973:973:973) (975:975:975))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT asdata (810:810:810) (898:898:898))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1023:1023:1023) (1040:1040:1040))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (861:861:861))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (507:507:507) (532:532:532))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (975:975:975) (990:990:990))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (597:597:597) (608:608:608))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1715:1715:1715) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (662:662:662) (670:670:670))
+        (PORT datab (1009:1009:1009) (992:992:992))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (278:278:278) (310:310:310))
+        (PORT datab (859:859:859) (797:797:797))
+        (PORT datac (442:442:442) (422:422:422))
+        (PORT datad (809:809:809) (756:756:756))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (1457:1457:1457) (1407:1407:1407))
+        (PORT datac (1269:1269:1269) (1186:1186:1186))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (587:587:587) (625:625:625))
+        (PORT datab (388:388:388) (481:481:481))
+        (PORT datad (889:889:889) (847:847:847))
+        (IOPATH dataa combout (405:405:405) (407:407:407))
+        (IOPATH datab combout (410:410:410) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1464:1464:1464) (1423:1423:1423))
+        (PORT datab (388:388:388) (481:481:481))
+        (PORT datac (346:346:346) (425:425:425))
+        (PORT datad (1306:1306:1306) (1274:1274:1274))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (382:382:382) (480:480:480))
+        (PORT datad (246:246:246) (267:267:267))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1385:1385:1385) (1356:1356:1356))
+        (PORT datad (1284:1284:1284) (1241:1241:1241))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (461:461:461))
+        (PORT datab (385:385:385) (478:478:478))
+        (PORT datac (282:282:282) (320:320:320))
+        (PORT datad (348:348:348) (432:432:432))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (240:240:240) (259:259:259))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (481:481:481))
+        (PORT datab (387:387:387) (481:481:481))
+        (PORT datac (346:346:346) (443:443:443))
+        (PORT datad (578:578:578) (612:612:612))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (296:296:296) (375:375:375))
+        (PORT datad (1311:1311:1311) (1267:1267:1267))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1184:1184:1184) (1141:1141:1141))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (971:971:971) (997:997:997))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1446:1446:1446) (1416:1416:1416))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (803:803:803) (883:883:883))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (542:542:542) (562:562:562))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (973:973:973))
+        (PORT datab (936:936:936) (925:925:925))
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (326:326:326))
+        (PORT datab (334:334:334) (410:410:410))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (325:325:325))
+        (PORT datab (898:898:898) (822:822:822))
+        (PORT datad (246:246:246) (268:268:268))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (910:910:910) (883:883:883))
+        (PORT datab (892:892:892) (866:866:866))
+        (PORT datac (752:752:752) (678:678:678))
+        (PORT datad (506:506:506) (532:532:532))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (576:576:576) (620:620:620))
+        (PORT datab (377:377:377) (467:467:467))
+        (PORT datac (552:552:552) (579:579:579))
+        (PORT datad (263:263:263) (295:295:295))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (389:389:389) (486:486:486))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (620:620:620))
+        (PORT datab (387:387:387) (484:484:484))
+        (PORT datac (355:355:355) (439:439:439))
+        (PORT datad (528:528:528) (565:565:565))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (913:913:913) (886:886:886))
+        (PORT datab (380:380:380) (470:470:470))
+        (PORT datac (855:855:855) (834:834:834))
+        (PORT datad (337:337:337) (421:421:421))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datac (297:297:297) (375:375:375))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (860:860:860) (862:862:862))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1377:1377:1377) (1332:1332:1332))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (PORT datab (368:368:368) (450:450:450))
+        (PORT datac (532:532:532) (516:516:516))
+        (PORT datad (859:859:859) (861:861:861))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (711:711:711) (642:642:642))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (381:381:381) (467:467:467))
+        (PORT datad (263:263:263) (295:295:295))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (620:620:620))
+        (PORT datab (378:378:378) (468:468:468))
+        (PORT datac (552:552:552) (579:579:579))
+        (PORT datad (264:264:264) (296:296:296))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (601:601:601) (636:636:636))
+        (PORT datab (387:387:387) (483:483:483))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (387:387:387) (483:483:483))
+        (PORT datac (351:351:351) (434:434:434))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (575:575:575) (615:615:615))
+        (PORT datad (245:245:245) (270:270:270))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1051:1051:1051) (1058:1058:1058))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1656:1656:1656) (1603:1603:1603))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (764:764:764) (833:833:833))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (759:759:759) (828:828:828))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (314:314:314) (402:402:402))
+        (PORT datad (324:324:324) (404:404:404))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (477:477:477))
+        (PORT datab (392:392:392) (486:486:486))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1474:1474:1474) (1459:1459:1459))
+        (PORT ena (1575:1575:1575) (1483:1483:1483))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1286:1286:1286) (1243:1243:1243))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1330:1330:1330) (1283:1283:1283))
+        (PORT datac (356:356:356) (441:441:441))
+        (PORT datad (1211:1211:1211) (1150:1150:1150))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (PORT datab (341:341:341) (420:420:420))
+        (PORT datac (307:307:307) (394:394:394))
+        (PORT datad (319:319:319) (398:398:398))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1429:1429:1429) (1386:1386:1386))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1328:1328:1328) (1280:1280:1280))
+        (PORT datab (1249:1249:1249) (1190:1190:1190))
+        (PORT datac (353:353:353) (438:438:438))
+        (PORT datad (946:946:946) (938:938:938))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (330:330:330) (413:413:413))
+        (PORT datad (829:829:829) (787:787:787))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1457:1457:1457) (1419:1419:1419))
+        (PORT datac (332:332:332) (416:416:416))
+        (PORT datad (826:826:826) (784:784:784))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1848:1848:1848) (1802:1802:1802))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1456:1456:1456) (1418:1418:1418))
+        (PORT datab (1660:1660:1660) (1584:1584:1584))
+        (PORT datac (328:328:328) (411:411:411))
+        (PORT datad (827:827:827) (785:785:785))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (543:543:543) (569:569:569))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1321:1321:1321) (1319:1319:1319))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (798:798:798) (777:777:777))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1055:1055:1055) (1064:1064:1064))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1680:1680:1680) (1608:1608:1608))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (846:846:846) (809:809:809))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (762:762:762) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (PORT datab (550:550:550) (578:578:578))
+        (PORT datac (327:327:327) (411:411:411))
+        (PORT datad (1572:1572:1572) (1421:1421:1421))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (900:900:900) (854:854:854))
+        (PORT datad (734:734:734) (669:669:669))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1772:1772:1772) (1735:1735:1735))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (297:297:297) (335:335:335))
+        (PORT datac (339:339:339) (428:428:428))
+        (PORT datad (553:553:553) (586:586:586))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (595:595:595) (566:566:566))
+        (PORT datab (370:370:370) (454:454:454))
+        (PORT datad (861:861:861) (863:863:863))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (833:833:833) (808:808:808))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1179:1179:1179) (1120:1120:1120))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (1284:1284:1284) (1237:1237:1237))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (858:858:858) (826:826:826))
+        (PORT datab (354:354:354) (441:441:441))
+        (PORT datac (358:358:358) (443:443:443))
+        (PORT datad (272:272:272) (292:292:292))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (859:859:859) (826:826:826))
+        (PORT datab (1206:1206:1206) (1153:1153:1153))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (902:902:902) (904:904:904))
+        (PORT datab (602:602:602) (609:609:609))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (554:554:554) (593:593:593))
+        (PORT datab (955:955:955) (929:929:929))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (612:612:612) (620:620:620))
+        (PORT datab (883:883:883) (885:885:885))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (336:336:336) (419:419:419))
+        (PORT datab (532:532:532) (559:559:559))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (421:421:421))
+        (PORT datad (528:528:528) (549:549:549))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (488:488:488) (478:478:478))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (239:239:239) (257:257:257))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (1983:1983:1983) (1881:1881:1881))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (279:279:279) (305:305:305))
+        (PORT datac (235:235:235) (261:261:261))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2015:2015:2015) (1838:1838:1838))
+        (PORT datab (370:370:370) (452:452:452))
+        (PORT datac (1631:1631:1631) (1576:1576:1576))
+        (PORT datad (826:826:826) (791:791:791))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (894:894:894) (834:834:834))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (836:836:836) (776:776:776))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (450:450:450))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (455:455:455))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (446:446:446))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (359:359:359) (455:455:455))
+        (PORT datac (318:318:318) (412:412:412))
+        (PORT datad (321:321:321) (404:404:404))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (319:319:319) (415:415:415))
+        (PORT datad (320:320:320) (407:407:407))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (357:357:357) (452:452:452))
+        (PORT datac (317:317:317) (411:411:411))
+        (PORT datad (318:318:318) (401:401:401))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (360:360:360) (449:449:449))
+        (PORT datac (319:319:319) (415:415:415))
+        (PORT datad (248:248:248) (271:271:271))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (490:490:490) (475:475:475))
+        (PORT datac (1968:1968:1968) (1887:1887:1887))
+        (PORT datad (783:783:783) (726:726:726))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (918:918:918) (904:904:904))
+        (PORT datab (2008:2008:2008) (1923:1923:1923))
+        (PORT datac (1946:1946:1946) (1865:1865:1865))
+        (PORT datad (539:539:539) (560:560:560))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (2010:2010:2010) (1925:1925:1925))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (868:868:868))
+        (PORT datab (941:941:941) (925:925:925))
+        (PORT datac (1707:1707:1707) (1633:1633:1633))
+        (PORT datad (334:334:334) (414:414:414))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (849:849:849) (846:846:846))
+        (PORT datac (895:895:895) (881:881:881))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2339:2339:2339) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (913:913:913) (928:928:928))
+        (PORT datab (341:341:341) (420:420:420))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (434:434:434))
+        (PORT datab (343:343:343) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (376:376:376))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (888:888:888) (888:888:888))
+        (PORT datab (865:865:865) (770:770:770))
+        (PORT datac (903:903:903) (887:887:887))
+        (PORT datad (931:931:931) (902:902:902))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (442:442:442))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (453:453:453))
+        (PORT datab (352:352:352) (442:442:442))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (313:313:313) (394:394:394))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (959:959:959) (944:944:944))
+        (PORT datac (911:911:911) (901:901:901))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (932:932:932) (925:925:925))
+        (PORT datab (289:289:289) (318:318:318))
+        (PORT datac (813:813:813) (755:755:755))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (433:433:433))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (350:350:350) (440:440:440))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (449:449:449))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (453:453:453))
+        (PORT datab (352:352:352) (441:441:441))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (960:960:960) (945:945:945))
+        (PORT datab (965:965:965) (941:941:941))
+        (PORT datac (1124:1124:1124) (990:990:990))
+        (PORT datad (248:248:248) (275:275:275))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1193:1193:1193) (1146:1146:1146))
+        (PORT datad (1187:1187:1187) (1123:1123:1123))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (1249:1249:1249) (1173:1173:1173))
+        (PORT datac (347:347:347) (466:466:466))
+        (PORT datad (310:310:310) (393:393:393))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1193:1193:1193) (1147:1147:1147))
+        (PORT datab (1252:1252:1252) (1177:1177:1177))
+        (PORT datad (291:291:291) (326:326:326))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (377:377:377))
+        (PORT datab (391:391:391) (507:507:507))
+        (PORT datad (256:256:256) (289:289:289))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (602:602:602))
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datac (350:350:350) (470:470:470))
+        (PORT datad (346:346:346) (446:446:446))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (377:377:377))
+        (PORT datab (297:297:297) (332:332:332))
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (434:434:434))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (445:445:445))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (632:632:632) (648:648:648))
+        (PORT datac (854:854:854) (833:833:833))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT asdata (1677:1677:1677) (1619:1619:1619))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (418:418:418))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (421:421:421))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (420:420:420))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (436:436:436))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (494:494:494) (472:472:472))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (839:839:839) (785:785:785))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1317:1317:1317) (1271:1271:1271))
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datad (1043:1043:1043) (938:938:938))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (628:628:628) (642:642:642))
+        (PORT datab (578:578:578) (602:602:602))
+        (PORT datac (527:527:527) (561:561:561))
+        (PORT datad (559:559:559) (579:579:579))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (324:324:324))
+        (PORT datab (279:279:279) (305:305:305))
+        (PORT datac (320:320:320) (398:398:398))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (434:434:434))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (624:624:624) (638:638:638))
+        (PORT datab (575:575:575) (599:599:599))
+        (PORT datac (524:524:524) (557:557:557))
+        (PORT datad (556:556:556) (575:575:575))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (600:600:600))
+        (PORT datab (559:559:559) (585:585:585))
+        (PORT datac (533:533:533) (549:549:549))
+        (PORT datad (552:552:552) (570:570:570))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (836:836:836) (819:819:819))
+        (PORT datab (617:617:617) (622:622:622))
+        (PORT datac (787:787:787) (765:765:765))
+        (PORT datad (522:522:522) (541:541:541))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1524:1524:1524) (1455:1455:1455))
+        (PORT datab (558:558:558) (583:583:583))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (632:632:632) (648:648:648))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (854:854:854) (833:833:833))
+        (PORT datad (245:245:245) (269:269:269))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (379:379:379) (466:466:466))
+        (PORT datac (348:348:348) (447:447:447))
+        (PORT datad (254:254:254) (278:278:278))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (377:377:377) (467:467:467))
+        (PORT datad (245:245:245) (266:266:266))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (881:881:881) (867:867:867))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (886:886:886))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (916:916:916) (915:915:915))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1140:1140:1140) (1130:1130:1130))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1322:1322:1322) (1307:1307:1307))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (760:760:760) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (1407:1407:1407) (1398:1398:1398))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (865:865:865) (853:853:853))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1265:1265:1265) (1225:1225:1225))
+        (PORT datab (361:361:361) (438:438:438))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (591:591:591) (628:628:628))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (339:339:339) (429:429:429))
+        (PORT datad (318:318:318) (405:405:405))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (298:298:298) (343:343:343))
+        (PORT datab (472:472:472) (455:455:455))
+        (PORT datac (511:511:511) (483:483:483))
+        (PORT datad (573:573:573) (594:594:594))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1367:1367:1367) (1362:1362:1362))
+        (PORT datab (368:368:368) (464:464:464))
+        (PORT datac (484:484:484) (459:459:459))
+        (PORT datad (275:275:275) (297:297:297))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1441:1441:1441) (1423:1423:1423))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (762:762:762) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (857:857:857))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1676:1676:1676) (1565:1565:1565))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT asdata (789:789:789) (859:859:859))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (549:549:549) (576:576:576))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (626:626:626))
+        (PORT datab (631:631:631) (635:635:635))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (931:931:931) (925:925:925))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (1884:1884:1884) (1779:1779:1779))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1410:1410:1410) (1388:1388:1388))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (462:462:462))
+        (PORT datab (377:377:377) (465:465:465))
+        (PORT datac (500:500:500) (480:480:480))
+        (PORT datad (338:338:338) (415:415:415))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1232:1232:1232))
+        (PORT datab (983:983:983) (947:947:947))
+        (PORT datad (282:282:282) (305:305:305))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (598:598:598) (609:609:609))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1134:1134:1134) (1128:1128:1128))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (842:842:842) (825:825:825))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (939:939:939) (923:923:923))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (937:937:937))
+        (PORT datab (549:549:549) (585:585:585))
+        (PORT datad (294:294:294) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (810:810:810) (811:811:811))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (323:323:323) (394:394:394))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (334:334:334) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (321:321:321) (391:391:391))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (555:555:555) (594:594:594))
+        (PORT datab (887:887:887) (893:893:893))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (310:310:310))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (236:236:236) (263:263:263))
+        (PORT datad (834:834:834) (764:764:764))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (286:286:286) (318:318:318))
+        (PORT datac (1848:1848:1848) (1742:1742:1742))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (886:886:886))
+        (PORT datab (379:379:379) (470:470:470))
+        (PORT datad (781:781:781) (719:719:719))
+        (IOPATH dataa combout (405:405:405) (407:407:407))
+        (IOPATH datab combout (410:410:410) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (948:948:948) (954:954:954))
+        (PORT datab (565:565:565) (600:600:600))
+        (PORT datac (300:300:300) (330:330:330))
+        (PORT datad (909:909:909) (908:908:908))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (945:945:945) (945:945:945))
+        (PORT datab (856:856:856) (861:861:861))
+        (PORT datad (792:792:792) (723:723:723))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (856:856:856) (862:862:862))
+        (PORT datad (792:792:792) (723:723:723))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (854:854:854) (826:826:826))
+        (PORT datab (956:956:956) (958:958:958))
+        (PORT datac (828:828:828) (828:828:828))
+        (PORT datad (459:459:459) (433:433:433))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (990:990:990) (971:971:971))
+        (PORT datad (252:252:252) (276:276:276))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (922:922:922) (927:927:927))
+        (PORT datab (363:363:363) (456:456:456))
+        (PORT datac (324:324:324) (420:420:420))
+        (PORT datad (933:933:933) (927:927:927))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (993:993:993) (974:974:974))
+        (PORT datac (322:322:322) (418:418:418))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (454:454:454))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (424:424:424))
+        (PORT datac (515:515:515) (545:545:545))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (944:944:944) (944:944:944))
+        (PORT datab (380:380:380) (470:470:470))
+        (PORT datac (324:324:324) (403:403:403))
+        (PORT datad (817:817:817) (819:819:819))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (297:297:297) (375:375:375))
+        (PORT datad (863:863:863) (858:858:858))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1893:1893:1893) (1790:1790:1790))
+        (PORT datab (288:288:288) (320:320:320))
+        (PORT datac (523:523:523) (561:561:561))
+        (PORT datad (248:248:248) (270:270:270))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (949:949:949) (954:954:954))
+        (PORT datab (973:973:973) (961:961:961))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (461:461:461))
+        (PORT datab (852:852:852) (856:856:856))
+        (PORT datac (791:791:791) (707:707:707))
+        (PORT datad (874:874:874) (886:886:886))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (459:459:459))
+        (PORT datab (991:991:991) (971:971:971))
+        (PORT datad (253:253:253) (277:277:277))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (454:454:454))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (982:982:982) (1003:1003:1003))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (787:787:787) (856:856:856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1238:1238:1238) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (382:382:382))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (802:802:802) (780:780:780))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (831:831:831) (825:825:825))
+        (PORT datab (613:613:613) (617:617:617))
+        (PORT datad (791:791:791) (760:760:760))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (1332:1332:1332) (1310:1310:1310))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (319:319:319) (410:410:410))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (831:831:831) (807:807:807))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (787:787:787) (873:873:873))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (831:831:831) (800:800:800))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (761:761:761) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (431:431:431))
+        (PORT datab (575:575:575) (591:591:591))
+        (PORT datad (294:294:294) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (537:537:537) (566:566:566))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (964:964:964) (958:958:958))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT asdata (763:763:763) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (874:874:874) (885:885:885))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT asdata (1597:1597:1597) (1523:1523:1523))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (912:912:912) (883:883:883))
+        (PORT datab (1184:1184:1184) (1107:1107:1107))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (448:448:448) (424:424:424))
+        (PORT datad (770:770:770) (705:705:705))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1118:1118:1118) (1020:1020:1020))
+        (PORT datab (1834:1834:1834) (1684:1684:1684))
+        (PORT datac (243:243:243) (274:274:274))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1419:1419:1419) (1410:1410:1410))
+        (PORT datab (991:991:991) (977:977:977))
+        (PORT datac (1194:1194:1194) (1158:1158:1158))
+        (PORT datad (827:827:827) (769:769:769))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (833:833:833))
+        (PORT datad (329:329:329) (402:402:402))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1309:1309:1309) (1230:1230:1230))
+        (PORT datab (982:982:982) (946:946:946))
+        (PORT datac (359:359:359) (447:447:447))
+        (PORT datad (282:282:282) (305:305:305))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (390:390:390) (492:492:492))
+        (PORT datad (255:255:255) (280:280:280))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (395:395:395) (498:498:498))
+        (PORT datab (381:381:381) (468:468:468))
+        (PORT datad (252:252:252) (277:277:277))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (380:380:380) (471:471:471))
+        (PORT datad (246:246:246) (268:268:268))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (PORT datad (320:320:320) (391:391:391))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (391:391:391) (494:494:494))
+        (PORT datab (379:379:379) (469:469:469))
+        (PORT datac (363:363:363) (451:451:451))
+        (PORT datad (339:339:339) (423:423:423))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (462:462:462))
+        (PORT datab (980:980:980) (943:943:943))
+        (PORT datac (340:340:340) (433:433:433))
+        (PORT datad (1242:1242:1242) (1176:1176:1176))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (296:296:296) (374:374:374))
+        (PORT datad (498:498:498) (525:525:525))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (340:340:340) (417:417:417))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (566:566:566) (533:533:533))
+        (PORT datab (382:382:382) (471:471:471))
+        (PORT datad (338:338:338) (415:415:415))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (1840:1840:1840) (1817:1817:1817))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (379:379:379) (469:469:469))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1290:1290:1290) (1255:1255:1255))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1280:1280:1280) (1245:1245:1245))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (972:972:972) (990:990:990))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (904:904:904) (869:869:869))
+        (PORT datab (934:934:934) (890:890:890))
+        (PORT datad (293:293:293) (362:362:362))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1832:1832:1832) (1682:1682:1682))
+        (PORT datac (247:247:247) (278:278:278))
+        (PORT datad (245:245:245) (267:267:267))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4197:4197:4197) (4406:4406:4406))
+        (PORT datab (1234:1234:1234) (1141:1141:1141))
+        (PORT datac (1266:1266:1266) (1240:1240:1240))
+        (PORT datad (882:882:882) (857:857:857))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1338:1338:1338) (1323:1323:1323))
+        (PORT datad (928:928:928) (924:924:924))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1364:1364:1364) (1359:1359:1359))
+        (PORT datab (364:364:364) (459:459:459))
+        (PORT datac (484:484:484) (458:458:458))
+        (PORT datad (275:275:275) (297:297:297))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1313:1313:1313) (1290:1290:1290))
+        (PORT datab (926:926:926) (902:902:902))
+        (PORT datac (1179:1179:1179) (1102:1102:1102))
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1311:1311:1311) (1288:1288:1288))
+        (PORT datab (925:925:925) (900:900:900))
+        (PORT datac (1182:1182:1182) (1106:1106:1106))
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1286:1286:1286))
+        (PORT datab (924:924:924) (899:899:899))
+        (PORT datac (1184:1184:1184) (1108:1108:1108))
+        (PORT datad (323:323:323) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1286:1286:1286))
+        (PORT datab (924:924:924) (899:899:899))
+        (PORT datac (1183:1183:1183) (1108:1108:1108))
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1309:1309:1309) (1285:1285:1285))
+        (PORT datab (923:923:923) (898:898:898))
+        (PORT datac (1185:1185:1185) (1109:1109:1109))
+        (PORT datad (323:323:323) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1274:1274:1274) (1194:1194:1194))
+        (PORT datab (1308:1308:1308) (1219:1219:1219))
+        (PORT datac (1626:1626:1626) (1583:1583:1583))
+        (PORT datad (911:911:911) (907:907:907))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1274:1274:1274) (1194:1194:1194))
+        (PORT datab (1307:1307:1307) (1219:1219:1219))
+        (PORT datac (1625:1625:1625) (1582:1582:1582))
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1676:1676:1676) (1642:1642:1642))
+        (PORT datab (1308:1308:1308) (1219:1219:1219))
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (1202:1202:1202) (1134:1134:1134))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1635:1635:1635) (1594:1594:1594))
+        (PORT datad (306:306:306) (380:380:380))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (331:331:331) (409:409:409))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1676:1676:1676) (1565:1565:1565))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (986:986:986) (971:971:971))
+        (PORT datac (1344:1344:1344) (1330:1330:1330))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1339:1339:1339) (1324:1324:1324))
+        (PORT datad (887:887:887) (885:885:885))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1352:1352:1352) (1339:1339:1339))
+        (PORT datad (931:931:931) (921:921:921))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1350:1350:1350) (1337:1337:1337))
+        (PORT datad (944:944:944) (934:934:934))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1627:1627:1627) (1584:1584:1584))
+        (PORT datad (911:911:911) (908:908:908))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1633:1633:1633) (1592:1592:1592))
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (435:435:435))
+        (PORT datac (1624:1624:1624) (1581:1581:1581))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1272:1272:1272) (1191:1191:1191))
+        (PORT datab (1309:1309:1309) (1221:1221:1221))
+        (PORT datac (1632:1632:1632) (1590:1590:1590))
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1622:1622:1622) (1578:1578:1578))
+        (PORT datad (307:307:307) (381:381:381))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datac (1632:1632:1632) (1591:1591:1591))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (440:440:440))
+        (PORT datac (1634:1634:1634) (1593:1593:1593))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (921:921:921) (907:907:907))
+        (PORT datac (1349:1349:1349) (1336:1336:1336))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (924:924:924) (911:911:911))
+        (PORT datab (1178:1178:1178) (1103:1103:1103))
+        (PORT datac (1342:1342:1342) (1328:1328:1328))
+        (PORT datad (860:860:860) (819:819:819))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1348:1348:1348) (1334:1334:1334))
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (440:440:440))
+        (PORT datac (1351:1351:1351) (1338:1338:1338))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (438:438:438))
+        (PORT datab (1177:1177:1177) (1103:1103:1103))
+        (PORT datac (1343:1343:1343) (1329:1329:1329))
+        (PORT datad (860:860:860) (819:819:819))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1341:1341:1341) (1326:1326:1326))
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (290:290:290) (328:328:328))
+        (PORT datab (353:353:353) (440:440:440))
+        (PORT datac (351:351:351) (471:471:471))
+        (PORT datad (842:842:842) (786:786:786))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|tx\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (1251:1251:1251) (1176:1176:1176))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|tx)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+)
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo
new file mode 100644
index 0000000..0bcbc2e
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo
@@ -0,0 +1,24509 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "06/02/2023 04:03:14"
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module uart_sd (
+	sys_clk,
+	sys_rst_n,
+	rx,
+	sd_miso,
+	sd_clk,
+	sd_cs_n,
+	sd_mosi,
+	tx);
+input 	sys_clk;
+input 	sys_rst_n;
+input 	rx;
+input 	sd_miso;
+output 	sd_clk;
+output 	sd_cs_n;
+output 	sd_mosi;
+output 	tx;
+
+// Design Ports Information
+// sd_clk	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_cs_n	=>  Location: PIN_E7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_mosi	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// tx	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_rst_n	=>  Location: PIN_U20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sys_clk	=>  Location: PIN_T22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// sd_miso	=>  Location: PIN_E9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// rx	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("uart_sd_min_1200mv_0c_v_fast.sdo");
+// synopsys translate_on
+
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ;
+wire \uart_tx_inst|baud_cnt[2]~17_combout ;
+wire \uart_tx_inst|baud_cnt[5]~23_combout ;
+wire \uart_tx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ;
+wire \uart_rx_inst|Add1~4_combout ;
+wire \uart_rx_inst|baud_cnt[4]~21_combout ;
+wire \uart_rx_inst|baud_cnt[10]~33_combout ;
+wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ;
+wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ;
+wire \data_rw_ctrl_inst|send_data_num[7]~27 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~29 ;
+wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ;
+wire \data_rw_ctrl_inst|send_data_num[9]~31 ;
+wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ;
+wire \data_rw_ctrl_inst|send_data_num[10]~33 ;
+wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ;
+wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ;
+wire \uart_tx_inst|always0~0_combout ;
+wire \uart_tx_inst|Mux0~1_combout ;
+wire \uart_tx_inst|Mux0~2_combout ;
+wire \uart_tx_inst|Mux0~3_combout ;
+wire \uart_tx_inst|Mux0~4_combout ;
+wire \uart_tx_inst|Mux0~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \uart_tx_inst|work_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \uart_tx_inst|Add1~1_combout ;
+wire \uart_tx_inst|bit_cnt[2]~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ;
+wire \data_rw_ctrl_inst|tx_flag~q ;
+wire \uart_tx_inst|work_en~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ;
+wire \uart_rx_inst|always8~0_combout ;
+wire \uart_rx_inst|rx_reg3~q ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ;
+wire \uart_rx_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ;
+wire \uart_rx_inst|rx_reg2~q ;
+wire \data_rw_ctrl_inst|always3~2_combout ;
+wire \uart_rx_inst|Equal1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ;
+wire \uart_rx_inst|rx_reg1~q ;
+wire \uart_rx_inst|start_nedge~q ;
+wire \uart_rx_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \uart_rx_inst|rx_data[7]~0_combout ;
+wire \uart_rx_inst|rx_reg1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ;
+wire \rx~input_o ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|tx_flag~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ;
+wire \uart_rx_inst|po_data[1]~feeder_combout ;
+wire \uart_rx_inst|rx_data[0]~feeder_combout ;
+wire \uart_rx_inst|po_data[5]~feeder_combout ;
+wire \uart_rx_inst|rx_data[4]~feeder_combout ;
+wire \uart_rx_inst|po_data[6]~feeder_combout ;
+wire \uart_rx_inst|rx_data[5]~feeder_combout ;
+wire \uart_rx_inst|po_data[7]~feeder_combout ;
+wire \uart_rx_inst|rx_data[6]~feeder_combout ;
+wire \uart_rx_inst|po_data[3]~feeder_combout ;
+wire \uart_rx_inst|rx_data[2]~feeder_combout ;
+wire \uart_rx_inst|po_data[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ;
+wire \uart_rx_inst|rx_reg2~feeder_combout ;
+wire \sys_clk~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ;
+wire \sys_rst_n~input_o ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ;
+wire \rst_n~0_combout ;
+wire \rst_n~0clkctrl_outclk ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_miso~input_o ;
+wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ;
+wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|init_end~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_en~q ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ;
+wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ;
+wire \data_rw_ctrl_inst|wr_busy_dly~q ;
+wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ;
+wire \data_rw_ctrl_inst|rd_en~q ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ;
+wire \sd_ctrl_inst|sd_init_inst|cs_n~q ;
+wire \sd_ctrl_inst|sd_cs_n~1_combout ;
+wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ;
+wire \sd_ctrl_inst|sd_init_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|mosi~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \uart_rx_inst|Add1~1 ;
+wire \uart_rx_inst|Add1~3 ;
+wire \uart_rx_inst|Add1~5 ;
+wire \uart_rx_inst|Add1~6_combout ;
+wire \uart_rx_inst|bit_cnt~0_combout ;
+wire \uart_rx_inst|Add1~0_combout ;
+wire \uart_rx_inst|bit_cnt~1_combout ;
+wire \uart_rx_inst|Add1~2_combout ;
+wire \uart_rx_inst|always4~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~13_combout ;
+wire \uart_rx_inst|Equal1~0_combout ;
+wire \uart_rx_inst|baud_cnt[5]~23_combout ;
+wire \uart_rx_inst|baud_cnt[2]~17_combout ;
+wire \uart_rx_inst|Equal1~1_combout ;
+wire \uart_rx_inst|Equal1~3_combout ;
+wire \uart_rx_inst|work_en~0_combout ;
+wire \uart_rx_inst|work_en~q ;
+wire \uart_rx_inst|always5~0_combout ;
+wire \uart_rx_inst|baud_cnt[0]~14 ;
+wire \uart_rx_inst|baud_cnt[1]~15_combout ;
+wire \uart_rx_inst|baud_cnt[1]~16 ;
+wire \uart_rx_inst|baud_cnt[2]~18 ;
+wire \uart_rx_inst|baud_cnt[3]~19_combout ;
+wire \uart_rx_inst|baud_cnt[3]~20 ;
+wire \uart_rx_inst|baud_cnt[4]~22 ;
+wire \uart_rx_inst|baud_cnt[5]~24 ;
+wire \uart_rx_inst|baud_cnt[6]~25_combout ;
+wire \uart_rx_inst|baud_cnt[6]~26 ;
+wire \uart_rx_inst|baud_cnt[7]~27_combout ;
+wire \uart_rx_inst|baud_cnt[7]~28 ;
+wire \uart_rx_inst|baud_cnt[8]~29_combout ;
+wire \uart_rx_inst|baud_cnt[8]~30 ;
+wire \uart_rx_inst|baud_cnt[9]~31_combout ;
+wire \uart_rx_inst|baud_cnt[9]~32 ;
+wire \uart_rx_inst|baud_cnt[10]~34 ;
+wire \uart_rx_inst|baud_cnt[11]~35_combout ;
+wire \uart_rx_inst|baud_cnt[11]~36 ;
+wire \uart_rx_inst|baud_cnt[12]~37_combout ;
+wire \uart_rx_inst|Equal2~1_combout ;
+wire \uart_rx_inst|Equal2~2_combout ;
+wire \uart_rx_inst|bit_flag~q ;
+wire \uart_rx_inst|always4~1_combout ;
+wire \uart_rx_inst|rx_flag~q ;
+wire \uart_rx_inst|po_flag~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ;
+wire \sd_ctrl_inst|comb~1_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ;
+wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ;
+wire \sd_ctrl_inst|comb~0_combout ;
+wire \sd_ctrl_inst|comb~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ;
+wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ;
+wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ;
+wire \sd_ctrl_inst|sd_write_inst|mosi~q ;
+wire \sd_ctrl_inst|sd_mosi~0_combout ;
+wire \sd_ctrl_inst|sd_mosi~1_combout ;
+wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
+wire \uart_tx_inst|baud_cnt[0]~13_combout ;
+wire \uart_tx_inst|Equal1~0_combout ;
+wire \uart_tx_inst|Equal1~1_combout ;
+wire \uart_tx_inst|baud_cnt[4]~21_combout ;
+wire \uart_tx_inst|Equal1~2_combout ;
+wire \uart_tx_inst|Equal1~3_combout ;
+wire \uart_tx_inst|always1~0_combout ;
+wire \uart_tx_inst|baud_cnt[0]~14 ;
+wire \uart_tx_inst|baud_cnt[1]~15_combout ;
+wire \uart_tx_inst|baud_cnt[1]~16 ;
+wire \uart_tx_inst|baud_cnt[2]~18 ;
+wire \uart_tx_inst|baud_cnt[3]~19_combout ;
+wire \uart_tx_inst|baud_cnt[3]~20 ;
+wire \uart_tx_inst|baud_cnt[4]~22 ;
+wire \uart_tx_inst|baud_cnt[5]~24 ;
+wire \uart_tx_inst|baud_cnt[6]~25_combout ;
+wire \uart_tx_inst|baud_cnt[6]~26 ;
+wire \uart_tx_inst|baud_cnt[7]~27_combout ;
+wire \uart_tx_inst|baud_cnt[7]~28 ;
+wire \uart_tx_inst|baud_cnt[8]~29_combout ;
+wire \uart_tx_inst|baud_cnt[8]~30 ;
+wire \uart_tx_inst|baud_cnt[9]~31_combout ;
+wire \uart_tx_inst|baud_cnt[9]~32 ;
+wire \uart_tx_inst|baud_cnt[10]~34 ;
+wire \uart_tx_inst|baud_cnt[11]~35_combout ;
+wire \uart_tx_inst|baud_cnt[11]~36 ;
+wire \uart_tx_inst|baud_cnt[12]~37_combout ;
+wire \uart_tx_inst|Equal2~0_combout ;
+wire \uart_tx_inst|Equal2~1_combout ;
+wire \uart_tx_inst|bit_flag~q ;
+wire \uart_tx_inst|always3~0_combout ;
+wire \uart_tx_inst|always0~1_combout ;
+wire \uart_tx_inst|bit_cnt[0]~5_combout ;
+wire \uart_tx_inst|bit_cnt[1]~4_combout ;
+wire \uart_tx_inst|Add1~0_combout ;
+wire \uart_tx_inst|bit_cnt[3]~2_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~23 ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ;
+wire \data_rw_ctrl_inst|Equal3~0_combout ;
+wire \data_rw_ctrl_inst|rd_busy_dly~q ;
+wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ;
+wire \data_rw_ctrl_inst|send_data_num[0]~13 ;
+wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ;
+wire \data_rw_ctrl_inst|send_data_num[1]~15 ;
+wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ;
+wire \data_rw_ctrl_inst|always3~0_combout ;
+wire \data_rw_ctrl_inst|send_data_num[2]~17 ;
+wire \data_rw_ctrl_inst|send_data_num[3]~19 ;
+wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ;
+wire \data_rw_ctrl_inst|send_data_num[4]~21 ;
+wire \data_rw_ctrl_inst|send_data_num[5]~23 ;
+wire \data_rw_ctrl_inst|send_data_num[6]~25 ;
+wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ;
+wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ;
+wire \data_rw_ctrl_inst|always3~1_combout ;
+wire \data_rw_ctrl_inst|always3~3_combout ;
+wire \data_rw_ctrl_inst|send_data_en~0_combout ;
+wire \data_rw_ctrl_inst|send_data_en~q ;
+wire \data_rw_ctrl_inst|Equal3~1_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[0]~17 ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[1]~19 ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[2]~21 ;
+wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ;
+wire \data_rw_ctrl_inst|Equal2~3_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[4]~25 ;
+wire \data_rw_ctrl_inst|cnt_wait[5]~28 ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~30 ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[7]~32 ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[8]~34 ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[9]~36 ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[10]~38 ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~40 ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[12]~42 ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~44 ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[14]~46 ;
+wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ;
+wire \data_rw_ctrl_inst|Equal2~0_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ;
+wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ;
+wire \data_rw_ctrl_inst|Equal2~1_combout ;
+wire \data_rw_ctrl_inst|Equal2~2_combout ;
+wire \data_rw_ctrl_inst|Equal2~4_combout ;
+wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ;
+wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ;
+wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ;
+wire \uart_tx_inst|Mux0~0_combout ;
+wire \uart_tx_inst|tx~0_combout ;
+wire \uart_tx_inst|tx~q ;
+wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ;
+wire [12:0] \uart_tx_inst|baud_cnt ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ;
+wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ;
+wire [3:0] \uart_tx_inst|bit_cnt ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ;
+wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ;
+wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ;
+wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ;
+wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ;
+wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ;
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ;
+wire [7:0] \uart_rx_inst|rx_data ;
+wire [7:0] \uart_rx_inst|po_data ;
+wire [3:0] \uart_rx_inst|bit_cnt ;
+wire [12:0] \uart_rx_inst|baud_cnt ;
+wire [11:0] \data_rw_ctrl_inst|send_data_num ;
+wire [15:0] \data_rw_ctrl_inst|cnt_wait ;
+wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ;
+wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ;
+wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ;
+wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ;
+wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ;
+wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ;
+wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ;
+wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ;
+wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ;
+wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ;
+
+wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ;
+wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ;
+
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3];
+assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4];
+
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15];
+assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16];
+
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6];
+assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7];
+
+// Location: PLL_2
+cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 (
+	.areset(!\sys_rst_n~input_o ),
+	.pfdena(vcc),
+	.fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.phaseupdown(gnd),
+	.phasestep(gnd),
+	.scandata(gnd),
+	.scanclk(gnd),
+	.scanclkena(vcc),
+	.configupdate(gnd),
+	.clkswitch(gnd),
+	.inclk({gnd,\sys_clk~input_o }),
+	.phasecounterselect(3'b000),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.activeclock(),
+	.locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.vcooverrange(),
+	.vcounderrange(),
+	.fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ),
+	.clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ),
+	.clkbad());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND)))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: M9K_X13_Y13_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(18'b000000000000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ,
+\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y27_N0
+cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 (
+	.portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9],
+\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2],
+\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}),
+	.portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(9'b000000000),
+	.portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1],
+\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N11
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N7
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0])
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N13
+dffeas \uart_tx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N7
+dffeas \uart_tx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N23
+dffeas \uart_tx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[2]~17_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16  & VCC))
+// \uart_tx_inst|baud_cnt[2]~18  = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_tx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_tx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[5]~23_combout  = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_tx_inst|baud_cnt[5]~24  = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5]))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_tx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_tx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[10]~33_combout  = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32  & VCC))
+// \uart_tx_inst|baud_cnt[10]~34  = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_tx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_tx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N11
+dffeas \data_rw_ctrl_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[5]~27_combout  = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[5]~28  = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[5]~28 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|Add1~4 (
+// Equation(s):
+// \uart_rx_inst|Add1~4_combout  = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3  $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3  & VCC))
+// \uart_rx_inst|Add1~5  = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 ))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~3 ),
+	.combout(\uart_rx_inst|Add1~4_combout ),
+	.cout(\uart_rx_inst|Add1~5 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N11
+dffeas \uart_rx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N23
+dffeas \uart_rx_inst|baud_cnt[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N7
+dffeas \data_rw_ctrl_inst|send_data_num[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N13
+dffeas \data_rw_ctrl_inst|send_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N17
+dffeas \data_rw_ctrl_inst|send_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N19
+dffeas \data_rw_ctrl_inst|send_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N21
+dffeas \data_rw_ctrl_inst|send_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N23
+dffeas \data_rw_ctrl_inst|send_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[4]~21_combout  = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20  & VCC))
+// \uart_rx_inst|baud_cnt[4]~22  = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_rx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_rx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[10]~33_combout  = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32  $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32  & VCC))
+// \uart_rx_inst|baud_cnt[10]~34  = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[9]~32 ),
+	.combout(\uart_rx_inst|baud_cnt[10]~33_combout ),
+	.cout(\uart_rx_inst|baud_cnt[10]~34 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[3]~18_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[3]~19  = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[2]~17 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[3]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[6]~24_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23  & VCC))
+// \data_rw_ctrl_inst|send_data_num[6]~25  = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 ))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[5]~23 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[6]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[7]~26_combout  = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[7]~27  = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[6]~25 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[7]~27 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[8]~28_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27  & VCC))
+// \data_rw_ctrl_inst|send_data_num[8]~29  = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[7]~27 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[8]~29 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[9]~30_combout  = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[9]~31  = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[8]~29 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[9]~31 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[10]~32_combout  = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31  & VCC))
+// \data_rw_ctrl_inst|send_data_num[10]~33  = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[9]~31 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[10]~33 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[11]~34_combout  = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 )
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|send_data_num[10]~33 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~1_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [14])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [15]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & 
+// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # 
+// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout  & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0;
+defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~6_combout  = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~7_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # 
+// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & 
+// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & 
+// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout  = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout  & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & 
+// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout  & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # 
+// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout  = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout  & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout  & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout  & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N15
+dffeas \uart_tx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneive_lcell_comb \uart_tx_inst|always0~0 (
+// Equation(s):
+// \uart_tx_inst|always0~0_combout  = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F;
+defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N30
+cycloneive_lcell_comb \uart_tx_inst|Mux0~1 (
+// Equation(s):
+// \uart_tx_inst|Mux0~1_combout  = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b 
+// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2;
+defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Mux0~2 (
+// Equation(s):
+// \uart_tx_inst|Mux0~2_combout  = (\uart_tx_inst|Mux0~1_combout  & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout  & 
+// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))
+
+	.dataa(\uart_tx_inst|Mux0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62;
+defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|Mux0~3 (
+// Equation(s):
+// \uart_tx_inst|Mux0~3_combout  = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0;
+defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneive_lcell_comb \uart_tx_inst|Mux0~4 (
+// Equation(s):
+// \uart_tx_inst|Mux0~4_combout  = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000;
+defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneive_lcell_comb \uart_tx_inst|Mux0~5 (
+// Equation(s):
+// \uart_tx_inst|Mux0~5_combout  = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout ))))
+
+	.dataa(\uart_tx_inst|Mux0~3_combout ),
+	.datab(\uart_tx_inst|Mux0~4_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|Mux0~2_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E;
+defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003;
+defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout  & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout  = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout  = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~0_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N17
+dffeas \uart_rx_inst|po_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N19
+dffeas \uart_rx_inst|po_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N21
+dffeas \uart_rx_inst|po_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N15
+dffeas \uart_rx_inst|po_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N9
+dffeas \uart_rx_inst|po_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N27
+dffeas \uart_rx_inst|po_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N13
+dffeas \uart_rx_inst|po_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N31
+dffeas \uart_rx_inst|po_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|rx_flag~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N21
+dffeas \uart_tx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_tx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneive_lcell_comb \uart_tx_inst|Add1~1 (
+// Equation(s):
+// \uart_tx_inst|Add1~1_combout  = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0;
+defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N14
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[2]~3_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|Add1~1_combout ))))
+
+	.dataa(\uart_tx_inst|Add1~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [2]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[2]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2;
+defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0;
+defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N1
+dffeas \uart_rx_inst|rx_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N11
+dffeas \uart_rx_inst|rx_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N29
+dffeas \uart_rx_inst|rx_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N23
+dffeas \uart_rx_inst|rx_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N27
+dffeas \uart_rx_inst|rx_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[7]~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N25
+dffeas \uart_rx_inst|rx_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N3
+dffeas \uart_rx_inst|rx_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y15_N5
+dffeas \uart_rx_inst|rx_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\uart_rx_inst|always8~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N13
+dffeas \data_rw_ctrl_inst|tx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|tx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|tx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|work_en~0 (
+// Equation(s):
+// \uart_tx_inst|work_en~0_combout  = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q  & !\uart_tx_inst|always0~1_combout ))
+
+	.dataa(\data_rw_ctrl_inst|tx_flag~q ),
+	.datab(gnd),
+	.datac(\uart_tx_inst|work_en~q ),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N27
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [2])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q  & \sd_ctrl_inst|sd_init_inst|miso_dly~q )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N13
+dffeas \uart_rx_inst|bit_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|always8~0 (
+// Equation(s):
+// \uart_rx_inst|always8~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|always4~0_combout  $ (!\uart_rx_inst|bit_cnt [3])))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282;
+defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N31
+dffeas \uart_rx_inst|rx_reg3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_reg2~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg3 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Equal2~0 (
+// Equation(s):
+// \uart_rx_inst|Equal2~0_combout  = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N1
+dffeas \uart_rx_inst|rx_reg2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~2_combout  = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [8]),
+	.datab(\data_rw_ctrl_inst|send_data_num [10]),
+	.datac(\data_rw_ctrl_inst|send_data_num [11]),
+	.datad(\data_rw_ctrl_inst|send_data_num [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002;
+defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N30
+cycloneive_lcell_comb \uart_rx_inst|Equal1~2 (
+// Equation(s):
+// \uart_rx_inst|Equal1~2_combout  = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y10_N3
+dffeas \uart_rx_inst|rx_reg1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|rx_reg1~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_reg1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_reg1 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N7
+dffeas \uart_rx_inst|start_nedge (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always3~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|start_nedge~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true";
+defparam \uart_rx_inst|start_nedge .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|always3~0 (
+// Equation(s):
+// \uart_rx_inst|always3~0_combout  = (!\uart_rx_inst|rx_reg3~q  & \uart_rx_inst|rx_reg2~q )
+
+	.dataa(\uart_rx_inst|rx_reg3~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg2~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050;
+defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 (
+// Equation(s):
+// \uart_rx_inst|rx_data[7]~0_combout  = !\uart_rx_inst|rx_reg3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\uart_rx_inst|rx_reg3~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F;
+defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 (
+// Equation(s):
+// \uart_rx_inst|rx_reg1~0_combout  = !\rx~input_o 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\rx~input_o ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF;
+defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneive_io_ibuf \rx~input (
+	.i(rx),
+	.ibar(gnd),
+	.o(\rx~input_o ));
+// synopsys translate_off
+defparam \rx~input .bus_hold = "false";
+defparam \rx~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|tx_flag~feeder_combout  = \data_rw_ctrl_inst|rd_fifo_rd_en~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N16
+cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[1]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N2
+cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[0]~feeder_combout  = \uart_rx_inst|rx_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N18
+cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[5]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N4
+cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[4]~feeder_combout  = \uart_rx_inst|rx_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [5]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N20
+cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[6]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N10
+cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[5]~feeder_combout  = \uart_rx_inst|rx_data [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [6]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N8
+cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[7]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N28
+cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[6]~feeder_combout  = \uart_rx_inst|rx_data [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [7]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N26
+cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[3]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N22
+cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_data[2]~feeder_combout  = \uart_rx_inst|rx_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y15_N12
+cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder (
+// Equation(s):
+// \uart_rx_inst|po_data[0]~feeder_combout  = \uart_rx_inst|rx_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_data [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|po_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y10_N0
+cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder (
+// Equation(s):
+// \uart_rx_inst|rx_reg2~feeder_combout  = \uart_rx_inst|rx_reg1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_rx_inst|rx_reg1~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|rx_reg2~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00;
+defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOOBUF_X5_Y29_N23
+cycloneive_io_obuf \sd_clk~output (
+	.i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_clk),
+	.obar());
+// synopsys translate_off
+defparam \sd_clk~output .bus_hold = "false";
+defparam \sd_clk~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y29_N23
+cycloneive_io_obuf \sd_cs_n~output (
+	.i(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_cs_n),
+	.obar());
+// synopsys translate_off
+defparam \sd_cs_n~output .bus_hold = "false";
+defparam \sd_cs_n~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X1_Y29_N9
+cycloneive_io_obuf \sd_mosi~output (
+	.i(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(sd_mosi),
+	.obar());
+// synopsys translate_off
+defparam \sd_mosi~output .bus_hold = "false";
+defparam \sd_mosi~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N16
+cycloneive_io_obuf \tx~output (
+	.i(!\uart_tx_inst|tx~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(tx),
+	.obar());
+// synopsys translate_off
+defparam \tx~output .bus_hold = "false";
+defparam \tx~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N22
+cycloneive_io_ibuf \sys_clk~input (
+	.i(sys_clk),
+	.ibar(gnd),
+	.o(\sys_clk~input_o ));
+// synopsys translate_off
+defparam \sys_clk~input .bus_hold = "false";
+defparam \sys_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y4_N1
+cycloneive_io_ibuf \sys_rst_n~input (
+	.i(sys_rst_n),
+	.ibar(gnd),
+	.o(\sys_rst_n~input_o ));
+// synopsys translate_off
+defparam \sys_rst_n~input .bus_hold = "false";
+defparam \sys_rst_n~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N0
+cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder (
+// Equation(s):
+// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout  = VCC
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y1_N1
+dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
+	.asdata(vcc),
+	.clrn(\sys_rst_n~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true";
+defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y1_N26
+cycloneive_lcell_comb \rst_n~0 (
+// Equation(s):
+// \rst_n~0_combout  = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )
+
+	.dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ),
+	.datab(\sys_rst_n~input_o ),
+	.datac(gnd),
+	.datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ),
+	.cin(gnd),
+	.combout(\rst_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \rst_n~0 .lut_mask = 16'h77FF;
+defparam \rst_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G16
+cycloneive_clkctrl \rst_n~0clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\rst_n~0_combout }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\rst_n~0clkctrl_outclk ));
+// synopsys translate_off
+defparam \rst_n~0clkctrl .clock_type = "global clock";
+defparam \rst_n~0clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X11_Y29_N29
+cycloneive_io_ibuf \sd_miso~input (
+	.i(sd_miso),
+	.ibar(gnd),
+	.o(\sd_miso~input_o ));
+// synopsys translate_off
+defparam \sd_miso~input .bus_hold = "false";
+defparam \sd_miso~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|miso_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_miso~input_o ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout  & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & (((\sd_ctrl_inst|sd_read_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8;
+defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N3
+dffeas \sd_ctrl_inst|sd_read_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout  & \sd_ctrl_inst|sd_read_inst|ack_en~q ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N19
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_read_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N27
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout  & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout  = (!\sd_miso~input_o  & (\sd_ctrl_inst|sd_init_inst|miso_dly~q  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout  & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450;
+defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  = (\sd_ctrl_inst|sd_init_inst|ack_en~q  & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout  = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout  & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [11]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [12]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [13]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [14]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y24_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [15]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [17]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [18]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [19]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N31
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [29]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [30]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N7
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [32]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N29
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [33]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [36]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N3
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|ack_data [37]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout  = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]),
+	.datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]),
+	.datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N19
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20  & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout  = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N27
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N13
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout  = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2;
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N9
+dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0;
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|WideOr18~combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout  & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C;
+defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N17
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20  
+// & VCC))
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22  = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N21
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout  = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N23
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout  = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F;
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N9
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N11
+dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0;
+defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N27
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888;
+defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N19
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q  & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q  & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N5
+dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # 
+// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q  & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2;
+defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N25
+dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q  & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout  & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q  & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC;
+defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y22_N13
+dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout  = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout  = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout  & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout  & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout  = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA;
+defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|init_end (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout  = (\data_rw_ctrl_inst|rd_en~q  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))
+
+	.dataa(\data_rw_ctrl_inst|rd_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N17
+dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19  
+// & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout  & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC;
+defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N9
+dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout  = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q  & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # 
+// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout  & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N29
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N7
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~0_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Add3~0_combout  = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0;
+defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N31
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [12])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N29
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [13])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [14])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [9])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [10])
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y25_N11
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [7])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N3
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout  = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout  & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout  & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N27
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [6])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N23
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q  & \sd_ctrl_inst|sd_read_inst|byte_head [4])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y25_N13
+dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]),
+	.datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y25_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout  = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout  & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N1
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N5
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N15
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23  & VCC))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25  = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N17
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27  = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N19
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y25_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~3_combout  = (\sd_ctrl_inst|sd_read_inst|always3~2_combout  & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|always3~4_combout  = (\sd_ctrl_inst|sd_read_inst|always3~1_combout  & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800;
+defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & (\sd_ctrl_inst|sd_read_inst|always3~4_combout  & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & 
+// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout  & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50;
+defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N23
+dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N21
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q  & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00;
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N31
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout  = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout  & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout 
+//  & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N3
+dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout  = \sd_ctrl_inst|sd_init_inst|miso_dly~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC)
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9  = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout  = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N13
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout  & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout  & (((\sd_ctrl_inst|sd_write_inst|ack_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8;
+defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q  & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N23
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N29
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N19
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N25
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N31
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N21
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout  = \sd_ctrl_inst|sd_write_inst|ack_data [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00;
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N27
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y24_N1
+dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout  = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]),
+	.datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]),
+	.datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout  = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) 
+// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout  & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30;
+defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N1
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~2_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Add3~1_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0;
+defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y13_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit 
+// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N5
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N9
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & 
+// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N25
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X10_Y16_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout  = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N27
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout  & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002;
+defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|always4~3_combout  = (\sd_ctrl_inst|sd_write_inst|always4~1_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N17
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout  = (\sd_miso~input_o  & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_miso~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N27
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N9
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N31
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N13
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N25
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N15
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N5
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y21_N19
+dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout  = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]),
+	.datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]),
+	.datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]),
+	.datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout  & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00;
+defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # 
+// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q  & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8;
+defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N5
+dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1])))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q  & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1])))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N29
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout  = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout  & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q )))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA;
+defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N3
+dffeas \sd_ctrl_inst|sd_write_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout  = (\sd_ctrl_inst|comb~2_combout  & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout  & 
+// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))))
+
+	.dataa(\sd_ctrl_inst|comb~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N9
+dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout  = \sd_ctrl_inst|sd_write_inst|state.IDLE~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N19
+dffeas \data_rw_ctrl_inst|wr_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|wr_busy_fall~0_combout  = (\data_rw_ctrl_inst|wr_busy_dly~q  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|wr_busy_dly~q ),
+	.datac(gnd),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC;
+defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N11
+dffeas \data_rw_ctrl_inst|rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout  = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout  & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q  & \data_rw_ctrl_inst|rd_en~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.datad(\data_rw_ctrl_inst|rd_en~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230;
+defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y23_N25
+dffeas \sd_ctrl_inst|sd_read_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y22_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout  = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q  & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q  & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ),
+	.datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y22_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout  = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]),
+	.datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout  = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]),
+	.datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800;
+defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout  = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) 
+// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout  = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout  & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF;
+defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y22_N15
+dffeas \sd_ctrl_inst|sd_init_inst|cs_n (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y22_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_cs_n~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q )))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_cs_n~0_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_cs_n~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F;
+defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y22_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout  = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & (((\sd_ctrl_inst|sd_init_inst|mosi~q  & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout  & 
+// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4;
+defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y22_N1
+dffeas \sd_ctrl_inst|sd_init_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N11
+dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~1_combout  = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout  & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y21_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|mosi~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q  & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # 
+// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout )))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]),
+	.datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700;
+defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y21_N1
+dffeas \sd_ctrl_inst|sd_read_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q  $ (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT  = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|Add1~0 (
+// Equation(s):
+// \uart_rx_inst|Add1~0_combout  = (\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q  & (\uart_rx_inst|bit_cnt [0] & VCC))
+// \uart_rx_inst|Add1~1  = CARRY((\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [0]))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Add1~0_combout ),
+	.cout(\uart_rx_inst|Add1~1 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Add1~2 (
+// Equation(s):
+// \uart_rx_inst|Add1~2_combout  = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND)))
+// \uart_rx_inst|Add1~3  = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|Add1~1 ),
+	.combout(\uart_rx_inst|Add1~2_combout ),
+	.cout(\uart_rx_inst|Add1~3 ));
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|Add1~6 (
+// Equation(s):
+// \uart_rx_inst|Add1~6_combout  = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|Add1~5 ),
+	.combout(\uart_rx_inst|Add1~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C;
+defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~0_combout  = (\uart_rx_inst|Add1~6_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|Add1~6_combout ),
+	.datac(\uart_rx_inst|bit_cnt [3]),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC;
+defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N5
+dffeas \uart_rx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 (
+// Equation(s):
+// \uart_rx_inst|bit_cnt~1_combout  = (\uart_rx_inst|Add1~0_combout  & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q )))
+
+	.dataa(\uart_rx_inst|bit_flag~q ),
+	.datab(\uart_rx_inst|bit_cnt [3]),
+	.datac(\uart_rx_inst|Add1~0_combout ),
+	.datad(\uart_rx_inst|always4~0_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|bit_cnt~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0;
+defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N25
+dffeas \uart_rx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|bit_cnt~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N11
+dffeas \uart_rx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|always4~0 (
+// Equation(s):
+// \uart_rx_inst|always4~0_combout  = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1]))
+
+	.dataa(\uart_rx_inst|bit_cnt [2]),
+	.datab(\uart_rx_inst|bit_cnt [0]),
+	.datac(gnd),
+	.datad(\uart_rx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011;
+defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[0]~13_combout  = (\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q  & (\uart_rx_inst|baud_cnt [0] & VCC))
+// \uart_rx_inst|baud_cnt[0]~14  = CARRY((\uart_rx_inst|work_en~q  & \uart_rx_inst|baud_cnt [0]))
+
+	.dataa(\uart_rx_inst|work_en~q ),
+	.datab(\uart_rx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_rx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|Equal1~0 (
+// Equation(s):
+// \uart_rx_inst|Equal1~0_combout  = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0])))
+
+	.dataa(\uart_rx_inst|baud_cnt [8]),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(\uart_rx_inst|baud_cnt [1]),
+	.datad(\uart_rx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000;
+defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N12
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[5]~23_combout  = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND)))
+// \uart_rx_inst|baud_cnt[5]~24  = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5]))
+
+	.dataa(\uart_rx_inst|baud_cnt [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[4]~22 ),
+	.combout(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.cout(\uart_rx_inst|baud_cnt[5]~24 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F;
+defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N13
+dffeas \uart_rx_inst|baud_cnt[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[5]~23_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N6
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[2]~17_combout  = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16  $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16  & VCC))
+// \uart_rx_inst|baud_cnt[2]~18  = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 ))
+
+	.dataa(\uart_rx_inst|baud_cnt [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[1]~16 ),
+	.combout(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.cout(\uart_rx_inst|baud_cnt[2]~18 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A;
+defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N7
+dffeas \uart_rx_inst|baud_cnt[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[2]~17_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y16_N10
+cycloneive_lcell_comb \uart_rx_inst|Equal1~1 (
+// Equation(s):
+// \uart_rx_inst|Equal1~1_combout  = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3])))
+
+	.dataa(\uart_rx_inst|baud_cnt [4]),
+	.datab(\uart_rx_inst|baud_cnt [5]),
+	.datac(\uart_rx_inst|baud_cnt [2]),
+	.datad(\uart_rx_inst|baud_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020;
+defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N2
+cycloneive_lcell_comb \uart_rx_inst|Equal1~3 (
+// Equation(s):
+// \uart_rx_inst|Equal1~3_combout  = (\uart_rx_inst|Equal1~2_combout  & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal1~2_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000;
+defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|work_en~0 (
+// Equation(s):
+// \uart_rx_inst|work_en~0_combout  = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q  & !\uart_rx_inst|always4~1_combout ))
+
+	.dataa(\uart_rx_inst|start_nedge~q ),
+	.datab(gnd),
+	.datac(\uart_rx_inst|work_en~q ),
+	.datad(\uart_rx_inst|always4~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|work_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA;
+defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N17
+dffeas \uart_rx_inst|work_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|work_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|work_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|work_en .is_wysiwyg = "true";
+defparam \uart_rx_inst|work_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|always5~0 (
+// Equation(s):
+// \uart_rx_inst|always5~0_combout  = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q )
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|Equal1~3_combout ),
+	.datac(gnd),
+	.datad(\uart_rx_inst|work_en~q ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF;
+defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N3
+dffeas \uart_rx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N4
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[1]~15_combout  = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_rx_inst|baud_cnt[1]~16  = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_rx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N5
+dffeas \uart_rx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N8
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[3]~19_combout  = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_rx_inst|baud_cnt[3]~20  = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_rx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N9
+dffeas \uart_rx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N14
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[6]~25_combout  = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24  & VCC))
+// \uart_rx_inst|baud_cnt[6]~26  = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_rx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N15
+dffeas \uart_rx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N16
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[7]~27_combout  = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_rx_inst|baud_cnt[7]~28  = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_rx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N17
+dffeas \uart_rx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N18
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[8]~29_combout  = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28  & VCC))
+// \uart_rx_inst|baud_cnt[8]~30  = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_rx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N19
+dffeas \uart_rx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N20
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[9]~31_combout  = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_rx_inst|baud_cnt[9]~32  = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_rx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N21
+dffeas \uart_rx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N24
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[11]~35_combout  = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_rx_inst|baud_cnt[11]~36  = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_rx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_rx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N25
+dffeas \uart_rx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N26
+cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_rx_inst|baud_cnt[12]~37_combout  = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_rx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_rx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X16_Y16_N27
+dffeas \uart_rx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_rx_inst|always5~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_rx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y16_N28
+cycloneive_lcell_comb \uart_rx_inst|Equal2~1 (
+// Equation(s):
+// \uart_rx_inst|Equal2~1_combout  = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9])))
+
+	.dataa(\uart_rx_inst|baud_cnt [10]),
+	.datab(\uart_rx_inst|baud_cnt [11]),
+	.datac(\uart_rx_inst|baud_cnt [6]),
+	.datad(\uart_rx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400;
+defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N22
+cycloneive_lcell_comb \uart_rx_inst|Equal2~2 (
+// Equation(s):
+// \uart_rx_inst|Equal2~2_combout  = (\uart_rx_inst|Equal2~0_combout  & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout  & \uart_rx_inst|Equal2~1_combout )))
+
+	.dataa(\uart_rx_inst|Equal2~0_combout ),
+	.datab(\uart_rx_inst|baud_cnt [12]),
+	.datac(\uart_rx_inst|Equal1~0_combout ),
+	.datad(\uart_rx_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\uart_rx_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000;
+defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N23
+dffeas \uart_rx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|Equal2~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y16_N0
+cycloneive_lcell_comb \uart_rx_inst|always4~1 (
+// Equation(s):
+// \uart_rx_inst|always4~1_combout  = (\uart_rx_inst|always4~0_combout  & (\uart_rx_inst|bit_flag~q  & \uart_rx_inst|bit_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_rx_inst|always4~0_combout ),
+	.datac(\uart_rx_inst|bit_flag~q ),
+	.datad(\uart_rx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_rx_inst|always4~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000;
+defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y16_N1
+dffeas \uart_rx_inst|rx_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_rx_inst|always4~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|rx_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|rx_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N1
+dffeas \uart_rx_inst|po_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\uart_rx_inst|rx_flag~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_rx_inst|po_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_rx_inst|po_flag .is_wysiwyg = "true";
+defparam \uart_rx_inst|po_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N25
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N7
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]),
+	.datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q  & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\uart_rx_inst|po_flag~q ),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\uart_rx_inst|po_flag~q  & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datac(\uart_rx_inst|po_flag~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q  $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N19
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y13_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y13_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N21
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q  & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X12_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y14_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y14_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y12_N23
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N5
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N9
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N27
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N31
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y13_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout  $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y13_N15
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y13_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & 
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y13_N13
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y13_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y13_N11
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y12_N29
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N1
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N17
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y12_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y12_N3
+dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & 
+// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & 
+// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9  & VCC)))) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout  = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND)
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13  = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ 
+// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15  $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]),
+	.cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ),
+	.combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A;
+defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N4
+cycloneive_lcell_comb \sd_ctrl_inst|comb~1 (
+// Equation(s):
+// \sd_ctrl_inst|comb~1_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout  & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001;
+defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N0
+cycloneive_lcell_comb \sd_ctrl_inst|comb~0 (
+// Equation(s):
+// \sd_ctrl_inst|comb~0_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout  & (\sd_ctrl_inst|sd_init_inst|init_end~q  & 
+// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout  & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ),
+	.datab(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004;
+defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y12_N2
+cycloneive_lcell_comb \sd_ctrl_inst|comb~2 (
+// Equation(s):
+// \sd_ctrl_inst|comb~2_combout  = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout  & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout  & 
+// (\sd_ctrl_inst|comb~1_combout  & \sd_ctrl_inst|comb~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ),
+	.datac(\sd_ctrl_inst|comb~1_combout ),
+	.datad(\sd_ctrl_inst|comb~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|comb~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000;
+defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N26
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout  = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & (((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout  & 
+// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout  & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|comb~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y23_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout  = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout  & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout 
+// ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA;
+defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y23_N15
+dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N14
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # 
+// (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N15
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) 
+// # (GND)))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N19
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8;
+defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15  & VCC))
+// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17  = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ),
+	.combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C;
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N21
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X12_Y16_N23
+dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~2_combout  = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout  & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout  = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]))
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000;
+defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X12_Y16_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~3_combout  = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & 
+// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]),
+	.datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]),
+	.datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~4_combout  = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~5_combout  = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q  & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y16_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_write_inst|mosi~8_combout  = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout  & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout  & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ),
+	.datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ),
+	.datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D;
+defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X11_Y16_N17
+dffeas \sd_ctrl_inst|sd_write_inst|mosi (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~0_combout  = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q  & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # 
+// (!\sd_ctrl_inst|sd_read_inst|mosi~q )))
+
+	.dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|mosi~q ),
+	.datac(\sd_ctrl_inst|sd_write_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F;
+defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_mosi~1_combout  = (\sd_ctrl_inst|sd_init_inst|init_end~q  & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q  & (!\sd_ctrl_inst|sd_init_inst|mosi~q ))
+
+	.dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_init_inst|mosi~q ),
+	.datad(\sd_ctrl_inst|sd_mosi~0_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_mosi~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05;
+defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G8
+cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
+// synopsys translate_off
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
+defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N2
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[0]~13_combout  = (\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q  & (\uart_tx_inst|baud_cnt [0] & VCC))
+// \uart_tx_inst|baud_cnt[0]~14  = CARRY((\uart_tx_inst|work_en~q  & \uart_tx_inst|baud_cnt [0]))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|baud_cnt [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.cout(\uart_tx_inst|baud_cnt[0]~14 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688;
+defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N0
+cycloneive_lcell_comb \uart_tx_inst|Equal1~0 (
+// Equation(s):
+// \uart_tx_inst|Equal1~0_combout  = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0])))
+
+	.dataa(\uart_tx_inst|baud_cnt [5]),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(\uart_tx_inst|baud_cnt [3]),
+	.datad(\uart_tx_inst|baud_cnt [0]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100;
+defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|Equal1~1 (
+// Equation(s):
+// \uart_tx_inst|Equal1~1_combout  = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout  & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9])))
+
+	.dataa(\uart_tx_inst|baud_cnt [8]),
+	.datab(\uart_tx_inst|Equal1~0_combout ),
+	.datac(\uart_tx_inst|baud_cnt [11]),
+	.datad(\uart_tx_inst|baud_cnt [9]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004;
+defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[4]~21_combout  = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20  $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20  & VCC))
+// \uart_tx_inst|baud_cnt[4]~22  = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 ))
+
+	.dataa(\uart_tx_inst|baud_cnt [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[3]~20 ),
+	.combout(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.cout(\uart_tx_inst|baud_cnt[4]~22 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A;
+defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N11
+dffeas \uart_tx_inst|baud_cnt[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[4]~21_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N30
+cycloneive_lcell_comb \uart_tx_inst|Equal1~2 (
+// Equation(s):
+// \uart_tx_inst|Equal1~2_combout  = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Equal1~3 (
+// Equation(s):
+// \uart_tx_inst|Equal1~3_combout  = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12])
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(gnd),
+	.datac(\uart_tx_inst|baud_cnt [12]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal1~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0;
+defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N26
+cycloneive_lcell_comb \uart_tx_inst|always1~0 (
+// Equation(s):
+// \uart_tx_inst|always1~0_combout  = ((\uart_tx_inst|Equal1~1_combout  & (\uart_tx_inst|Equal1~2_combout  & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|Equal1~1_combout ),
+	.datac(\uart_tx_inst|Equal1~2_combout ),
+	.datad(\uart_tx_inst|Equal1~3_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555;
+defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N3
+dffeas \uart_tx_inst|baud_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[0]~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[1]~15_combout  = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND)))
+// \uart_tx_inst|baud_cnt[1]~16  = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[0]~14 ),
+	.combout(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.cout(\uart_tx_inst|baud_cnt[1]~16 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N5
+dffeas \uart_tx_inst|baud_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[1]~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[3]~19_combout  = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND)))
+// \uart_tx_inst|baud_cnt[3]~20  = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[2]~18 ),
+	.combout(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.cout(\uart_tx_inst|baud_cnt[3]~20 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N9
+dffeas \uart_tx_inst|baud_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[3]~19_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[6]~25_combout  = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24  $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24  & VCC))
+// \uart_tx_inst|baud_cnt[6]~26  = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[5]~24 ),
+	.combout(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.cout(\uart_tx_inst|baud_cnt[6]~26 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N15
+dffeas \uart_tx_inst|baud_cnt[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[6]~25_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[7]~27_combout  = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND)))
+// \uart_tx_inst|baud_cnt[7]~28  = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[6]~26 ),
+	.combout(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.cout(\uart_tx_inst|baud_cnt[7]~28 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N17
+dffeas \uart_tx_inst|baud_cnt[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[7]~27_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[8]~29_combout  = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28  $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28  & VCC))
+// \uart_tx_inst|baud_cnt[8]~30  = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 ))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[7]~28 ),
+	.combout(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.cout(\uart_tx_inst|baud_cnt[8]~30 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C;
+defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N19
+dffeas \uart_tx_inst|baud_cnt[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[8]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[9]~31_combout  = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND)))
+// \uart_tx_inst|baud_cnt[9]~32  = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[8]~30 ),
+	.combout(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.cout(\uart_tx_inst|baud_cnt[9]~32 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N21
+dffeas \uart_tx_inst|baud_cnt[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[9]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[11]~35_combout  = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND)))
+// \uart_tx_inst|baud_cnt[11]~36  = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11]))
+
+	.dataa(gnd),
+	.datab(\uart_tx_inst|baud_cnt [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\uart_tx_inst|baud_cnt[10]~34 ),
+	.combout(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.cout(\uart_tx_inst|baud_cnt[11]~36 ));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F;
+defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N25
+dffeas \uart_tx_inst|baud_cnt[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[11]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N26
+cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 (
+// Equation(s):
+// \uart_tx_inst|baud_cnt[12]~37_combout  = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 )
+
+	.dataa(\uart_tx_inst|baud_cnt [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\uart_tx_inst|baud_cnt[11]~36 ),
+	.combout(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5;
+defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X15_Y26_N27
+dffeas \uart_tx_inst|baud_cnt[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|baud_cnt[12]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\uart_tx_inst|always1~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|baud_cnt [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true";
+defparam \uart_tx_inst|baud_cnt[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N28
+cycloneive_lcell_comb \uart_tx_inst|Equal2~0 (
+// Equation(s):
+// \uart_tx_inst|Equal2~0_combout  = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4])))
+
+	.dataa(\uart_tx_inst|baud_cnt [2]),
+	.datab(\uart_tx_inst|baud_cnt [6]),
+	.datac(\uart_tx_inst|baud_cnt [1]),
+	.datad(\uart_tx_inst|baud_cnt [4]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001;
+defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N24
+cycloneive_lcell_comb \uart_tx_inst|Equal2~1 (
+// Equation(s):
+// \uart_tx_inst|Equal2~1_combout  = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout  & \uart_tx_inst|Equal1~1_combout )))
+
+	.dataa(\uart_tx_inst|baud_cnt [10]),
+	.datab(\uart_tx_inst|baud_cnt [12]),
+	.datac(\uart_tx_inst|Equal2~0_combout ),
+	.datad(\uart_tx_inst|Equal1~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N25
+dffeas \uart_tx_inst|bit_flag (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|Equal2~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_flag~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_flag .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N18
+cycloneive_lcell_comb \uart_tx_inst|always3~0 (
+// Equation(s):
+// \uart_tx_inst|always3~0_combout  = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q )
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\uart_tx_inst|bit_flag~q ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF;
+defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneive_lcell_comb \uart_tx_inst|always0~1 (
+// Equation(s):
+// \uart_tx_inst|always0~1_combout  = (\uart_tx_inst|always0~0_combout  & (\uart_tx_inst|bit_flag~q  & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3])))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [3]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|always0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000;
+defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[0]~5_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q  & \uart_tx_inst|bit_flag~q )))))
+
+	.dataa(\uart_tx_inst|work_en~q ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|always0~1_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078;
+defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N5
+dffeas \uart_tx_inst|bit_cnt[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[1]~4_combout  = (!\uart_tx_inst|always0~1_combout  & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|bit_cnt [0]),
+	.datac(\uart_tx_inst|bit_cnt [1]),
+	.datad(\uart_tx_inst|always3~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014;
+defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N1
+dffeas \uart_tx_inst|bit_cnt[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[1]~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneive_lcell_comb \uart_tx_inst|Add1~0 (
+// Equation(s):
+// \uart_tx_inst|Add1~0_combout  = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))))
+
+	.dataa(\uart_tx_inst|bit_cnt [2]),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\uart_tx_inst|bit_cnt [1]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Add1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC;
+defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 (
+// Equation(s):
+// \uart_tx_inst|bit_cnt[3]~2_combout  = (!\uart_tx_inst|always0~1_combout  & ((\uart_tx_inst|always3~0_combout  & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout  & ((\uart_tx_inst|Add1~0_combout )))))
+
+	.dataa(\uart_tx_inst|always0~1_combout ),
+	.datab(\uart_tx_inst|always3~0_combout ),
+	.datac(\uart_tx_inst|bit_cnt [3]),
+	.datad(\uart_tx_inst|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140;
+defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N3
+dffeas \uart_tx_inst|bit_cnt[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|bit_cnt[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|bit_cnt [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true";
+defparam \uart_tx_inst|bit_cnt[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[0]~16_combout  = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC)
+// \data_rw_ctrl_inst|cnt_wait[0]~17  = CARRY(\data_rw_ctrl_inst|cnt_wait [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[0]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[3]~22_combout  = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[3]~23  = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[3]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[4]~24_combout  = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[4]~25  = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[4]~25 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N9
+dffeas \data_rw_ctrl_inst|cnt_wait[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~0_combout  = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5])
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5;
+defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N15
+dffeas \data_rw_ctrl_inst|rd_busy_dly (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[0]~12_combout  = \data_rw_ctrl_inst|send_data_num [0] $ (VCC)
+// \data_rw_ctrl_inst|send_data_num[0]~13  = CARRY(\data_rw_ctrl_inst|send_data_num [0])
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[0]~13 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC;
+defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N1
+dffeas \data_rw_ctrl_inst|send_data_num[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[1]~14_combout  = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[1]~15  = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[0]~13 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[1]~15 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N3
+dffeas \data_rw_ctrl_inst|send_data_num[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[2]~16_combout  = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15  & VCC))
+// \data_rw_ctrl_inst|send_data_num[2]~17  = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[1]~15 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[2]~17 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N5
+dffeas \data_rw_ctrl_inst|send_data_num[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~0_combout  = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [3]),
+	.datab(\data_rw_ctrl_inst|send_data_num [1]),
+	.datac(\data_rw_ctrl_inst|send_data_num [2]),
+	.datad(\data_rw_ctrl_inst|send_data_num [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[4]~20_combout  = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19  $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19  & VCC))
+// \data_rw_ctrl_inst|send_data_num[4]~21  = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|send_data_num [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[3]~19 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[4]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N9
+dffeas \data_rw_ctrl_inst|send_data_num[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_num[5]~22_combout  = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND)))
+// \data_rw_ctrl_inst|send_data_num[5]~23  = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5]))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|send_data_num[4]~21 ),
+	.combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.cout(\data_rw_ctrl_inst|send_data_num[5]~23 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N15
+dffeas \data_rw_ctrl_inst|send_data_num[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y26_N11
+dffeas \data_rw_ctrl_inst|send_data_num[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(!\data_rw_ctrl_inst|send_data_en~q ),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_num [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~1_combout  = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5])))
+
+	.dataa(\data_rw_ctrl_inst|send_data_num [6]),
+	.datab(\data_rw_ctrl_inst|send_data_num [7]),
+	.datac(\data_rw_ctrl_inst|send_data_num [4]),
+	.datad(\data_rw_ctrl_inst|send_data_num [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|always3~3_combout  = (\data_rw_ctrl_inst|always3~2_combout  & (\data_rw_ctrl_inst|always3~0_combout  & (\data_rw_ctrl_inst|always3~1_combout  & \data_rw_ctrl_inst|Equal2~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|always3~2_combout ),
+	.datab(\data_rw_ctrl_inst|always3~0_combout ),
+	.datac(\data_rw_ctrl_inst|always3~1_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|always3~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|send_data_en~0_combout  = (!\data_rw_ctrl_inst|always3~3_combout  & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q  & \data_rw_ctrl_inst|rd_busy_dly~q ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ),
+	.datab(\data_rw_ctrl_inst|rd_busy_dly~q ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|always3~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4;
+defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N23
+dffeas \data_rw_ctrl_inst|send_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|send_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|send_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|send_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal3~1_combout  = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~26_combout  = ((\data_rw_ctrl_inst|Equal2~2_combout  & (!\data_rw_ctrl_inst|Equal3~0_combout  & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q )
+
+	.dataa(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.datab(\data_rw_ctrl_inst|Equal3~0_combout ),
+	.datac(\data_rw_ctrl_inst|send_data_en~q ),
+	.datad(\data_rw_ctrl_inst|Equal3~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N1
+dffeas \data_rw_ctrl_inst|cnt_wait[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[1]~18_combout  = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[1]~19  = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[1]~19 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N3
+dffeas \data_rw_ctrl_inst|cnt_wait[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[2]~20_combout  = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[2]~21  = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[2]~21 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N5
+dffeas \data_rw_ctrl_inst|cnt_wait[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N7
+dffeas \data_rw_ctrl_inst|cnt_wait[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~3_combout  = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [0]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [3]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [2]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[6]~29_combout  = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[6]~30  = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 ))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[6]~30 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A;
+defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[7]~31_combout  = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[7]~32  = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[7]~32 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N15
+dffeas \data_rw_ctrl_inst|cnt_wait[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[8]~33_combout  = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[8]~34  = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[8]~34 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N17
+dffeas \data_rw_ctrl_inst|cnt_wait[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[9]~35_combout  = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[9]~36  = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[9]~36 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F;
+defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N19
+dffeas \data_rw_ctrl_inst|cnt_wait[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[10]~37_combout  = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[10]~38  = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[10]~38 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N21
+dffeas \data_rw_ctrl_inst|cnt_wait[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[11]~39_combout  = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[11]~40  = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[11]~40 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[12]~41_combout  = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[12]~42  = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[12]~42 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N25
+dffeas \data_rw_ctrl_inst|cnt_wait[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[13]~43_combout  = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND)))
+// \data_rw_ctrl_inst|cnt_wait[13]~44  = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13]))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[13]~44 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F;
+defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[14]~45_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44  $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44  & VCC))
+// \data_rw_ctrl_inst|cnt_wait[14]~46  = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.cout(\data_rw_ctrl_inst|cnt_wait[14]~46 ));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C;
+defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N29
+dffeas \data_rw_ctrl_inst|cnt_wait[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 (
+// Equation(s):
+// \data_rw_ctrl_inst|cnt_wait[15]~47_combout  = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 )
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ),
+	.combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N31
+dffeas \data_rw_ctrl_inst|cnt_wait[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N13
+dffeas \data_rw_ctrl_inst|cnt_wait[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~0_combout  = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [7]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [9]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [8]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400;
+defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N27
+dffeas \data_rw_ctrl_inst|cnt_wait[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y27_N23
+dffeas \data_rw_ctrl_inst|cnt_wait[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|cnt_wait [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~1_combout  = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11])))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [10]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [12]),
+	.datac(\data_rw_ctrl_inst|cnt_wait [13]),
+	.datad(\data_rw_ctrl_inst|cnt_wait [11]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~2_combout  = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout  & \data_rw_ctrl_inst|Equal2~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [14]),
+	.datab(\data_rw_ctrl_inst|cnt_wait [15]),
+	.datac(\data_rw_ctrl_inst|Equal2~0_combout ),
+	.datad(\data_rw_ctrl_inst|Equal2~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000;
+defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|Equal2~4_combout  = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout  & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|cnt_wait [5]),
+	.datab(\data_rw_ctrl_inst|Equal2~3_combout ),
+	.datac(\data_rw_ctrl_inst|cnt_wait [4]),
+	.datad(\data_rw_ctrl_inst|Equal2~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000;
+defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y27_N7
+dffeas \data_rw_ctrl_inst|rd_fifo_rd_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|Equal2~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q )
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y25_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout  = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]),
+	.datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55;
+defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X15_Y25_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q )
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N10
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y27_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y27_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q  & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout  & 
+// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q  & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q  $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X27_Y27_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X27_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N5
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N1
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N7
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X30_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout  = 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout  & (\data_rw_ctrl_inst|rd_fifo_rd_en~q  
+// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N6
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q  & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y27_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout  & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N31
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N0
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout  = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N16
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N20
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ 
+// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N21
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9])
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N15
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N28
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2])))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N29
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q  $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q  $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y28_N26
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ 
+// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout  & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & 
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y28_N27
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N24
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q 
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N25
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N22
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N23
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N11
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N9
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N17
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N2
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X28_Y28_N3
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout  = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # 
+// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]))))
+
+	.dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]),
+	.datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X28_Y28_N30
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout  = (\data_rw_ctrl_inst|rd_fifo_rd_en~q  & 
+// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))
+
+	.dataa(gnd),
+	.datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout  = (\sd_miso~input_o  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_miso~input_o ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N30
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y25_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout  = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]),
+	.datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N31
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N12
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N13
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y24_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y24_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N22
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N23
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X29_Y27_N18
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout  = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X29_Y27_N19
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X27_Y27_N8
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ 
+// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N12
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X26_Y28_N13
+dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true";
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X26_Y28_N14
+cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell (
+// Equation(s):
+// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout  = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ),
+	.cin(gnd),
+	.combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ),
+	.cout());
+// synopsys translate_off
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF;
+defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N16
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(gnd),
+	.datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N17
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N0
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N1
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout  = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8])))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N28
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N29
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N8
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N9
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X17_Y27_N4
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X17_Y27_N5
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N6
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N7
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N20
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N21
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N10
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N11
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N2
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N3
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N18
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout  = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout  & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout )))
+
+	.dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]),
+	.datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N19
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X16_Y27_N24
+cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 (
+// Equation(s):
+// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout  = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q  & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ),
+	.datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]),
+	.cin(gnd),
+	.combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000;
+defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X16_Y27_N25
+dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sd_ctrl_inst|sd_read_inst|rd_data [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true";
+defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N20
+cycloneive_lcell_comb \uart_tx_inst|Mux0~0 (
+// Equation(s):
+// \uart_tx_inst|Mux0~0_combout  = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout )))
+
+	.dataa(\uart_tx_inst|always0~0_combout ),
+	.datab(\uart_tx_inst|bit_cnt [3]),
+	.datac(\uart_tx_inst|bit_cnt [0]),
+	.datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]),
+	.cin(gnd),
+	.combout(\uart_tx_inst|Mux0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4;
+defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N8
+cycloneive_lcell_comb \uart_tx_inst|tx~0 (
+// Equation(s):
+// \uart_tx_inst|tx~0_combout  = (\uart_tx_inst|bit_flag~q  & (!\uart_tx_inst|Mux0~5_combout  & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q  & (((\uart_tx_inst|tx~q ))))
+
+	.dataa(\uart_tx_inst|Mux0~5_combout ),
+	.datab(\uart_tx_inst|bit_flag~q ),
+	.datac(\uart_tx_inst|tx~q ),
+	.datad(\uart_tx_inst|Mux0~0_combout ),
+	.cin(gnd),
+	.combout(\uart_tx_inst|tx~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074;
+defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y27_N9
+dffeas \uart_tx_inst|tx (
+	.clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
+	.d(\uart_tx_inst|tx~0_combout ),
+	.asdata(vcc),
+	.clrn(!\rst_n~0clkctrl_outclk ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\uart_tx_inst|tx~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \uart_tx_inst|tx .is_wysiwyg = "true";
+defparam \uart_tx_inst|tx .power_up = "low";
+// synopsys translate_on
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo
new file mode 100644
index 0000000..d3b225b
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo
@@ -0,0 +1,19061 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CE15F23C8,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "uart_sd")
+  (DATE "06/02/2023 04:03:15")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_pll")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1)
+    (DELAY
+      (ABSOLUTE
+        (PORT areset (2025:2025:2025) (2025:2025:2025))
+        (PORT inclk[0] (1104:1104:1104) (1104:1104:1104))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (357:357:357) (433:433:433))
+        (PORT datab (303:303:303) (363:363:363))
+        (IOPATH dataa combout (166:166:166) (159:159:159))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (367:367:367))
+        (PORT datab (465:465:465) (550:550:550))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (257:257:257))
+        (PORT datab (131:131:131) (179:179:179))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (870:870:870))
+        (PORT sclr (1357:1357:1357) (1249:1249:1249))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (571:571:571) (678:678:678))
+        (PORT d[1] (558:558:558) (658:658:658))
+        (PORT d[2] (586:586:586) (698:698:698))
+        (PORT d[3] (670:670:670) (793:793:793))
+        (PORT d[4] (568:568:568) (674:674:674))
+        (PORT d[5] (674:674:674) (798:798:798))
+        (PORT d[6] (575:575:575) (684:684:684))
+        (PORT d[7] (574:574:574) (682:682:682))
+        (PORT clk (1063:1063:1063) (1083:1083:1083))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (412:412:412) (491:491:491))
+        (PORT d[1] (435:435:435) (517:517:517))
+        (PORT d[2] (515:515:515) (602:602:602))
+        (PORT d[3] (445:445:445) (522:522:522))
+        (PORT d[4] (414:414:414) (494:494:494))
+        (PORT d[5] (727:727:727) (853:853:853))
+        (PORT d[6] (559:559:559) (667:667:667))
+        (PORT d[7] (721:721:721) (835:835:835))
+        (PORT d[8] (420:420:420) (506:506:506))
+        (PORT d[9] (381:381:381) (439:439:439))
+        (PORT clk (1061:1061:1061) (1081:1081:1081))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (527:527:527) (542:542:542))
+        (PORT clk (1061:1061:1061) (1081:1081:1081))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1083:1083:1083))
+        (PORT d[0] (811:811:811) (835:835:835))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1064:1064:1064) (1084:1084:1084))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1064:1064:1064) (1084:1084:1084))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1064:1064:1064) (1084:1084:1084))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1064:1064:1064) (1084:1084:1084))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (543:543:543) (629:629:629))
+        (PORT d[1] (413:413:413) (490:490:490))
+        (PORT d[2] (743:743:743) (863:863:863))
+        (PORT d[3] (752:752:752) (870:870:870))
+        (PORT d[4] (692:692:692) (822:822:822))
+        (PORT d[5] (787:787:787) (921:921:921))
+        (PORT d[6] (566:566:566) (657:657:657))
+        (PORT d[7] (607:607:607) (712:712:712))
+        (PORT d[8] (381:381:381) (447:447:447))
+        (PORT clk (1020:1020:1020) (1042:1042:1042))
+        (PORT stall (788:788:788) (738:738:738))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+      (HOLD stall (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1042:1042:1042))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1021:1021:1021) (1043:1043:1043))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1021:1021:1021) (1043:1043:1043))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1021:1021:1021) (1043:1043:1043))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1019:1019:1019) (1041:1041:1041))
+        (PORT ena (862:862:862) (920:920:920))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (SETUP ena (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+      (HOLD ena (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (477:477:477) (549:549:549))
+        (PORT d[1] (467:467:467) (537:537:537))
+        (PORT d[2] (477:477:477) (547:547:547))
+        (PORT d[3] (639:639:639) (731:731:731))
+        (PORT d[4] (475:475:475) (551:551:551))
+        (PORT d[5] (465:465:465) (539:539:539))
+        (PORT d[6] (479:479:479) (552:552:552))
+        (PORT d[7] (475:475:475) (548:548:548))
+        (PORT d[9] (468:468:468) (541:541:541))
+        (PORT d[10] (517:517:517) (596:596:596))
+        (PORT d[11] (517:517:517) (586:586:586))
+        (PORT d[12] (478:478:478) (554:554:554))
+        (PORT d[13] (613:613:613) (703:703:703))
+        (PORT d[14] (468:468:468) (538:538:538))
+        (PORT d[15] (637:637:637) (721:721:721))
+        (PORT d[16] (632:632:632) (726:726:726))
+        (PORT clk (1070:1070:1070) (1088:1088:1088))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (548:548:548) (647:647:647))
+        (PORT d[1] (510:510:510) (598:598:598))
+        (PORT d[2] (659:659:659) (768:768:768))
+        (PORT d[3] (477:477:477) (562:562:562))
+        (PORT d[4] (402:402:402) (480:480:480))
+        (PORT d[5] (705:705:705) (817:817:817))
+        (PORT d[6] (681:681:681) (794:794:794))
+        (PORT d[7] (386:386:386) (465:465:465))
+        (PORT d[8] (626:626:626) (712:712:712))
+        (PORT clk (1068:1068:1068) (1086:1086:1086))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (534:534:534) (553:553:553))
+        (PORT clk (1068:1068:1068) (1086:1086:1086))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1070:1070:1070) (1088:1088:1088))
+        (PORT d[0] (818:818:818) (846:846:846))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1071:1071:1071) (1089:1089:1089))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1071:1071:1071) (1089:1089:1089))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1071:1071:1071) (1089:1089:1089))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1071:1071:1071) (1089:1089:1089))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (522:522:522) (600:600:600))
+        (PORT d[1] (753:753:753) (874:874:874))
+        (PORT d[2] (611:611:611) (724:724:724))
+        (PORT d[3] (414:414:414) (493:493:493))
+        (PORT d[4] (428:428:428) (509:509:509))
+        (PORT d[5] (655:655:655) (779:779:779))
+        (PORT d[6] (402:402:402) (480:480:480))
+        (PORT d[7] (548:548:548) (643:643:643))
+        (PORT d[8] (527:527:527) (615:615:615))
+        (PORT d[9] (672:672:672) (760:760:760))
+        (PORT clk (1027:1027:1027) (1047:1047:1047))
+        (PORT stall (607:607:607) (589:589:589))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+      (HOLD stall (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1027:1027:1027) (1047:1047:1047))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1028:1028:1028) (1048:1048:1048))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1028:1028:1028) (1048:1048:1048))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1028:1028:1028) (1048:1048:1048))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1026:1026:1026) (1046:1046:1046))
+        (PORT ena (714:714:714) (740:740:740))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (SETUP ena (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+      (HOLD ena (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (278:278:278))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (211:211:211))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (203:203:203))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (146:146:146) (201:201:201))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (189:189:189))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (189:189:189))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (188:188:188))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (146:146:146) (204:204:204))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (189:189:189))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (196:196:196))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (196:196:196))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (189:189:189))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (136:136:136) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (188:188:188))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (306:306:306) (369:369:369))
+        (PORT datad (126:126:126) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (285:285:285))
+        (PORT datac (214:214:214) (267:267:267))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (PORT datab (211:211:211) (267:267:267))
+        (PORT datac (120:120:120) (163:163:163))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (273:273:273))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (89:89:89) (107:107:107))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (199:199:199) (248:248:248))
+        (PORT datad (170:170:170) (201:201:201))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (242:242:242) (300:300:300))
+        (PORT datac (825:825:825) (951:951:951))
+        (PORT datad (429:429:429) (490:490:490))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (204:204:204))
+        (PORT datab (146:146:146) (200:200:200))
+        (PORT datac (130:130:130) (177:177:177))
+        (PORT datad (131:131:131) (174:174:174))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (282:282:282))
+        (PORT datab (166:166:166) (227:227:227))
+        (PORT datac (389:389:389) (446:446:446))
+        (PORT datad (207:207:207) (243:243:243))
+        (IOPATH dataa combout (170:170:170) (165:165:165))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (398:398:398) (473:473:473))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (207:207:207) (247:247:247))
+        (PORT datad (154:154:154) (206:206:206))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (291:291:291))
+        (PORT datab (157:157:157) (211:211:211))
+        (PORT datac (229:229:229) (272:272:272))
+        (PORT datad (154:154:154) (207:207:207))
+        (IOPATH dataa combout (166:166:166) (159:159:159))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (107:107:107) (140:140:140))
+        (PORT datab (158:158:158) (212:212:212))
+        (PORT datac (684:684:684) (777:777:777))
+        (PORT datad (396:396:396) (457:457:457))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (282:282:282))
+        (PORT datab (161:161:161) (222:222:222))
+        (PORT datac (379:379:379) (436:436:436))
+        (PORT datad (211:211:211) (247:247:247))
+        (IOPATH dataa combout (188:188:188) (184:184:184))
+        (IOPATH datab combout (190:190:190) (188:188:188))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (475:475:475))
+        (PORT datab (156:156:156) (210:210:210))
+        (PORT datac (161:161:161) (189:189:189))
+        (PORT datad (391:391:391) (456:456:456))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (136:136:136))
+        (PORT datab (147:147:147) (200:200:200))
+        (PORT datac (142:142:142) (190:190:190))
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (402:402:402) (477:477:477))
+        (PORT datab (156:156:156) (210:210:210))
+        (PORT datac (224:224:224) (267:267:267))
+        (PORT datad (153:153:153) (205:205:205))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (188:188:188))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (400:400:400) (468:468:468))
+        (PORT datab (168:168:168) (230:230:230))
+        (PORT datac (224:224:224) (267:267:267))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (137:137:137))
+        (PORT datab (151:151:151) (206:206:206))
+        (PORT datac (92:92:92) (114:114:114))
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (111:111:111) (145:145:145))
+        (PORT datab (241:241:241) (299:299:299))
+        (PORT datac (214:214:214) (266:266:266))
+        (PORT datad (344:344:344) (401:401:401))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (417:417:417) (501:501:501))
+        (PORT datab (448:448:448) (542:542:542))
+        (PORT datac (407:407:407) (489:489:489))
+        (PORT datad (413:413:413) (497:497:497))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (493:493:493))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (406:406:406) (488:488:488))
+        (PORT datad (392:392:392) (478:478:478))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (509:509:509))
+        (PORT datab (422:422:422) (508:508:508))
+        (PORT datac (423:423:423) (516:516:516))
+        (PORT datad (411:411:411) (495:495:495))
+        (IOPATH dataa combout (188:188:188) (184:184:184))
+        (IOPATH datab combout (190:190:190) (188:188:188))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (396:396:396) (472:472:472))
+        (PORT datad (370:370:370) (435:435:435))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (417:417:417) (501:501:501))
+        (PORT datab (444:444:444) (538:538:538))
+        (PORT datac (396:396:396) (484:484:484))
+        (PORT datad (411:411:411) (495:495:495))
+        (IOPATH dataa combout (172:172:172) (165:165:165))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (415:415:415) (509:509:509))
+        (PORT datab (421:421:421) (508:508:508))
+        (PORT datac (395:395:395) (471:471:471))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (170:170:170) (165:165:165))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (417:417:417) (501:501:501))
+        (PORT datab (424:424:424) (510:510:510))
+        (PORT datac (394:394:394) (481:481:481))
+        (PORT datad (413:413:413) (496:496:496))
+        (IOPATH dataa combout (170:170:170) (165:165:165))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (492:492:492))
+        (PORT datab (447:447:447) (542:542:542))
+        (PORT datac (407:407:407) (489:489:489))
+        (PORT datad (90:90:90) (108:108:108))
+        (IOPATH dataa combout (159:159:159) (165:165:165))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (417:417:417) (501:501:501))
+        (PORT datab (451:451:451) (546:546:546))
+        (PORT datac (408:408:408) (491:491:491))
+        (PORT datad (414:414:414) (498:498:498))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (491:491:491))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (393:393:393) (480:480:480))
+        (PORT datad (369:369:369) (434:434:434))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (106:106:106) (138:138:138))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (372:372:372) (437:437:437))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (420:420:420) (506:506:506))
+        (PORT datab (104:104:104) (134:134:134))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (885:885:885) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (869:869:869) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (137:137:137) (182:182:182))
+        (PORT datad (141:141:141) (191:191:191))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (376:376:376) (439:439:439))
+        (PORT datab (164:164:164) (223:223:223))
+        (PORT datac (154:154:154) (212:212:212))
+        (PORT datad (346:346:346) (401:401:401))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (163:163:163) (222:222:222))
+        (PORT datac (345:345:345) (395:395:395))
+        (PORT datad (352:352:352) (406:406:406))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (410:410:410))
+        (PORT datab (170:170:170) (233:233:233))
+        (PORT datac (330:330:330) (376:376:376))
+        (PORT datad (148:148:148) (198:198:198))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (171:171:171) (235:235:235))
+        (PORT datac (333:333:333) (380:380:380))
+        (PORT datad (149:149:149) (199:199:199))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (138:138:138) (184:184:184))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (188:188:188))
+        (PORT datab (140:140:140) (191:191:191))
+        (PORT datad (200:200:200) (249:249:249))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (145:145:145) (198:198:198))
+        (PORT datac (130:130:130) (177:177:177))
+        (PORT datad (102:102:102) (119:119:119))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (225:225:225) (279:279:279))
+        (PORT datac (209:209:209) (259:259:259))
+        (PORT datad (197:197:197) (240:240:240))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (654:654:654) (742:742:742))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (412:412:412))
+        (PORT datab (474:474:474) (569:569:569))
+        (PORT datac (140:140:140) (187:187:187))
+        (PORT datad (99:99:99) (121:121:121))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (139:139:139) (191:191:191))
+        (PORT datac (146:146:146) (190:190:190))
+        (PORT datad (108:108:108) (127:127:127))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (228:228:228) (287:287:287))
+        (PORT datad (100:100:100) (121:121:121))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (330:330:330) (389:389:389))
+        (PORT datac (308:308:308) (362:362:362))
+        (PORT datad (289:289:289) (331:331:331))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (308:308:308) (363:363:363))
+        (PORT datad (288:288:288) (331:331:331))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (497:497:497) (596:596:596))
+        (PORT datad (472:472:472) (548:548:548))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datac (127:127:127) (174:174:174))
+        (PORT datad (130:130:130) (173:173:173))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (154:154:154) (209:209:209))
+        (PORT datab (144:144:144) (197:197:197))
+        (PORT datac (138:138:138) (184:184:184))
+        (PORT datad (129:129:129) (170:170:170))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (195:195:195))
+        (PORT datab (114:114:114) (147:147:147))
+        (PORT datac (321:321:321) (385:385:385))
+        (PORT datad (100:100:100) (122:122:122))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (358:358:358) (440:440:440))
+        (PORT datab (221:221:221) (267:267:267))
+        (PORT datac (429:429:429) (484:484:484))
+        (PORT datad (139:139:139) (180:180:180))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (PORT datab (136:136:136) (187:187:187))
+        (PORT datad (120:120:120) (159:159:159))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (384:384:384) (449:449:449))
+        (PORT datac (287:287:287) (330:330:330))
+        (PORT datad (142:142:142) (184:184:184))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (141:141:141) (196:196:196))
+        (PORT datab (113:113:113) (147:147:147))
+        (PORT datac (320:320:320) (385:385:385))
+        (PORT datad (99:99:99) (121:121:121))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (458:458:458) (542:542:542))
+        (PORT datab (149:149:149) (204:204:204))
+        (PORT datac (130:130:130) (178:178:178))
+        (PORT datad (179:179:179) (213:213:213))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (106:106:106) (138:138:138))
+        (PORT datab (105:105:105) (135:135:135))
+        (PORT datac (175:175:175) (211:211:211))
+        (PORT datad (307:307:307) (361:361:361))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (155:155:155) (214:214:214))
+        (PORT datab (108:108:108) (138:138:138))
+        (PORT datac (185:185:185) (216:216:216))
+        (PORT datad (380:380:380) (464:464:464))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (PORT datab (134:134:134) (183:183:183))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (149:149:149) (207:207:207))
+        (PORT datab (137:137:137) (187:187:187))
+        (PORT datac (123:123:123) (167:167:167))
+        (PORT datad (132:132:132) (176:176:176))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (204:204:204))
+        (PORT datab (102:102:102) (131:131:131))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (191:191:191) (229:229:229))
+        (PORT datac (179:179:179) (208:208:208))
+        (PORT datad (134:134:134) (172:172:172))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (269:269:269))
+        (PORT datab (166:166:166) (228:228:228))
+        (PORT datad (134:134:134) (179:179:179))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (520:520:520) (585:585:585))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (436:436:436))
+        (PORT datab (334:334:334) (407:407:407))
+        (PORT datad (347:347:347) (420:420:420))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (167:167:167) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (294:294:294) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (430:430:430))
+        (PORT datab (356:356:356) (429:429:429))
+        (PORT datad (117:117:117) (153:153:153))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (294:294:294) (333:333:333))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (450:450:450))
+        (PORT datab (342:342:342) (413:413:413))
+        (PORT datad (341:341:341) (411:411:411))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (365:365:365) (410:410:410))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (517:517:517))
+        (PORT datab (338:338:338) (409:409:409))
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (177:177:177) (215:215:215))
+        (PORT datab (105:105:105) (134:134:134))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (173:173:173) (204:204:204))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (446:446:446))
+        (PORT datab (516:516:516) (606:606:606))
+        (PORT datad (126:126:126) (168:168:168))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (606:606:606) (703:703:703))
+        (PORT datab (350:350:350) (418:418:418))
+        (PORT datad (211:211:211) (255:255:255))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (131:131:131) (168:168:168))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT asdata (299:299:299) (341:341:341))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT asdata (302:302:302) (345:345:345))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (664:664:664) (740:740:740))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (497:497:497) (557:557:557))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (417:417:417))
+        (PORT datab (226:226:226) (288:288:288))
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (521:521:521) (555:555:555))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (295:295:295) (334:334:334))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (226:226:226) (279:279:279))
+        (PORT datab (308:308:308) (375:375:375))
+        (PORT datad (118:118:118) (156:156:156))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (163:163:163) (225:225:225))
+        (PORT datac (138:138:138) (183:183:183))
+        (PORT datad (139:139:139) (189:189:189))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (137:137:137))
+        (PORT datab (113:113:113) (146:146:146))
+        (PORT datad (117:117:117) (142:142:142))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (447:447:447))
+        (PORT datab (134:134:134) (184:184:184))
+        (PORT datac (125:125:125) (170:170:170))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (542:542:542) (666:666:666))
+        (PORT datad (116:116:116) (137:137:137))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (294:294:294) (334:334:334))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (191:191:191) (228:228:228))
+        (PORT datac (179:179:179) (208:208:208))
+        (PORT datad (133:133:133) (171:171:171))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (806:806:806) (924:924:924))
+        (PORT datac (133:133:133) (175:175:175))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (703:703:703) (791:791:791))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (737:737:737) (840:840:840))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (310:310:310) (351:351:351))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT asdata (301:301:301) (343:343:343))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT ena (434:434:434) (461:461:461))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT asdata (301:301:301) (344:344:344))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT ena (667:667:667) (727:727:727))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (183:183:183))
+        (PORT datad (430:430:430) (490:490:490))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT asdata (299:299:299) (340:340:340))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (296:296:296) (335:335:335))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (492:492:492) (583:583:583))
+        (PORT datab (369:369:369) (441:441:441))
+        (PORT datac (152:152:152) (198:198:198))
+        (PORT datad (111:111:111) (132:132:132))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (177:177:177) (238:238:238))
+        (PORT datac (122:122:122) (165:165:165))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (177:177:177) (239:239:239))
+        (PORT datac (125:125:125) (170:170:170))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (453:453:453))
+        (PORT datac (162:162:162) (219:219:219))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1984:1984:1984) (2245:2245:2245))
+        (PORT datad (356:356:356) (426:426:426))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (308:308:308) (348:348:348))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1797:1797:1797) (2026:2026:2026))
+        (PORT datab (143:143:143) (196:196:196))
+        (PORT datac (214:214:214) (267:267:267))
+        (PORT datad (360:360:360) (436:436:436))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (151:151:151) (210:210:210))
+        (PORT datab (143:143:143) (196:196:196))
+        (PORT datac (201:201:201) (253:253:253))
+        (PORT datad (90:90:90) (108:108:108))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (209:209:209))
+        (PORT datab (117:117:117) (150:150:150))
+        (PORT datac (140:140:140) (186:186:186))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (182:182:182) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT asdata (878:878:878) (993:993:993))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (403:403:403) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (683:683:683) (816:816:816))
+        (PORT datab (516:516:516) (596:596:596))
+        (PORT datac (126:126:126) (171:171:171))
+        (PORT datad (470:470:470) (543:543:543))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (669:669:669) (800:800:800))
+        (PORT datab (512:512:512) (592:592:592))
+        (PORT datac (120:120:120) (164:164:164))
+        (PORT datad (475:475:475) (550:550:550))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (559:559:559) (683:683:683))
+        (PORT datab (355:355:355) (415:415:415))
+        (PORT datac (448:448:448) (512:512:512))
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (582:582:582))
+        (PORT datab (511:511:511) (591:591:591))
+        (PORT datac (648:648:648) (769:769:769))
+        (PORT datad (124:124:124) (164:164:164))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (150:150:150) (208:208:208))
+        (PORT datab (153:153:153) (208:208:208))
+        (PORT datac (128:128:128) (175:175:175))
+        (PORT datad (125:125:125) (165:165:165))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (543:543:543) (667:667:667))
+        (PORT datad (91:91:91) (109:109:109))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (290:290:290))
+        (PORT datab (324:324:324) (389:389:389))
+        (PORT datac (202:202:202) (249:249:249))
+        (PORT datad (200:200:200) (244:244:244))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (614:614:614) (655:655:655))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (858:858:858))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (268:268:268))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (197:197:197))
+        (PORT datab (140:140:140) (192:192:192))
+        (PORT datac (128:128:128) (173:173:173))
+        (PORT datad (126:126:126) (167:167:167))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (194:194:194))
+        (PORT datad (132:132:132) (169:169:169))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (858:858:858))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|start_nedge)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (PORT datac (696:696:696) (812:812:812))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (124:124:124) (169:169:169))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (120:120:120) (164:164:164))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1726:1726:1726) (1921:1921:1921))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (142:142:142) (187:187:187))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE rx\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (348:348:348) (728:728:728))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (209:209:209) (257:257:257))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (375:375:375) (453:453:453))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (495:495:495) (574:574:574))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (133:133:133) (170:170:170))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (252:252:252))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (543:543:543) (628:628:628))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (130:130:130) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (132:132:132) (170:170:170))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (354:354:354) (425:425:425))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (123:123:123) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (354:354:354) (428:428:428))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (352:352:352) (425:425:425))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (341:341:341) (411:411:411))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (300:300:300) (359:359:359))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg2\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (116:116:116) (153:153:153))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_clk\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (736:736:736) (766:766:766))
+        (IOPATH i o (1637:1637:1637) (1617:1617:1617))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_cs_n\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (769:769:769) (872:872:872))
+        (IOPATH i o (1637:1637:1637) (1617:1617:1617))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_mosi\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (756:756:756) (851:851:851))
+        (IOPATH i o (1637:1637:1637) (1617:1617:1617))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE tx\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1453:1453:1453) (1256:1256:1256))
+        (IOPATH i o (1755:1755:1755) (1782:1782:1782))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_clk\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (358:358:358) (738:738:738))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1120:1120:1120) (1119:1119:1119))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (150:150:150) (203:203:203))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_rst_n\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (318:318:318) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1648:1648:1648))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (2249:2249:2249) (2037:2037:2037))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE rst_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1558:1558:1558) (1353:1353:1353))
+        (PORT datab (1758:1758:1758) (1966:1966:1966))
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE rst_n\~0clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1074:1074:1074) (1218:1218:1218))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (139:139:139) (191:191:191))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sd_miso\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (288:288:288) (667:667:667))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT asdata (2138:2138:2138) (2396:2396:2396))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1984:1984:1984) (2245:2245:2245))
+        (PORT datab (137:137:137) (188:188:188))
+        (PORT datad (202:202:202) (248:248:248))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (233:233:233) (290:290:290))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (314:314:314) (369:369:369))
+        (PORT datad (211:211:211) (256:256:256))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (271:271:271))
+        (PORT datab (329:329:329) (390:390:390))
+        (PORT datac (312:312:312) (367:367:367))
+        (PORT datad (210:210:210) (255:255:255))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (203:203:203) (245:245:245))
+        (PORT datab (178:178:178) (219:219:219))
+        (PORT datad (99:99:99) (120:120:120))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (859:859:859) (863:863:863))
+        (PORT sclr (470:470:470) (468:468:468))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (215:215:215) (271:271:271))
+        (PORT datab (137:137:137) (187:187:187))
+        (PORT datac (124:124:124) (168:168:168))
+        (PORT datad (123:123:123) (163:163:163))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (282:282:282))
+        (PORT datac (181:181:181) (221:221:221))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (650:650:650) (734:734:734))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (299:299:299) (340:340:340))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (375:375:375) (422:422:422))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (306:306:306) (346:346:346))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (299:299:299) (341:341:341))
+        (PORT clrn (856:856:856) (859:859:859))
+        (PORT ena (636:636:636) (690:690:690))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (134:134:134) (184:184:184))
+        (PORT datad (200:200:200) (243:243:243))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (300:300:300) (354:354:354))
+        (PORT datac (161:161:161) (188:188:188))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (137:137:137) (189:189:189))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (139:139:139) (191:191:191))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (202:202:202))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (157:157:157) (211:211:211))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (155:155:155) (211:211:211))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1856:1856:1856) (2122:2122:2122))
+        (PORT datab (377:377:377) (458:458:458))
+        (PORT datac (146:146:146) (195:195:195))
+        (PORT datad (145:145:145) (189:189:189))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (236:236:236))
+        (PORT datab (104:104:104) (134:134:134))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (137:137:137) (188:188:188))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datac (127:127:127) (174:174:174))
+        (PORT datad (134:134:134) (180:180:180))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (108:108:108) (138:138:138))
+        (PORT datac (146:146:146) (195:195:195))
+        (PORT datad (145:145:145) (189:189:189))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (205:205:205))
+        (PORT datab (135:135:135) (184:184:184))
+        (PORT datac (143:143:143) (192:192:192))
+        (PORT datad (143:143:143) (187:187:187))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (206:206:206))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (152:152:152) (205:205:205))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT sclr (382:382:382) (388:388:388))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (138:138:138) (184:184:184))
+        (PORT datad (140:140:140) (183:183:183))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (480:480:480) (538:538:538))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (296:296:296) (335:335:335))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (293:293:293) (332:332:332))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (295:295:295) (334:334:334))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (294:294:294) (333:333:333))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (293:293:293) (332:332:332))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (124:124:124) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (123:123:123) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT asdata (377:377:377) (426:426:426))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT ena (760:760:760) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (350:350:350) (422:422:422))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (293:293:293) (332:332:332))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (296:296:296) (335:335:335))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (294:294:294) (333:333:333))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (296:296:296) (335:335:335))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (296:296:296) (336:336:336))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT asdata (294:294:294) (334:334:334))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (116:116:116) (153:153:153))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (868:868:868))
+        (PORT ena (610:610:610) (650:650:650))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (470:470:470) (524:524:524))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (130:130:130) (172:172:172))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (191:191:191) (237:237:237))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (370:370:370) (418:418:418))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (266:266:266))
+        (PORT datad (192:192:192) (238:238:238))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (364:364:364) (409:409:409))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (300:300:300) (342:342:342))
+        (PORT clrn (861:861:861) (867:867:867))
+        (PORT ena (510:510:510) (553:553:553))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (PORT datab (137:137:137) (188:188:188))
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (114:114:114) (147:147:147))
+        (PORT datad (100:100:100) (122:122:122))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (137:137:137))
+        (PORT datab (322:322:322) (381:381:381))
+        (PORT datac (132:132:132) (181:181:181))
+        (PORT datad (178:178:178) (213:213:213))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (186:186:186))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (195:195:195))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (268:268:268))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (108:108:108) (139:139:139))
+        (PORT datac (129:129:129) (176:176:176))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (PORT sload (417:417:417) (459:459:459))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sload (posedge clk) (84:84:84))
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (144:144:144) (200:200:200))
+        (PORT datab (109:109:109) (140:140:140))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (854:854:854) (857:857:857))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (313:313:313) (373:373:373))
+        (PORT datad (284:284:284) (330:330:330))
+        (IOPATH dataa combout (165:165:165) (163:163:163))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (197:197:197) (238:238:238))
+        (PORT datac (125:125:125) (170:170:170))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (146:146:146) (196:196:196))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (136:136:136) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (188:188:188))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (212:212:212) (277:277:277))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (134:134:134) (173:173:173))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (372:372:372) (452:452:452))
+        (PORT datac (354:354:354) (407:407:407))
+        (PORT datad (115:115:115) (138:138:138))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (PORT sclr (319:319:319) (370:370:370))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (417:417:417) (501:501:501))
+        (PORT datab (450:450:450) (545:545:545))
+        (PORT datac (408:408:408) (490:490:490))
+        (PORT datad (414:414:414) (498:498:498))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (348:348:348) (400:400:400))
+        (PORT datad (110:110:110) (132:132:132))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (291:291:291) (345:345:345))
+        (PORT datab (152:152:152) (203:203:203))
+        (PORT datad (202:202:202) (243:243:243))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (460:460:460) (543:543:543))
+        (PORT datab (145:145:145) (199:199:199))
+        (PORT datac (134:134:134) (184:184:184))
+        (PORT datad (176:176:176) (211:211:211))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (292:292:292) (347:347:347))
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datad (203:203:203) (244:244:244))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (293:293:293) (348:348:348))
+        (PORT datab (147:147:147) (198:198:198))
+        (PORT datad (204:204:204) (245:245:245))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (207:207:207))
+        (PORT datab (226:226:226) (272:272:272))
+        (PORT datad (307:307:307) (361:361:361))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (201:201:201))
+        (PORT datab (222:222:222) (268:268:268))
+        (PORT datad (301:301:301) (354:354:354))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (149:149:149) (208:208:208))
+        (PORT datab (145:145:145) (198:198:198))
+        (PORT datac (130:130:130) (178:178:178))
+        (PORT datad (131:131:131) (168:168:168))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (454:454:454))
+        (PORT datac (292:292:292) (336:336:336))
+        (PORT datad (134:134:134) (173:173:173))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (191:191:191) (238:238:238))
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datac (131:131:131) (179:179:179))
+        (PORT datad (305:305:305) (359:359:359))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (207:207:207))
+        (PORT datab (149:149:149) (200:200:200))
+        (PORT datac (204:204:204) (256:256:256))
+        (PORT datad (139:139:139) (180:180:180))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (430:430:430))
+        (PORT datab (128:128:128) (161:161:161))
+        (PORT datac (188:188:188) (222:222:222))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (195:195:195))
+        (PORT datab (197:197:197) (238:238:238))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (866:866:866))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (195:195:195))
+        (PORT datac (305:305:305) (368:368:368))
+        (PORT datad (139:139:139) (180:180:180))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (394:394:394))
+        (PORT datab (309:309:309) (359:359:359))
+        (PORT datac (90:90:90) (112:112:112))
+        (PORT datad (456:456:456) (528:528:528))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (147:147:147) (197:197:197))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (141:141:141) (194:194:194))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (200:200:200))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (267:267:267))
+        (PORT datab (142:142:142) (195:195:195))
+        (PORT datac (131:131:131) (179:179:179))
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (194:194:194))
+        (PORT datac (133:133:133) (176:176:176))
+        (PORT datad (125:125:125) (166:166:166))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (155:155:155) (214:214:214))
+        (PORT datab (108:108:108) (138:138:138))
+        (PORT datac (185:185:185) (216:216:216))
+        (PORT datad (381:381:381) (464:464:464))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (204:204:204) (246:246:246))
+        (PORT datab (460:460:460) (525:525:525))
+        (PORT datad (99:99:99) (120:120:120))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (114:114:114) (149:149:149))
+        (PORT datab (138:138:138) (189:189:189))
+        (PORT datac (186:186:186) (228:228:228))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (365:365:365))
+        (PORT datab (336:336:336) (398:398:398))
+        (PORT datad (456:456:456) (527:527:527))
+        (IOPATH dataa combout (165:165:165) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (147:147:147) (201:201:201))
+        (PORT datac (141:141:141) (187:187:187))
+        (PORT datad (130:130:130) (173:173:173))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (PORT datab (211:211:211) (267:267:267))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (114:114:114) (149:149:149))
+        (PORT datab (186:186:186) (223:223:223))
+        (PORT datac (185:185:185) (218:218:218))
+        (PORT datad (218:218:218) (267:267:267))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (146:146:146) (204:204:204))
+        (PORT datab (661:661:661) (788:788:788))
+        (PORT datad (116:116:116) (138:138:138))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (210:210:210))
+        (PORT datac (130:130:130) (177:177:177))
+        (PORT datad (126:126:126) (166:166:166))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (544:544:544) (669:669:669))
+        (PORT datac (91:91:91) (113:113:113))
+        (PORT datad (115:115:115) (138:138:138))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (207:207:207))
+        (PORT datac (127:127:127) (173:173:173))
+        (PORT datad (125:125:125) (165:165:165))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (197:197:197))
+        (PORT datad (238:238:238) (295:295:295))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (321:321:321))
+        (PORT datac (119:119:119) (163:163:163))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (320:320:320))
+        (PORT datad (190:190:190) (238:238:238))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datac (122:122:122) (165:165:165))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (194:194:194))
+        (PORT datab (209:209:209) (267:267:267))
+        (PORT datac (124:124:124) (168:168:168))
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (223:223:223) (281:281:281))
+        (PORT datad (237:237:237) (293:293:293))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (317:317:317))
+        (PORT datac (123:123:123) (167:167:167))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (318:318:318))
+        (PORT datac (121:121:121) (164:164:164))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (178:178:178) (239:239:239))
+        (PORT datac (121:121:121) (164:164:164))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (PORT datab (137:137:137) (188:188:188))
+        (PORT datac (201:201:201) (246:246:246))
+        (PORT datad (200:200:200) (252:252:252))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (243:243:243))
+        (PORT datab (109:109:109) (140:140:140))
+        (PORT datac (184:184:184) (224:224:224))
+        (PORT datad (176:176:176) (209:209:209))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (179:179:179) (216:216:216))
+        (PORT datab (318:318:318) (370:370:370))
+        (PORT datad (91:91:91) (109:109:109))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (178:178:178) (241:241:241))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (177:177:177) (238:238:238))
+        (PORT datac (123:123:123) (168:168:168))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (PORT datab (178:178:178) (240:240:240))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (176:176:176) (237:237:237))
+        (PORT datac (123:123:123) (167:167:167))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datac (121:121:121) (165:165:165))
+        (PORT datad (122:122:122) (162:162:162))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (200:200:200) (242:242:242))
+        (PORT datab (109:109:109) (139:139:139))
+        (PORT datac (183:183:183) (222:222:222))
+        (PORT datad (176:176:176) (209:209:209))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (541:541:541) (665:665:665))
+        (PORT datab (128:128:128) (160:160:160))
+        (PORT datad (116:116:116) (138:138:138))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (545:545:545) (670:670:670))
+        (PORT datab (127:127:127) (159:159:159))
+        (PORT datac (161:161:161) (193:193:193))
+        (PORT datad (140:140:140) (184:184:184))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (136:136:136) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (199:199:199))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (197:197:197))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (864:864:864))
+        (PORT sclr (670:670:670) (642:642:642))
+        (PORT ena (488:488:488) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (117:117:117) (154:154:154))
+        (PORT datab (126:126:126) (158:158:158))
+        (PORT datac (198:198:198) (245:245:245))
+        (PORT datad (140:140:140) (184:184:184))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (190:190:190) (227:227:227))
+        (PORT datab (235:235:235) (291:291:291))
+        (PORT datad (90:90:90) (108:108:108))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (188:188:188) (228:228:228))
+        (PORT datab (336:336:336) (397:397:397))
+        (PORT datad (197:197:197) (246:246:246))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (201:201:201) (250:250:250))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (191:191:191))
+        (PORT datad (200:200:200) (249:249:249))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (133:133:133) (185:185:185))
+        (PORT datac (124:124:124) (169:169:169))
+        (PORT datad (127:127:127) (169:169:169))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (136:136:136))
+        (PORT datab (121:121:121) (151:151:151))
+        (PORT datad (203:203:203) (252:252:252))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (190:190:190))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (257:257:257))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (137:137:137) (189:189:189))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (210:210:210) (269:269:269))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (139:139:139) (191:191:191))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (187:187:187))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (PORT sclr (384:384:384) (390:390:390))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (122:122:122) (165:165:165))
+        (PORT datad (123:123:123) (163:163:163))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (149:149:149) (208:208:208))
+        (PORT datab (214:214:214) (273:273:273))
+        (PORT datac (127:127:127) (173:173:173))
+        (PORT datad (129:129:129) (171:171:171))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (121:121:121) (151:151:151))
+        (PORT datad (104:104:104) (121:121:121))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (150:150:150) (209:209:209))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datad (108:108:108) (127:127:127))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (299:299:299) (340:340:340))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (373:373:373) (420:420:420))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (PORT datab (134:134:134) (184:184:184))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (306:306:306) (346:346:346))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (303:303:303) (346:346:346))
+        (PORT clrn (860:860:860) (863:863:863))
+        (PORT ena (623:623:623) (668:668:668))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (195:195:195))
+        (PORT datab (137:137:137) (187:187:187))
+        (PORT datad (203:203:203) (248:248:248))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (337:337:337) (397:397:397))
+        (PORT datad (314:314:314) (367:367:367))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (790:790:790) (907:907:907))
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH dataa combout (165:165:165) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (983:983:983) (1135:1135:1135))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (870:870:870))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (157:157:157) (212:212:212))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (870:870:870))
+        (PORT sclr (1357:1357:1357) (1249:1249:1249))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (158:158:158) (212:212:212))
+        (PORT datad (137:137:137) (181:181:181))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (870:870:870))
+        (PORT sclr (1357:1357:1357) (1249:1249:1249))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (282:282:282))
+        (PORT datab (160:160:160) (221:221:221))
+        (PORT datac (141:141:141) (188:188:188))
+        (PORT datad (135:135:135) (179:179:179))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (809:809:809) (942:942:942))
+        (PORT datad (430:430:430) (491:491:491))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (891:891:891))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (867:867:867) (874:874:874))
+        (PORT sclr (1252:1252:1252) (1160:1160:1160))
+        (PORT ena (488:488:488) (520:520:520))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (442:442:442) (515:515:515))
+        (PORT datab (229:229:229) (285:285:285))
+        (PORT datac (216:216:216) (268:268:268))
+        (PORT datad (204:204:204) (249:249:249))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (195:195:195) (233:233:233))
+        (PORT datab (240:240:240) (298:298:298))
+        (PORT datac (202:202:202) (251:251:251))
+        (PORT datad (104:104:104) (122:122:122))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (468:468:468) (557:557:557))
+        (PORT datab (681:681:681) (783:783:783))
+        (PORT datad (174:174:174) (198:198:198))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2019:2019:2019) (2296:2296:2296))
+        (PORT datad (158:158:158) (206:206:206))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (123:123:123) (167:167:167))
+        (PORT datad (158:158:158) (208:208:208))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (124:124:124) (169:169:169))
+        (PORT datad (158:158:158) (207:207:207))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (124:124:124) (168:168:168))
+        (PORT datad (157:157:157) (207:207:207))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (134:134:134) (187:187:187))
+        (PORT datab (138:138:138) (189:189:189))
+        (PORT datac (119:119:119) (162:162:162))
+        (PORT datad (124:124:124) (164:164:164))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datad (158:158:158) (206:206:206))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (143:143:143) (192:192:192))
+        (PORT datad (157:157:157) (207:207:207))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (122:122:122) (165:165:165))
+        (PORT datad (159:159:159) (208:208:208))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (123:123:123) (167:167:167))
+        (PORT datad (157:157:157) (207:207:207))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (215:215:215) (270:270:270))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datad (92:92:92) (109:109:109))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (493:493:493) (586:586:586))
+        (PORT datab (456:456:456) (518:518:518))
+        (PORT datad (101:101:101) (124:124:124))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (197:197:197))
+        (PORT datad (201:201:201) (253:253:253))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (202:202:202) (254:254:254))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (141:141:141) (196:196:196))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datad (203:203:203) (256:256:256))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (127:127:127) (172:172:172))
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (702:702:702) (818:818:818))
+        (PORT datad (102:102:102) (124:124:124))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (700:700:700) (817:817:817))
+        (PORT datab (114:114:114) (147:147:147))
+        (PORT datad (198:198:198) (250:250:250))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (311:311:311) (378:378:378))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (131:131:131) (180:180:180))
+        (PORT datad (310:310:310) (378:378:378))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (318:318:318) (390:390:390))
+        (PORT datab (123:123:123) (153:153:153))
+        (PORT datad (128:128:128) (170:170:170))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (876:876:876))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (856:856:856) (859:859:859))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (404:404:404))
+        (PORT datab (149:149:149) (200:200:200))
+        (PORT datac (295:295:295) (354:354:354))
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (146:146:146) (204:204:204))
+        (PORT datab (145:145:145) (200:200:200))
+        (PORT datac (133:133:133) (181:181:181))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (149:149:149) (207:207:207))
+        (PORT datab (144:144:144) (197:197:197))
+        (PORT datac (128:128:128) (174:174:174))
+        (PORT datad (129:129:129) (170:170:170))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (405:405:405))
+        (PORT datab (221:221:221) (279:279:279))
+        (PORT datac (219:219:219) (275:275:275))
+        (PORT datad (176:176:176) (209:209:209))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (114:114:114) (149:149:149))
+        (PORT datab (219:219:219) (278:278:278))
+        (PORT datac (217:217:217) (272:272:272))
+        (PORT datad (180:180:180) (213:213:213))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (145:145:145))
+        (PORT datab (189:189:189) (226:226:226))
+        (PORT datac (90:90:90) (111:111:111))
+        (PORT datad (105:105:105) (123:123:123))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (236:236:236))
+        (PORT datab (283:283:283) (328:328:328))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (451:451:451) (522:522:522))
+        (PORT datac (117:117:117) (158:158:158))
+        (PORT datad (310:310:310) (371:371:371))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (368:368:368) (433:433:433))
+        (PORT datad (350:350:350) (399:399:399))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (868:868:868))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (272:272:272))
+        (PORT datab (142:142:142) (195:195:195))
+        (PORT datac (131:131:131) (179:179:179))
+        (PORT datad (128:128:128) (170:170:170))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (PORT sclr (682:682:682) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (154:154:154) (214:214:214))
+        (PORT datab (104:104:104) (132:132:132))
+        (PORT datac (131:131:131) (179:179:179))
+        (PORT datad (128:128:128) (171:171:171))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (211:211:211))
+        (PORT datab (115:115:115) (144:144:144))
+        (PORT datac (92:92:92) (114:114:114))
+        (PORT datad (375:375:375) (458:458:458))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (867:867:867) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (851:851:851) (855:855:855))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (137:137:137) (187:187:187))
+        (IOPATH datab combout (167:167:167) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (92:92:92) (114:114:114))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (155:155:155) (214:214:214))
+        (PORT datab (137:137:137) (187:187:187))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (153:153:153) (207:207:207))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (156:156:156) (216:216:216))
+        (PORT datab (104:104:104) (132:132:132))
+        (PORT datad (105:105:105) (130:130:130))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (151:151:151) (208:208:208))
+        (PORT datab (155:155:155) (209:209:209))
+        (PORT datac (92:92:92) (114:114:114))
+        (PORT datad (103:103:103) (127:127:127))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datad (123:123:123) (163:163:163))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (269:269:269))
+        (PORT datab (134:134:134) (183:183:183))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (274:274:274))
+        (PORT datab (137:137:137) (187:187:187))
+        (PORT datac (120:120:120) (163:163:163))
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (289:289:289))
+        (PORT datab (324:324:324) (389:389:389))
+        (PORT datac (202:202:202) (249:249:249))
+        (PORT datad (200:200:200) (244:244:244))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (198:198:198) (238:238:238))
+        (PORT datab (237:237:237) (295:295:295))
+        (PORT datac (178:178:178) (217:217:217))
+        (PORT datad (269:269:269) (308:308:308))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (184:184:184))
+        (PORT datad (93:93:93) (110:110:110))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (106:106:106) (136:136:136))
+        (PORT datad (130:130:130) (167:167:167))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (192:192:192))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (192:192:192))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (197:197:197))
+        (PORT datab (141:141:141) (192:192:192))
+        (PORT datac (128:128:128) (173:173:173))
+        (PORT datad (127:127:127) (167:167:167))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (294:294:294) (342:342:342))
+        (PORT datab (233:233:233) (292:292:292))
+        (PORT datac (183:183:183) (222:222:222))
+        (PORT datad (163:163:163) (191:191:191))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (120:120:120) (154:154:154))
+        (PORT datac (141:141:141) (190:190:190))
+        (PORT datad (197:197:197) (243:243:243))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (884:884:884) (892:892:892))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (868:868:868) (875:875:875))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (556:556:556) (640:640:640))
+        (PORT clrn (862:862:862) (868:868:868))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (496:496:496) (549:549:549))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (588:588:588) (701:701:701))
+        (PORT datab (558:558:558) (667:667:667))
+        (PORT datac (352:352:352) (409:409:409))
+        (PORT datad (617:617:617) (729:729:729))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (128:128:128) (164:164:164))
+        (PORT datad (143:143:143) (185:185:185))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (589:589:589) (701:701:701))
+        (PORT datab (557:557:557) (666:666:666))
+        (PORT datac (353:353:353) (409:409:409))
+        (PORT datad (616:616:616) (728:728:728))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (156:156:156) (211:211:211))
+        (PORT datab (220:220:220) (276:276:276))
+        (PORT datad (174:174:174) (198:198:198))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (150:150:150) (204:204:204))
+        (PORT datab (159:159:159) (214:214:214))
+        (PORT datac (111:111:111) (136:136:136))
+        (PORT datad (143:143:143) (186:186:186))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (157:157:157) (213:213:213))
+        (PORT datad (99:99:99) (120:120:120))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (154:154:154) (210:210:210))
+        (PORT datac (145:145:145) (194:194:194))
+        (PORT datad (98:98:98) (118:118:118))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (158:158:158) (216:216:216))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (555:555:555) (651:651:651))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (108:108:108) (140:140:140))
+        (PORT datad (206:206:206) (258:258:258))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (201:201:201) (247:247:247))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (508:508:508) (596:596:596))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (494:494:494) (580:580:580))
+        (PORT datab (383:383:383) (460:460:460))
+        (PORT datad (128:128:128) (169:169:169))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (211:211:211) (260:260:260))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (498:498:498) (590:590:590))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (201:201:201) (253:253:253))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (118:118:118) (155:155:155))
+        (PORT datab (151:151:151) (203:203:203))
+        (PORT datad (205:205:205) (248:248:248))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (161:161:161) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (203:203:203) (256:256:256))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (525:525:525) (591:591:591))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (354:354:354))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (293:293:293) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (321:321:321) (368:368:368))
+        (PORT ena (672:672:672) (728:728:728))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (379:379:379) (467:467:467))
+        (PORT datab (147:147:147) (197:197:197))
+        (PORT datad (400:400:400) (482:482:482))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (319:319:319) (365:365:365))
+        (PORT ena (672:672:672) (728:728:728))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (382:382:382) (436:436:436))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (336:336:336) (404:404:404))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (190:190:190) (238:238:238))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (366:366:366) (412:412:412))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (222:222:222) (270:270:270))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (659:659:659) (743:743:743))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (246:246:246) (302:302:302))
+        (PORT datab (406:406:406) (487:487:487))
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (314:314:314) (369:369:369))
+        (PORT datac (159:159:159) (191:191:191))
+        (PORT datad (294:294:294) (342:342:342))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (136:136:136))
+        (PORT datab (598:598:598) (703:703:703))
+        (PORT datac (525:525:525) (597:597:597))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (219:219:219) (281:281:281))
+        (PORT datab (157:157:157) (210:210:210))
+        (PORT datad (350:350:350) (410:410:410))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (597:597:597) (709:709:709))
+        (PORT datab (156:156:156) (210:210:210))
+        (PORT datac (141:141:141) (181:181:181))
+        (PORT datad (544:544:544) (638:638:638))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (155:155:155) (212:212:212))
+        (PORT datad (94:94:94) (113:113:113))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (572:572:572) (675:675:675))
+        (PORT datad (533:533:533) (619:619:619))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (201:201:201))
+        (PORT datab (156:156:156) (211:211:211))
+        (PORT datac (114:114:114) (141:141:141))
+        (PORT datad (143:143:143) (186:186:186))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (156:156:156) (214:214:214))
+        (PORT datab (158:158:158) (214:214:214))
+        (PORT datac (143:143:143) (191:191:191))
+        (PORT datad (226:226:226) (279:279:279))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (672:672:672) (728:728:728))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (131:131:131) (178:178:178))
+        (PORT datac (118:118:118) (160:160:160))
+        (PORT datad (541:541:541) (631:631:631))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (157:157:157) (211:211:211))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (457:457:457) (541:541:541))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT asdata (366:366:366) (416:416:416))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (552:552:552) (625:625:625))
+        (PORT ena (675:675:675) (751:751:751))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (315:315:315) (358:358:358))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (199:199:199) (250:250:250))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (449:449:449))
+        (PORT datab (354:354:354) (424:424:424))
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (143:143:143))
+        (PORT datab (130:130:130) (179:179:179))
+        (PORT datad (95:95:95) (113:113:113))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (330:330:330) (388:388:388))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (406:406:406))
+        (PORT datab (336:336:336) (405:405:405))
+        (PORT datac (281:281:281) (316:316:316))
+        (PORT datad (191:191:191) (238:238:238))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (219:219:219) (282:282:282))
+        (PORT datab (152:152:152) (203:203:203))
+        (PORT datac (210:210:210) (261:261:261))
+        (PORT datad (103:103:103) (126:126:126))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (159:159:159) (214:214:214))
+        (PORT datad (98:98:98) (118:118:118))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (281:281:281))
+        (PORT datab (157:157:157) (211:211:211))
+        (PORT datac (147:147:147) (190:190:190))
+        (PORT datad (201:201:201) (252:252:252))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (614:614:614) (655:655:655))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (409:409:409))
+        (PORT datab (153:153:153) (206:206:206))
+        (PORT datac (324:324:324) (388:388:388))
+        (PORT datad (137:137:137) (179:179:179))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (614:614:614) (655:655:655))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (133:133:133) (184:184:184))
+        (PORT datab (132:132:132) (180:180:180))
+        (PORT datac (119:119:119) (160:160:160))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (614:614:614) (655:655:655))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (334:334:334) (401:401:401))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (531:531:531) (579:579:579))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (PORT datab (146:146:146) (197:197:197))
+        (PORT datac (195:195:195) (234:234:234))
+        (PORT datad (334:334:334) (401:401:401))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (265:265:265) (300:300:300))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (154:154:154) (206:206:206))
+        (PORT datad (103:103:103) (127:127:127))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (282:282:282))
+        (PORT datab (152:152:152) (205:205:205))
+        (PORT datac (209:209:209) (260:260:260))
+        (PORT datad (104:104:104) (128:128:128))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (288:288:288))
+        (PORT datab (157:157:157) (212:212:212))
+        (PORT datad (100:100:100) (121:121:121))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (161:161:161) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (159:159:159) (213:213:213))
+        (PORT datac (144:144:144) (188:188:188))
+        (PORT datad (98:98:98) (118:118:118))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (283:283:283))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (393:393:393) (444:444:444))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (641:641:641) (717:717:717))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (297:297:297) (337:337:337))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (293:293:293) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (129:129:129) (175:175:175))
+        (PORT datad (132:132:132) (175:175:175))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (152:152:152) (208:208:208))
+        (PORT datab (162:162:162) (217:217:217))
+        (PORT datad (98:98:98) (119:119:119))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT asdata (595:595:595) (668:668:668))
+        (PORT ena (605:605:605) (656:656:656))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (534:534:534) (620:620:620))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (666:666:666) (726:726:726))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (519:519:519) (618:618:618))
+        (PORT datac (148:148:148) (193:193:193))
+        (PORT datad (471:471:471) (548:548:548))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (134:134:134) (183:183:183))
+        (PORT datac (124:124:124) (170:170:170))
+        (PORT datad (129:129:129) (170:170:170))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (582:582:582) (686:686:686))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (675:675:675) (751:751:751))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (517:517:517) (616:616:616))
+        (PORT datab (484:484:484) (570:570:570))
+        (PORT datac (147:147:147) (192:192:192))
+        (PORT datad (385:385:385) (464:464:464))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (134:134:134) (178:178:178))
+        (PORT datad (321:321:321) (374:374:374))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (705:705:705))
+        (PORT datac (136:136:136) (180:180:180))
+        (PORT datad (319:319:319) (372:372:372))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (736:736:736) (838:838:838))
+        (PORT ena (675:675:675) (751:751:751))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (705:705:705))
+        (PORT datab (654:654:654) (771:771:771))
+        (PORT datac (133:133:133) (176:176:176))
+        (PORT datad (319:319:319) (372:372:372))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (254:254:254))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (511:511:511) (580:580:580))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (358:358:358))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (116:116:116) (153:153:153))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (394:394:394) (447:447:447))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (640:640:640) (720:720:720))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (308:308:308) (370:370:370))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (296:296:296) (335:335:335))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (PORT datab (204:204:204) (264:264:264))
+        (PORT datac (132:132:132) (176:176:176))
+        (PORT datad (597:597:597) (686:686:686))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (335:335:335) (395:395:395))
+        (PORT datad (276:276:276) (310:310:310))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT asdata (715:715:715) (808:808:808))
+        (PORT ena (675:675:675) (751:751:751))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (113:113:113) (147:147:147))
+        (PORT datac (139:139:139) (185:185:185))
+        (PORT datad (213:213:213) (261:261:261))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (219:219:219) (259:259:259))
+        (PORT datab (148:148:148) (199:199:199))
+        (PORT datad (335:335:335) (401:401:401))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (315:315:315) (368:368:368))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (605:605:605) (638:638:638))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (456:456:456) (531:531:531))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT asdata (480:480:480) (536:536:536))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (315:315:315) (379:379:379))
+        (PORT datab (141:141:141) (193:193:193))
+        (PORT datac (149:149:149) (193:193:193))
+        (PORT datad (106:106:106) (125:125:125))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (315:315:315) (378:378:378))
+        (PORT datab (460:460:460) (544:544:544))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (425:425:425))
+        (PORT datab (217:217:217) (275:275:275))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (268:268:268))
+        (PORT datab (358:358:358) (437:437:437))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (280:280:280))
+        (PORT datab (343:343:343) (419:419:419))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (182:182:182))
+        (PORT datab (196:196:196) (252:252:252))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (133:133:133) (184:184:184))
+        (PORT datad (197:197:197) (245:245:245))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (175:175:175) (218:218:218))
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datac (91:91:91) (113:113:113))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (812:812:812) (944:944:944))
+        (PORT datac (90:90:90) (111:111:111))
+        (PORT datad (92:92:92) (109:109:109))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (106:106:106) (138:138:138))
+        (PORT datab (106:106:106) (135:135:135))
+        (PORT datac (88:88:88) (110:110:110))
+        (PORT datad (89:89:89) (106:106:106))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (809:809:809) (928:928:928))
+        (PORT datab (148:148:148) (199:199:199))
+        (PORT datac (680:680:680) (787:787:787))
+        (PORT datad (301:301:301) (361:361:361))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (144:144:144))
+        (PORT datab (338:338:338) (398:398:398))
+        (PORT datac (90:90:90) (112:112:112))
+        (PORT datad (317:317:317) (370:370:370))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (857:857:857) (860:860:860))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (199:199:199))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (199:199:199))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (143:143:143) (195:195:195))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (205:205:205))
+        (PORT datab (147:147:147) (201:201:201))
+        (PORT datac (131:131:131) (178:178:178))
+        (PORT datad (132:132:132) (175:175:175))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (196:196:196))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (872:872:872))
+        (PORT sclr (1174:1174:1174) (1088:1088:1088))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datac (133:133:133) (182:182:182))
+        (PORT datad (132:132:132) (176:176:176))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (198:198:198))
+        (PORT datac (131:131:131) (178:178:178))
+        (PORT datad (129:129:129) (171:171:171))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (145:145:145) (199:199:199))
+        (PORT datac (133:133:133) (182:182:182))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (136:136:136))
+        (PORT datab (177:177:177) (217:217:217))
+        (PORT datac (826:826:826) (953:953:953))
+        (PORT datad (301:301:301) (347:347:347))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (410:410:410))
+        (PORT datab (839:839:839) (972:972:972))
+        (PORT datac (809:809:809) (942:942:942))
+        (PORT datad (205:205:205) (251:251:251))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (136:136:136))
+        (PORT datab (841:841:841) (974:974:974))
+        (PORT datac (90:90:90) (111:111:111))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (866:866:866) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (404:404:404))
+        (PORT datab (363:363:363) (440:440:440))
+        (PORT datac (703:703:703) (823:823:823))
+        (PORT datad (137:137:137) (178:178:178))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (322:322:322) (394:394:394))
+        (PORT datac (365:365:365) (430:430:430))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1120:1120:1120) (1119:1119:1119))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (439:439:439))
+        (PORT datab (134:134:134) (183:183:183))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (189:189:189))
+        (PORT datab (136:136:136) (187:187:187))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (416:416:416))
+        (PORT datab (310:310:310) (364:364:364))
+        (PORT datac (347:347:347) (418:418:418))
+        (PORT datad (352:352:352) (421:421:421))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (192:192:192))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (146:146:146) (202:202:202))
+        (PORT datab (142:142:142) (194:194:194))
+        (PORT datac (130:130:130) (176:176:176))
+        (PORT datad (129:129:129) (171:171:171))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (441:441:441))
+        (PORT datac (351:351:351) (424:424:424))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (422:422:422))
+        (PORT datab (111:111:111) (142:142:142))
+        (PORT datac (307:307:307) (359:359:359))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (138:138:138) (191:191:191))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (136:136:136) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (139:139:139) (192:192:192))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (546:546:546) (634:634:634))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (202:202:202))
+        (PORT datab (142:142:142) (194:194:194))
+        (PORT datac (129:129:129) (176:176:176))
+        (PORT datad (129:129:129) (171:171:171))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (440:440:440))
+        (PORT datab (369:369:369) (445:445:445))
+        (PORT datac (418:418:418) (471:471:471))
+        (PORT datad (98:98:98) (119:119:119))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (464:464:464) (550:550:550))
+        (PORT datad (461:461:461) (538:538:538))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (483:483:483) (564:564:564))
+        (PORT datac (148:148:148) (205:205:205))
+        (PORT datad (127:127:127) (169:169:169))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (464:464:464) (551:551:551))
+        (PORT datab (485:485:485) (568:568:568))
+        (PORT datad (118:118:118) (142:142:142))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (885:885:885) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (869:869:869) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (168:168:168))
+        (PORT datab (161:161:161) (223:223:223))
+        (PORT datad (103:103:103) (125:125:125))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (885:885:885) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (869:869:869) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (269:269:269))
+        (PORT datab (142:142:142) (194:194:194))
+        (PORT datac (150:150:150) (208:208:208))
+        (PORT datad (146:146:146) (195:195:195))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (168:168:168))
+        (PORT datab (115:115:115) (148:148:148))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (885:885:885) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (869:869:869) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (188:188:188))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (234:234:234) (292:292:292))
+        (PORT datac (317:317:317) (381:381:381))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT asdata (649:649:649) (731:731:731))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (132:132:132) (182:182:182))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (183:183:183))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (191:191:191))
+        (PORT datab (137:137:137) (188:188:188))
+        (PORT datac (123:123:123) (166:166:166))
+        (PORT datad (125:125:125) (164:164:164))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (866:866:866))
+        (PORT sclr (653:653:653) (627:627:627))
+        (PORT ena (639:639:639) (693:693:693))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (191:191:191))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datac (123:123:123) (166:166:166))
+        (PORT datad (124:124:124) (163:163:163))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (177:177:177) (214:214:214))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (89:89:89) (111:111:111))
+        (PORT datad (318:318:318) (371:371:371))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (518:518:518) (620:620:620))
+        (PORT datab (131:131:131) (179:179:179))
+        (PORT datad (400:400:400) (450:450:450))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (289:289:289))
+        (PORT datab (217:217:217) (271:271:271))
+        (PORT datac (202:202:202) (251:251:251))
+        (PORT datad (211:211:211) (258:258:258))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (143:143:143))
+        (PORT datab (106:106:106) (135:135:135))
+        (PORT datac (129:129:129) (169:169:169))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (285:285:285))
+        (PORT datab (214:214:214) (268:268:268))
+        (PORT datac (199:199:199) (247:247:247))
+        (PORT datad (207:207:207) (255:255:255))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (193:193:193))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (269:269:269))
+        (PORT datab (209:209:209) (263:263:263))
+        (PORT datac (199:199:199) (243:243:243))
+        (PORT datad (207:207:207) (253:253:253))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (862:862:862) (866:866:866))
+        (PORT sclr (395:395:395) (458:458:458))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (314:314:314) (376:376:376))
+        (PORT datab (227:227:227) (280:280:280))
+        (PORT datac (298:298:298) (350:350:350))
+        (PORT datad (198:198:198) (241:241:241))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (593:593:593) (696:696:696))
+        (PORT datab (209:209:209) (263:263:263))
+        (PORT datac (91:91:91) (114:114:114))
+        (PORT datad (90:90:90) (109:109:109))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (234:234:234) (291:291:291))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (317:317:317) (381:381:381))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (103:103:103) (135:135:135))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (152:152:152) (205:205:205))
+        (PORT datac (147:147:147) (196:196:196))
+        (PORT datad (98:98:98) (120:120:120))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (151:151:151) (204:204:204))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (334:334:334) (395:395:395))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (521:521:521) (555:555:555))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (414:414:414))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (363:363:363) (437:437:437))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (452:452:452) (481:481:481))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (507:507:507) (569:569:569))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (294:294:294) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (544:544:544) (617:617:617))
+        (PORT ena (534:534:534) (577:577:577))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (327:327:327) (394:394:394))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (484:484:484) (576:576:576))
+        (PORT datab (144:144:144) (193:193:193))
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (147:147:147) (201:201:201))
+        (PORT datac (141:141:141) (188:188:188))
+        (PORT datad (131:131:131) (174:174:174))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (117:117:117) (153:153:153))
+        (PORT datab (169:169:169) (206:206:206))
+        (PORT datac (188:188:188) (221:221:221))
+        (PORT datad (217:217:217) (266:266:266))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (542:542:542) (667:667:667))
+        (PORT datab (149:149:149) (204:204:204))
+        (PORT datac (179:179:179) (207:207:207))
+        (PORT datad (109:109:109) (129:129:129))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (877:877:877) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (861:861:861) (865:865:865))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (551:551:551) (628:628:628))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (295:295:295) (335:335:335))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (341:341:341) (406:406:406))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (649:649:649) (691:691:691))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT asdata (308:308:308) (348:348:348))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (203:203:203) (257:257:257))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (283:283:283))
+        (PORT datab (230:230:230) (287:287:287))
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH datab combout (182:182:182) (193:193:193))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (364:364:364) (442:442:442))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT asdata (730:730:730) (805:805:805))
+        (PORT ena (521:521:521) (555:555:555))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (534:534:534) (612:612:612))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (150:150:150) (204:204:204))
+        (PORT datab (152:152:152) (204:204:204))
+        (PORT datac (181:181:181) (220:220:220))
+        (PORT datad (137:137:137) (179:179:179))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (490:490:490) (582:582:582))
+        (PORT datab (372:372:372) (444:444:444))
+        (PORT datad (111:111:111) (131:131:131))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (223:223:223) (271:271:271))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (449:449:449) (480:480:480))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (319:319:319) (376:376:376))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (357:357:357) (433:433:433))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (435:435:435))
+        (PORT datab (205:205:205) (265:265:265))
+        (PORT datad (118:118:118) (156:156:156))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (310:310:310) (370:370:370))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (306:306:306) (346:346:346))
+        (PORT ena (534:534:534) (577:577:577))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (131:131:131) (168:168:168))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (294:294:294) (333:333:333))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (137:137:137) (176:176:176))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (534:534:534) (577:577:577))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (128:128:128) (165:165:165))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (269:269:269))
+        (PORT datab (350:350:350) (424:424:424))
+        (PORT datad (118:118:118) (156:156:156))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (89:89:89) (111:111:111))
+        (PORT datad (310:310:310) (360:360:360))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (110:110:110) (142:142:142))
+        (PORT datac (752:752:752) (862:862:862))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (413:413:413))
+        (PORT datab (153:153:153) (205:205:205))
+        (PORT datad (298:298:298) (335:335:335))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (367:367:367) (447:447:447))
+        (PORT datab (213:213:213) (276:276:276))
+        (PORT datac (122:122:122) (145:145:145))
+        (PORT datad (357:357:357) (430:430:430))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (447:447:447))
+        (PORT datab (330:330:330) (401:401:401))
+        (PORT datad (299:299:299) (339:339:339))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (161:161:161) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (331:331:331) (402:402:402))
+        (PORT datad (299:299:299) (339:339:339))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (313:313:313) (379:379:379))
+        (PORT datab (373:373:373) (456:456:456))
+        (PORT datac (327:327:327) (393:393:393))
+        (PORT datad (167:167:167) (192:192:192))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (382:382:382) (464:464:464))
+        (PORT datad (96:96:96) (117:117:117))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (440:440:440))
+        (PORT datab (147:147:147) (202:202:202))
+        (PORT datac (135:135:135) (183:183:183))
+        (PORT datad (366:366:366) (445:445:445))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (386:386:386) (469:469:469))
+        (PORT datac (135:135:135) (183:183:183))
+        (PORT datad (101:101:101) (122:122:122))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (198:198:198))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (PORT datac (190:190:190) (244:244:244))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (446:446:446))
+        (PORT datab (153:153:153) (205:205:205))
+        (PORT datac (131:131:131) (173:173:173))
+        (PORT datad (317:317:317) (377:377:377))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (131:131:131) (179:179:179))
+        (PORT datac (118:118:118) (160:160:160))
+        (PORT datad (336:336:336) (406:406:406))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (768:768:768) (887:887:887))
+        (PORT datab (111:111:111) (143:143:143))
+        (PORT datac (196:196:196) (252:252:252))
+        (PORT datad (96:96:96) (116:116:116))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (446:446:446))
+        (PORT datab (378:378:378) (458:458:458))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (201:201:201))
+        (PORT datab (326:326:326) (397:397:397))
+        (PORT datac (293:293:293) (328:328:328))
+        (PORT datad (342:342:342) (419:419:419))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (90:90:90) (108:108:108))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (203:203:203))
+        (PORT datab (383:383:383) (465:465:465))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (161:161:161) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (198:198:198))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (369:369:369) (420:420:420))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (306:306:306) (345:345:345))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (467:467:467) (518:518:518))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (293:293:293) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (124:124:124) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (359:359:359))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (120:120:120) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (315:315:315) (381:381:381))
+        (PORT datab (223:223:223) (276:276:276))
+        (PORT datad (295:295:295) (350:350:350))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT asdata (505:505:505) (563:563:563))
+        (PORT ena (521:521:521) (555:555:555))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (131:131:131) (174:174:174))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (312:312:312) (373:373:373))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT asdata (295:295:295) (334:334:334))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (882:882:882) (887:887:887))
+        (PORT asdata (311:311:311) (359:359:359))
+        (PORT ena (496:496:496) (519:519:519))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (311:311:311) (371:371:371))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT asdata (294:294:294) (332:332:332))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (896:896:896))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (PORT datab (213:213:213) (265:265:265))
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (207:207:207) (254:254:254))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (380:380:380) (456:456:456))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (889:889:889))
+        (PORT asdata (296:296:296) (335:335:335))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (341:341:341) (418:418:418))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (889:889:889))
+        (PORT asdata (611:611:611) (682:682:682))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (889:889:889))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (412:412:412))
+        (PORT datab (452:452:452) (525:525:525))
+        (PORT datad (119:119:119) (157:157:157))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (136:136:136))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (160:160:160) (189:189:189))
+        (PORT datad (286:286:286) (333:333:333))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (412:412:412) (475:475:475))
+        (PORT datab (728:728:728) (828:828:828))
+        (PORT datac (93:93:93) (117:117:117))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (585:585:585) (699:699:699))
+        (PORT datab (383:383:383) (461:461:461))
+        (PORT datac (462:462:462) (539:539:539))
+        (PORT datad (314:314:314) (369:369:369))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (395:395:395))
+        (PORT datad (131:131:131) (170:170:170))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (490:490:490) (581:581:581))
+        (PORT datab (372:372:372) (444:444:444))
+        (PORT datac (148:148:148) (193:193:193))
+        (PORT datad (111:111:111) (131:131:131))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (160:160:160) (219:219:219))
+        (PORT datad (100:100:100) (122:122:122))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (164:164:164) (223:223:223))
+        (PORT datab (153:153:153) (206:206:206))
+        (PORT datad (96:96:96) (117:117:117))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (155:155:155) (208:208:208))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (196:196:196))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (499:499:499) (538:538:538))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (162:162:162) (221:221:221))
+        (PORT datab (153:153:153) (207:207:207))
+        (PORT datac (151:151:151) (196:196:196))
+        (PORT datad (138:138:138) (180:180:180))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (499:499:499) (538:538:538))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (201:201:201))
+        (PORT datab (369:369:369) (441:441:441))
+        (PORT datac (140:140:140) (187:187:187))
+        (PORT datad (469:469:469) (556:556:556))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (499:499:499) (538:538:538))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (131:131:131) (179:179:179))
+        (PORT datac (117:117:117) (158:158:158))
+        (PORT datad (187:187:187) (233:233:233))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (499:499:499) (538:538:538))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (138:138:138) (179:179:179))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (499:499:499) (538:538:538))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (248:248:248))
+        (PORT datab (155:155:155) (208:208:208))
+        (PORT datad (137:137:137) (177:177:177))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (887:887:887) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (745:745:745) (847:847:847))
+        (PORT ena (534:534:534) (577:577:577))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (152:152:152) (204:204:204))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT asdata (295:295:295) (334:334:334))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (483:483:483) (543:543:543))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (485:485:485) (535:535:535))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT asdata (363:363:363) (413:413:413))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (119:119:119) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (888:888:888) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (336:336:336) (400:400:400))
+        (PORT datab (342:342:342) (413:413:413))
+        (PORT datad (117:117:117) (154:154:154))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (726:726:726) (825:825:825))
+        (PORT datac (97:97:97) (121:121:121))
+        (PORT datad (94:94:94) (113:113:113))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1984:1984:1984) (2245:2245:2245))
+        (PORT datab (479:479:479) (552:552:552))
+        (PORT datac (498:498:498) (599:599:599))
+        (PORT datad (354:354:354) (409:409:409))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (538:538:538) (651:651:651))
+        (PORT datad (370:370:370) (441:441:441))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (540:540:540) (664:664:664))
+        (PORT datab (146:146:146) (201:201:201))
+        (PORT datac (179:179:179) (207:207:207))
+        (PORT datad (110:110:110) (129:129:129))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (516:516:516) (624:624:624))
+        (PORT datab (369:369:369) (433:433:433))
+        (PORT datac (458:458:458) (531:531:531))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (514:514:514) (622:622:622))
+        (PORT datab (368:368:368) (431:431:431))
+        (PORT datac (462:462:462) (534:534:534))
+        (PORT datad (130:130:130) (168:168:168))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (513:513:513) (620:620:620))
+        (PORT datab (367:367:367) (430:430:430))
+        (PORT datac (465:465:465) (538:538:538))
+        (PORT datad (130:130:130) (167:167:167))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (513:513:513) (621:621:621))
+        (PORT datab (367:367:367) (431:431:431))
+        (PORT datac (464:464:464) (537:537:537))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (512:512:512) (619:619:619))
+        (PORT datab (366:366:366) (430:430:430))
+        (PORT datac (466:466:466) (539:539:539))
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (860:860:860) (863:863:863))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (498:498:498) (579:579:579))
+        (PORT datab (513:513:513) (593:593:593))
+        (PORT datac (653:653:653) (775:775:775))
+        (PORT datad (361:361:361) (434:434:434))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (498:498:498) (580:580:580))
+        (PORT datab (512:512:512) (592:592:592))
+        (PORT datac (652:652:652) (774:774:774))
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (674:674:674) (805:805:805))
+        (PORT datab (513:513:513) (593:593:593))
+        (PORT datac (122:122:122) (165:165:165))
+        (PORT datad (473:473:473) (547:547:547))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (664:664:664) (787:787:787))
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (135:135:135) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (881:881:881) (886:886:886))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (615:615:615) (648:648:648))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (166:166:166))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (91:91:91) (109:109:109))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (889:889:889) (897:897:897))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (649:649:649) (691:691:691))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (162:162:162))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (386:386:386) (464:464:464))
+        (PORT datac (544:544:544) (658:658:658))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (538:538:538) (652:652:652))
+        (PORT datad (356:356:356) (421:421:421))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (552:552:552) (668:668:668))
+        (PORT datad (369:369:369) (439:439:439))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (550:550:550) (666:666:666))
+        (PORT datad (372:372:372) (445:445:445))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (654:654:654) (776:776:776))
+        (PORT datad (361:361:361) (434:434:434))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (661:661:661) (784:784:784))
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (PORT datac (651:651:651) (773:773:773))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (496:496:496) (576:576:576))
+        (PORT datab (514:514:514) (595:595:595))
+        (PORT datac (660:660:660) (782:782:782))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (649:649:649) (770:770:770))
+        (PORT datad (124:124:124) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (PORT datac (661:661:661) (783:783:783))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (140:140:140) (194:194:194))
+        (PORT datac (662:662:662) (786:786:786))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (754:754:754) (819:819:819))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (339:339:339) (412:412:412))
+        (PORT datac (550:550:550) (665:665:665))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (415:415:415))
+        (PORT datab (463:463:463) (533:533:533))
+        (PORT datac (542:542:542) (656:656:656))
+        (PORT datad (342:342:342) (392:392:392))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (548:548:548) (663:663:663))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (PORT datac (551:551:551) (667:667:667))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (189:189:189))
+        (PORT datab (463:463:463) (533:533:533))
+        (PORT datac (543:543:543) (657:657:657))
+        (PORT datad (342:342:342) (393:393:393))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (540:540:540) (654:654:654))
+        (PORT datad (118:118:118) (154:154:154))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (863:863:863) (867:867:867))
+        (PORT ena (636:636:636) (688:688:688))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (111:111:111) (145:145:145))
+        (PORT datab (142:142:142) (195:195:195))
+        (PORT datac (151:151:151) (209:209:209))
+        (PORT datad (344:344:344) (393:393:393))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|tx\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (105:105:105) (137:137:137))
+        (PORT datab (484:484:484) (567:567:567))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|tx)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (885:885:885) (890:890:890))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (869:869:869) (873:873:873))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf
new file mode 100644
index 0000000..8521a91
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf
@@ -0,0 +1,1312 @@
+vendor_name = ModelSim
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_tx.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_sd.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_rx.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_write.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_read.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_init.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_ctrl.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/uart_sd.cbx.xml
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/clk_gen_altpll.v
+source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dcfifo_uqf1.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_gray2bin_6ib.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_3p6.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_u6c.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/altsyncram_3011.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_909.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_b7d.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_a09.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_c7d.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_b09.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/cmpr_n76.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/cntr_old.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dcfifo_h0f1.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_2p6.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_v6c.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/altsyncram_4011.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_d7d.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_c09.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_e7d.tdf
+source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_d09.tdf
+design_name = uart_sd
+instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] , sd_ctrl_inst|sd_write_inst|cnt_data_num[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] , sd_ctrl_inst|sd_write_inst|cnt_data_num[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] , sd_ctrl_inst|sd_write_inst|cnt_data_num[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] , sd_ctrl_inst|sd_read_inst|cnt_data_num[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] , sd_ctrl_inst|sd_read_inst|cnt_data_num[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] , sd_ctrl_inst|sd_read_inst|cnt_data_num[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] , sd_ctrl_inst|sd_read_inst|cnt_data_num[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[0] , sd_ctrl_inst|sd_init_inst|cnt_wait[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 , sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 , sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 , sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[5] , uart_tx_inst|baud_cnt[5], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[2] , uart_tx_inst|baud_cnt[2], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[10] , uart_tx_inst|baud_cnt[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 , sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 , sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 , sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 , sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 , sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 , sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[2]~17 , uart_tx_inst|baud_cnt[2]~17, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[5]~23 , uart_tx_inst|baud_cnt[5]~23, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[10]~33 , uart_tx_inst|baud_cnt[10]~33, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[5] , data_rw_ctrl_inst|cnt_wait[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[5]~27 , data_rw_ctrl_inst|cnt_wait[5]~27, uart_sd, 1
+instance = comp, \uart_rx_inst|Add1~4 , uart_rx_inst|Add1~4, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[4] , uart_rx_inst|baud_cnt[4], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[10] , uart_rx_inst|baud_cnt[10], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[3] , data_rw_ctrl_inst|send_data_num[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[6] , data_rw_ctrl_inst|send_data_num[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[8] , data_rw_ctrl_inst|send_data_num[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[9] , data_rw_ctrl_inst|send_data_num[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[10] , data_rw_ctrl_inst|send_data_num[10], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[11] , data_rw_ctrl_inst|send_data_num[11], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[4]~21 , uart_rx_inst|baud_cnt[4]~21, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[10]~33 , uart_rx_inst|baud_cnt[10]~33, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[3]~18 , data_rw_ctrl_inst|send_data_num[3]~18, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[6]~24 , data_rw_ctrl_inst|send_data_num[6]~24, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[7]~26 , data_rw_ctrl_inst|send_data_num[7]~26, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[8]~28 , data_rw_ctrl_inst|send_data_num[8]~28, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[9]~30 , data_rw_ctrl_inst|send_data_num[9]~30, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[10]~32 , data_rw_ctrl_inst|send_data_num[10]~32, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[11]~34 , data_rw_ctrl_inst|send_data_num[11]~34, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[2] , sd_ctrl_inst|sd_read_inst|cnt_end[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~0 , sd_ctrl_inst|sd_read_inst|Selector1~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD55, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~0 , sd_ctrl_inst|sd_init_inst|Equal6~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|always4~0 , sd_ctrl_inst|sd_write_inst|always4~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|always4~1 , sd_ctrl_inst|sd_write_inst|always4~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~0 , sd_ctrl_inst|sd_write_inst|mosi~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~1 , sd_ctrl_inst|sd_write_inst|mosi~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux0~1 , sd_ctrl_inst|sd_write_inst|Mux0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~0 , sd_ctrl_inst|sd_write_inst|Mux1~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~1 , sd_ctrl_inst|sd_write_inst|Mux1~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~2 , sd_ctrl_inst|sd_write_inst|Mux1~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~3 , sd_ctrl_inst|sd_write_inst|Mux1~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~4 , sd_ctrl_inst|sd_write_inst|Mux1~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~5 , sd_ctrl_inst|sd_write_inst|Mux1~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~6 , sd_ctrl_inst|sd_write_inst|Mux1~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~7 , sd_ctrl_inst|sd_write_inst|Mux1~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~8 , sd_ctrl_inst|sd_write_inst|Mux1~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~6 , sd_ctrl_inst|sd_write_inst|mosi~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~7 , sd_ctrl_inst|sd_write_inst|mosi~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~1 , sd_ctrl_inst|sd_init_inst|Selector14~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~2 , sd_ctrl_inst|sd_init_inst|Selector14~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr14~0 , sd_ctrl_inst|sd_init_inst|WideOr14~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~3 , sd_ctrl_inst|sd_init_inst|Selector14~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~4 , sd_ctrl_inst|sd_init_inst|Selector14~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~5 , sd_ctrl_inst|sd_init_inst|Selector14~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~6 , sd_ctrl_inst|sd_init_inst|Selector14~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~7 , sd_ctrl_inst|sd_init_inst|Selector14~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr12~0 , sd_ctrl_inst|sd_init_inst|WideOr12~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~8 , sd_ctrl_inst|sd_init_inst|Selector14~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~9 , sd_ctrl_inst|sd_init_inst|Selector14~9, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~10 , sd_ctrl_inst|sd_init_inst|Selector14~10, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[2] , uart_tx_inst|bit_cnt[2], uart_sd, 1
+instance = comp, \uart_tx_inst|always0~0 , uart_tx_inst|always0~0, uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~1 , uart_tx_inst|Mux0~1, uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~2 , uart_tx_inst|Mux0~2, uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~3 , uart_tx_inst|Mux0~3, uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~4 , uart_tx_inst|Mux0~4, uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~5 , uart_tx_inst|Mux0~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~0 , sd_ctrl_inst|sd_read_inst|cnt_end~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|always3~1 , sd_ctrl_inst|sd_read_inst|always3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|always3~2 , sd_ctrl_inst|sd_read_inst|always3~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~0 , sd_ctrl_inst|sd_init_inst|Equal1~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector8~0 , sd_ctrl_inst|sd_init_inst|Selector8~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector0~0 , sd_ctrl_inst|sd_init_inst|Selector0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal3~0 , sd_ctrl_inst|sd_init_inst|Equal3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~0 , sd_ctrl_inst|sd_init_inst|Selector6~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~1 , sd_ctrl_inst|sd_init_inst|Selector6~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~2 , sd_ctrl_inst|sd_init_inst|Selector6~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~3 , sd_ctrl_inst|sd_init_inst|Selector6~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~1 , sd_ctrl_inst|sd_read_inst|Selector1~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~1 , sd_ctrl_inst|sd_read_inst|Equal3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~1 , sd_ctrl_inst|sd_write_inst|Equal3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~2 , sd_ctrl_inst|sd_write_inst|Equal3~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK , sd_ctrl_inst|sd_write_inst|state.CMD24_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector2~0 , sd_ctrl_inst|sd_write_inst|Selector2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~0 , sd_ctrl_inst|sd_write_inst|Add3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[1] , uart_rx_inst|po_data[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[5] , uart_rx_inst|po_data[5], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[6] , uart_rx_inst|po_data[6], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[2] , uart_rx_inst|po_data[2], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[7] , uart_rx_inst|po_data[7], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[3] , uart_rx_inst|po_data[3], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[0] , uart_rx_inst|po_data[0], uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[4] , uart_rx_inst|po_data[4], uart_sd, 1
+instance = comp, \uart_tx_inst|work_en , uart_tx_inst|work_en, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3, uart_sd, 1
+instance = comp, \uart_tx_inst|Add1~1 , uart_tx_inst|Add1~1, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[2]~3 , uart_tx_inst|bit_cnt[2]~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[3] , sd_ctrl_inst|sd_read_inst|byte_head[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[2] , sd_ctrl_inst|sd_read_inst|byte_head[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[1] , sd_ctrl_inst|sd_read_inst|byte_head[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[0] , sd_ctrl_inst|sd_read_inst|byte_head[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~1 , sd_ctrl_inst|sd_read_inst|Equal6~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector3~0 , sd_ctrl_inst|sd_write_inst|Selector3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector3~1 , sd_ctrl_inst|sd_write_inst|Selector3~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[1] , uart_rx_inst|rx_data[1], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[5] , uart_rx_inst|rx_data[5], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[6] , uart_rx_inst|rx_data[6], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[2] , uart_rx_inst|rx_data[2], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[7] , uart_rx_inst|rx_data[7], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[3] , uart_rx_inst|rx_data[3], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[0] , uart_rx_inst|rx_data[0], uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[4] , uart_rx_inst|rx_data[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|tx_flag , data_rw_ctrl_inst|tx_flag, uart_sd, 1
+instance = comp, \uart_tx_inst|work_en~0 , uart_tx_inst|work_en~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] , sd_ctrl_inst|sd_read_inst|rd_data_reg[12], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] , sd_ctrl_inst|sd_read_inst|rd_data_reg[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] , sd_ctrl_inst|sd_read_inst|rd_data_reg[14], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] , sd_ctrl_inst|sd_read_inst|rd_data_reg[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~4 , sd_ctrl_inst|sd_read_inst|byte_head~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~5 , sd_ctrl_inst|sd_read_inst|byte_head~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~6 , sd_ctrl_inst|sd_read_inst|byte_head~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~7 , sd_ctrl_inst|sd_read_inst|byte_head~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~0 , sd_ctrl_inst|sd_write_inst|ack_en~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~1 , sd_ctrl_inst|sd_write_inst|ack_en~1, uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt[2] , uart_rx_inst|bit_cnt[2], uart_sd, 1
+instance = comp, \uart_rx_inst|always8~0 , uart_rx_inst|always8~0, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_reg3 , uart_rx_inst|rx_reg3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 , sd_ctrl_inst|sd_read_inst|rd_data_reg~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 , sd_ctrl_inst|sd_read_inst|rd_data_reg~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 , sd_ctrl_inst|sd_read_inst|rd_data_reg~9, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 , sd_ctrl_inst|sd_read_inst|rd_data_reg~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~2 , sd_ctrl_inst|sd_read_inst|byte_head_en~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~3 , sd_ctrl_inst|sd_read_inst|byte_head_en~3, uart_sd, 1
+instance = comp, \uart_rx_inst|Equal2~0 , uart_rx_inst|Equal2~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_reg2 , uart_rx_inst|rx_reg2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|always3~2 , data_rw_ctrl_inst|always3~2, uart_sd, 1
+instance = comp, \uart_rx_inst|Equal1~2 , uart_rx_inst|Equal1~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_reg1 , uart_rx_inst|rx_reg1, uart_sd, 1
+instance = comp, \uart_rx_inst|start_nedge , uart_rx_inst|start_nedge, uart_sd, 1
+instance = comp, \uart_rx_inst|always3~0 , uart_rx_inst|always3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[7]~0 , uart_rx_inst|rx_data[7]~0, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_reg1~0 , uart_rx_inst|rx_reg1~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell, uart_sd, 1
+instance = comp, \rx~input , rx~input, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|tx_flag~feeder , data_rw_ctrl_inst|tx_flag~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[1]~feeder , uart_rx_inst|po_data[1]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[0]~feeder , uart_rx_inst|rx_data[0]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[5]~feeder , uart_rx_inst|po_data[5]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[4]~feeder , uart_rx_inst|rx_data[4]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[6]~feeder , uart_rx_inst|po_data[6]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[5]~feeder , uart_rx_inst|rx_data[5]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[7]~feeder , uart_rx_inst|po_data[7]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[6]~feeder , uart_rx_inst|rx_data[6]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[3]~feeder , uart_rx_inst|po_data[3]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_data[2]~feeder , uart_rx_inst|rx_data[2]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|po_data[0]~feeder , uart_rx_inst|po_data[0]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_reg2~feeder , uart_rx_inst|rx_reg2~feeder, uart_sd, 1
+instance = comp, \sd_clk~output , sd_clk~output, uart_sd, 1
+instance = comp, \sd_cs_n~output , sd_cs_n~output, uart_sd, 1
+instance = comp, \sd_mosi~output , sd_mosi~output, uart_sd, 1
+instance = comp, \tx~output , tx~output, uart_sd, 1
+instance = comp, \sys_clk~input , sys_clk~input, uart_sd, 1
+instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 , sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12, uart_sd, 1
+instance = comp, \sys_rst_n~input , sys_rst_n~input, uart_sd, 1
+instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, uart_sd, 1
+instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, uart_sd, 1
+instance = comp, \rst_n~0 , rst_n~0, uart_sd, 1
+instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8, uart_sd, 1
+instance = comp, \sd_miso~input , sd_miso~input, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|miso_dly , sd_ctrl_inst|sd_init_inst|miso_dly, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~0 , sd_ctrl_inst|sd_read_inst|ack_en~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~1 , sd_ctrl_inst|sd_read_inst|ack_en~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal0~1 , sd_ctrl_inst|sd_read_inst|Equal0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~2 , sd_ctrl_inst|sd_read_inst|ack_en~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en , sd_ctrl_inst|sd_read_inst|ack_en, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal0~0 , sd_ctrl_inst|sd_read_inst|Equal0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 , sd_ctrl_inst|sd_read_inst|ack_data[7]~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[0] , sd_ctrl_inst|sd_read_inst|ack_data[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[1] , sd_ctrl_inst|sd_read_inst|ack_data[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[2] , sd_ctrl_inst|sd_read_inst|ack_data[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[3] , sd_ctrl_inst|sd_read_inst|ack_data[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[4] , sd_ctrl_inst|sd_read_inst|ack_data[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[5] , sd_ctrl_inst|sd_read_inst|ack_data[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[6] , sd_ctrl_inst|sd_read_inst|ack_data[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[7] , sd_ctrl_inst|sd_read_inst|ack_data[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~0 , sd_ctrl_inst|sd_read_inst|Equal3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~2 , sd_ctrl_inst|sd_read_inst|Equal3~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en~0 , sd_ctrl_inst|sd_init_inst|ack_en~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en~1 , sd_ctrl_inst|sd_init_inst|ack_en~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en , sd_ctrl_inst|sd_init_inst|ack_en, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~1 , sd_ctrl_inst|sd_init_inst|Equal1~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~2 , sd_ctrl_inst|sd_init_inst|Equal1~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 , sd_ctrl_inst|sd_init_inst|ack_data[39]~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 , sd_ctrl_inst|sd_init_inst|ack_data[39]~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[0] , sd_ctrl_inst|sd_init_inst|ack_data[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[1] , sd_ctrl_inst|sd_init_inst|ack_data[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[2] , sd_ctrl_inst|sd_init_inst|ack_data[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[3] , sd_ctrl_inst|sd_init_inst|ack_data[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[4] , sd_ctrl_inst|sd_init_inst|ack_data[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[5] , sd_ctrl_inst|sd_init_inst|ack_data[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[6] , sd_ctrl_inst|sd_init_inst|ack_data[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[7] , sd_ctrl_inst|sd_init_inst|ack_data[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[8] , sd_ctrl_inst|sd_init_inst|ack_data[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[9] , sd_ctrl_inst|sd_init_inst|ack_data[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[10] , sd_ctrl_inst|sd_init_inst|ack_data[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[11] , sd_ctrl_inst|sd_init_inst|ack_data[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[12] , sd_ctrl_inst|sd_init_inst|ack_data[12], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[13] , sd_ctrl_inst|sd_init_inst|ack_data[13], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[14] , sd_ctrl_inst|sd_init_inst|ack_data[14], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[15] , sd_ctrl_inst|sd_init_inst|ack_data[15], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[16] , sd_ctrl_inst|sd_init_inst|ack_data[16], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[17] , sd_ctrl_inst|sd_init_inst|ack_data[17], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[18] , sd_ctrl_inst|sd_init_inst|ack_data[18], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[19] , sd_ctrl_inst|sd_init_inst|ack_data[19], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[20] , sd_ctrl_inst|sd_init_inst|ack_data[20], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[21] , sd_ctrl_inst|sd_init_inst|ack_data[21], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[22] , sd_ctrl_inst|sd_init_inst|ack_data[22], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[23] , sd_ctrl_inst|sd_init_inst|ack_data[23], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[24] , sd_ctrl_inst|sd_init_inst|ack_data[24], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[25] , sd_ctrl_inst|sd_init_inst|ack_data[25], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[26] , sd_ctrl_inst|sd_init_inst|ack_data[26], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[27] , sd_ctrl_inst|sd_init_inst|ack_data[27], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[28] , sd_ctrl_inst|sd_init_inst|ack_data[28], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[29] , sd_ctrl_inst|sd_init_inst|ack_data[29], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[30] , sd_ctrl_inst|sd_init_inst|ack_data[30], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[31] , sd_ctrl_inst|sd_init_inst|ack_data[31], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[32] , sd_ctrl_inst|sd_init_inst|ack_data[32], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[33] , sd_ctrl_inst|sd_init_inst|ack_data[33], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[34] , sd_ctrl_inst|sd_init_inst|ack_data[34], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[35] , sd_ctrl_inst|sd_init_inst|ack_data[35], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~1 , sd_ctrl_inst|sd_init_inst|Equal2~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[36] , sd_ctrl_inst|sd_init_inst|ack_data[36], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[37] , sd_ctrl_inst|sd_init_inst|ack_data[37], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[38] , sd_ctrl_inst|sd_init_inst|ack_data[38], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39] , sd_ctrl_inst|sd_init_inst|ack_data[39], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~0 , sd_ctrl_inst|sd_init_inst|Equal2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~2 , sd_ctrl_inst|sd_init_inst|Equal2~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector0~1 , sd_ctrl_inst|sd_init_inst|Selector0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 , sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 , sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 , sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 , sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[4] , sd_ctrl_inst|sd_init_inst|cnt_wait[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 , sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[5] , sd_ctrl_inst|sd_init_inst|cnt_wait[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 , sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 , sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[7] , sd_ctrl_inst|sd_init_inst|cnt_wait[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 , sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[8] , sd_ctrl_inst|sd_init_inst|cnt_wait[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[6] , sd_ctrl_inst|sd_init_inst|cnt_wait[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~1 , sd_ctrl_inst|sd_init_inst|Equal0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~2 , sd_ctrl_inst|sd_init_inst|Equal0~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[2] , sd_ctrl_inst|sd_init_inst|cnt_wait[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[3] , sd_ctrl_inst|sd_init_inst|cnt_wait[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[1] , sd_ctrl_inst|sd_init_inst|cnt_wait[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~0 , sd_ctrl_inst|sd_init_inst|Equal0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.IDLE~0 , sd_ctrl_inst|sd_init_inst|state.IDLE~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.IDLE , sd_ctrl_inst|sd_init_inst|state.IDLE, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 , sd_ctrl_inst|sd_init_inst|state.INIT_END~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.INIT_END , sd_ctrl_inst|sd_init_inst|state.INIT_END, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr18 , sd_ctrl_inst|sd_init_inst|WideOr18, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~1 , sd_ctrl_inst|sd_init_inst|Equal5~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~0 , sd_ctrl_inst|sd_init_inst|Equal5~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~2 , sd_ctrl_inst|sd_init_inst|Equal5~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector2~0 , sd_ctrl_inst|sd_init_inst|Selector2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK , sd_ctrl_inst|sd_init_inst|state.CMD0_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector1~0 , sd_ctrl_inst|sd_init_inst|Selector1~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector1~1 , sd_ctrl_inst|sd_init_inst|Selector1~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector5~0 , sd_ctrl_inst|sd_init_inst|Selector5~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK , sd_ctrl_inst|sd_init_inst|state.CMD8_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector4~0 , sd_ctrl_inst|sd_init_inst|Selector4~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK , sd_ctrl_inst|sd_init_inst|state.CMD55_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector7~0 , sd_ctrl_inst|sd_init_inst|Selector7~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK , sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~0 , sd_ctrl_inst|sd_init_inst|Selector14~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector3~0 , sd_ctrl_inst|sd_init_inst|Selector3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector3~1 , sd_ctrl_inst|sd_init_inst|Selector3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 , sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~0 , sd_ctrl_inst|sd_init_inst|Selector15~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~1 , sd_ctrl_inst|sd_init_inst|Selector15~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~2 , sd_ctrl_inst|sd_init_inst|Selector15~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|init_end , sd_ctrl_inst|sd_init_inst|init_end, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~2 , sd_ctrl_inst|sd_read_inst|Selector1~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~3 , sd_ctrl_inst|sd_read_inst|Selector1~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 , sd_ctrl_inst|sd_read_inst|state.SEND_CMD17, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal2~1 , sd_ctrl_inst|sd_read_inst|Equal2~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal2~0 , sd_ctrl_inst|sd_read_inst|Equal2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector3~0 , sd_ctrl_inst|sd_read_inst|Selector3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector3~1 , sd_ctrl_inst|sd_read_inst|Selector3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK , sd_ctrl_inst|sd_read_inst|state.CMD17_ACK, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector2~0 , sd_ctrl_inst|sd_read_inst|Selector2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector2~1 , sd_ctrl_inst|sd_read_inst|Selector2~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|state.RD_DATA , sd_ctrl_inst|sd_read_inst|state.RD_DATA, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~0 , sd_ctrl_inst|sd_read_inst|byte_head_en~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 , sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] , sd_ctrl_inst|sd_read_inst|cnt_data_num[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 , sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] , sd_ctrl_inst|sd_read_inst|cnt_data_num[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|always3~0 , sd_ctrl_inst|sd_read_inst|always3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~1 , sd_ctrl_inst|sd_read_inst|byte_head_en~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Add3~0 , sd_ctrl_inst|sd_read_inst|Add3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal9~0 , sd_ctrl_inst|sd_read_inst|Equal9~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~11 , sd_ctrl_inst|sd_read_inst|byte_head~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[12] , sd_ctrl_inst|sd_read_inst|byte_head[12], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~10 , sd_ctrl_inst|sd_read_inst|byte_head~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[13] , sd_ctrl_inst|sd_read_inst|byte_head[13], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~9 , sd_ctrl_inst|sd_read_inst|byte_head~9, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[14] , sd_ctrl_inst|sd_read_inst|byte_head[14], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~8 , sd_ctrl_inst|sd_read_inst|byte_head~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[15] , sd_ctrl_inst|sd_read_inst|byte_head[15], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~2 , sd_ctrl_inst|sd_read_inst|Equal6~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~14 , sd_ctrl_inst|sd_read_inst|byte_head~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[9] , sd_ctrl_inst|sd_read_inst|byte_head[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~13 , sd_ctrl_inst|sd_read_inst|byte_head~13, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[10] , sd_ctrl_inst|sd_read_inst|byte_head[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~12 , sd_ctrl_inst|sd_read_inst|byte_head~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[11] , sd_ctrl_inst|sd_read_inst|byte_head[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~15 , sd_ctrl_inst|sd_read_inst|byte_head~15, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[8] , sd_ctrl_inst|sd_read_inst|byte_head[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~3 , sd_ctrl_inst|sd_read_inst|Equal6~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~4 , sd_ctrl_inst|sd_read_inst|Equal6~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~4 , sd_ctrl_inst|sd_read_inst|byte_head_en~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en , sd_ctrl_inst|sd_read_inst|byte_head_en, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~1 , sd_ctrl_inst|sd_read_inst|byte_head~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[6] , sd_ctrl_inst|sd_read_inst|byte_head[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~0 , sd_ctrl_inst|sd_read_inst|byte_head~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[7] , sd_ctrl_inst|sd_read_inst|byte_head[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~3 , sd_ctrl_inst|sd_read_inst|byte_head~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[4] , sd_ctrl_inst|sd_read_inst|byte_head[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~2 , sd_ctrl_inst|sd_read_inst|byte_head~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[5] , sd_ctrl_inst|sd_read_inst|byte_head[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~0 , sd_ctrl_inst|sd_read_inst|Equal6~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] , sd_ctrl_inst|sd_read_inst|cnt_data_num[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] , sd_ctrl_inst|sd_read_inst|cnt_data_num[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 , sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] , sd_ctrl_inst|sd_read_inst|cnt_data_num[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 , sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] , sd_ctrl_inst|sd_read_inst|cnt_data_num[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 , sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] , sd_ctrl_inst|sd_read_inst|cnt_data_num[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] , sd_ctrl_inst|sd_read_inst|cnt_data_num[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|always3~3 , sd_ctrl_inst|sd_read_inst|always3~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|always3~4 , sd_ctrl_inst|sd_read_inst|always3~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector4~0 , sd_ctrl_inst|sd_read_inst|Selector4~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|state.RD_END , sd_ctrl_inst|sd_read_inst|state.RD_END, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~1 , sd_ctrl_inst|sd_read_inst|cnt_end~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[0] , sd_ctrl_inst|sd_read_inst|cnt_end[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~2 , sd_ctrl_inst|sd_read_inst|cnt_end~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[1] , sd_ctrl_inst|sd_read_inst|cnt_end[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector0~0 , sd_ctrl_inst|sd_read_inst|Selector0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|Selector0~1 , sd_ctrl_inst|sd_read_inst|Selector0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|state.IDLE , sd_ctrl_inst|sd_read_inst|state.IDLE, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 , sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal1~0 , sd_ctrl_inst|sd_write_inst|Equal1~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal1~1 , sd_ctrl_inst|sd_write_inst|Equal1~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~2 , sd_ctrl_inst|sd_write_inst|ack_en~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en , sd_ctrl_inst|sd_write_inst|ack_en, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 , sd_ctrl_inst|sd_write_inst|ack_data[7]~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[0] , sd_ctrl_inst|sd_write_inst|ack_data[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[1] , sd_ctrl_inst|sd_write_inst|ack_data[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[2] , sd_ctrl_inst|sd_write_inst|ack_data[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[3] , sd_ctrl_inst|sd_write_inst|ack_data[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~1 , sd_ctrl_inst|sd_write_inst|Equal4~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[4] , sd_ctrl_inst|sd_write_inst|ack_data[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[5] , sd_ctrl_inst|sd_write_inst|ack_data[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[6] , sd_ctrl_inst|sd_write_inst|ack_data[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[7] , sd_ctrl_inst|sd_write_inst|ack_data[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~0 , sd_ctrl_inst|sd_write_inst|Equal4~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~2 , sd_ctrl_inst|sd_write_inst|Equal4~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector2~1 , sd_ctrl_inst|sd_write_inst|Selector2~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_DATA , sd_ctrl_inst|sd_write_inst|state.WR_DATA, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 , sd_ctrl_inst|sd_write_inst|cnt_data_bit~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~2 , sd_ctrl_inst|sd_write_inst|Add3~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~1 , sd_ctrl_inst|sd_write_inst|Add3~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 , sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] , sd_ctrl_inst|sd_write_inst|cnt_data_num[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 , sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] , sd_ctrl_inst|sd_write_inst|cnt_data_num[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 , sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] , sd_ctrl_inst|sd_write_inst|cnt_data_num[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 , sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] , sd_ctrl_inst|sd_write_inst|cnt_data_num[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 , sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] , sd_ctrl_inst|sd_write_inst|cnt_data_num[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 , sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] , sd_ctrl_inst|sd_write_inst|cnt_data_num[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 , sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 , sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] , sd_ctrl_inst|sd_write_inst|cnt_data_num[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 , sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] , sd_ctrl_inst|sd_write_inst|cnt_data_num[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] , sd_ctrl_inst|sd_write_inst|cnt_data_num[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|always4~2 , sd_ctrl_inst|sd_write_inst|always4~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|always4~3 , sd_ctrl_inst|sd_write_inst|always4~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector4~0 , sd_ctrl_inst|sd_write_inst|Selector4~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_BUSY , sd_ctrl_inst|sd_write_inst|state.WR_BUSY, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~8 , sd_ctrl_inst|sd_write_inst|busy_data~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[0] , sd_ctrl_inst|sd_write_inst|busy_data[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~7 , sd_ctrl_inst|sd_write_inst|busy_data~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[1] , sd_ctrl_inst|sd_write_inst|busy_data[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~6 , sd_ctrl_inst|sd_write_inst|busy_data~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[2] , sd_ctrl_inst|sd_write_inst|busy_data[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~5 , sd_ctrl_inst|sd_write_inst|busy_data~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[3] , sd_ctrl_inst|sd_write_inst|busy_data[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~1 , sd_ctrl_inst|sd_write_inst|Equal6~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~4 , sd_ctrl_inst|sd_write_inst|busy_data~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[4] , sd_ctrl_inst|sd_write_inst|busy_data[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~3 , sd_ctrl_inst|sd_write_inst|busy_data~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[5] , sd_ctrl_inst|sd_write_inst|busy_data[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~2 , sd_ctrl_inst|sd_write_inst|busy_data~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[6] , sd_ctrl_inst|sd_write_inst|busy_data[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~1 , sd_ctrl_inst|sd_write_inst|busy_data~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[7] , sd_ctrl_inst|sd_write_inst|busy_data[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~0 , sd_ctrl_inst|sd_write_inst|Equal6~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~2 , sd_ctrl_inst|sd_write_inst|Equal6~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector5~0 , sd_ctrl_inst|sd_write_inst|Selector5~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_END , sd_ctrl_inst|sd_write_inst|state.WR_END, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~2 , sd_ctrl_inst|sd_write_inst|cnt_end~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[1] , sd_ctrl_inst|sd_write_inst|cnt_end[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~1 , sd_ctrl_inst|sd_write_inst|cnt_end~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[0] , sd_ctrl_inst|sd_write_inst|cnt_end[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~0 , sd_ctrl_inst|sd_write_inst|cnt_end~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[2] , sd_ctrl_inst|sd_write_inst|cnt_end[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector0~0 , sd_ctrl_inst|sd_write_inst|Selector0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cs_n~0 , sd_ctrl_inst|sd_write_inst|cs_n~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cs_n , sd_ctrl_inst|sd_write_inst|cs_n, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector0~1 , sd_ctrl_inst|sd_write_inst|Selector0~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.IDLE , sd_ctrl_inst|sd_write_inst|state.IDLE, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|wr_busy_dly~feeder , data_rw_ctrl_inst|wr_busy_dly~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|wr_busy_dly , data_rw_ctrl_inst|wr_busy_dly, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|wr_busy_fall~0 , data_rw_ctrl_inst|wr_busy_fall~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|rd_en , data_rw_ctrl_inst|rd_en, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cs_n~2 , sd_ctrl_inst|sd_read_inst|cs_n~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cs_n , sd_ctrl_inst|sd_read_inst|cs_n, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_cs_n~0 , sd_ctrl_inst|sd_cs_n~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~1 , sd_ctrl_inst|sd_init_inst|Selector13~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~1 , sd_ctrl_inst|sd_init_inst|Equal6~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~0 , sd_ctrl_inst|sd_init_inst|Selector13~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~2 , sd_ctrl_inst|sd_init_inst|Equal6~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~2 , sd_ctrl_inst|sd_init_inst|Selector13~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~3 , sd_ctrl_inst|sd_init_inst|Selector13~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|cs_n , sd_ctrl_inst|sd_init_inst|cs_n, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_cs_n~1 , sd_ctrl_inst|sd_cs_n~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~11 , sd_ctrl_inst|sd_init_inst|Selector14~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_init_inst|mosi , sd_ctrl_inst|sd_init_inst|mosi, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~0 , sd_ctrl_inst|sd_read_inst|mosi~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~1 , sd_ctrl_inst|sd_read_inst|mosi~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~2 , sd_ctrl_inst|sd_read_inst|mosi~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|mosi , sd_ctrl_inst|sd_read_inst|mosi, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0, uart_sd, 1
+instance = comp, \uart_rx_inst|Add1~0 , uart_rx_inst|Add1~0, uart_sd, 1
+instance = comp, \uart_rx_inst|Add1~2 , uart_rx_inst|Add1~2, uart_sd, 1
+instance = comp, \uart_rx_inst|Add1~6 , uart_rx_inst|Add1~6, uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt~0 , uart_rx_inst|bit_cnt~0, uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt[3] , uart_rx_inst|bit_cnt[3], uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt~1 , uart_rx_inst|bit_cnt~1, uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt[0] , uart_rx_inst|bit_cnt[0], uart_sd, 1
+instance = comp, \uart_rx_inst|bit_cnt[1] , uart_rx_inst|bit_cnt[1], uart_sd, 1
+instance = comp, \uart_rx_inst|always4~0 , uart_rx_inst|always4~0, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[0]~13 , uart_rx_inst|baud_cnt[0]~13, uart_sd, 1
+instance = comp, \uart_rx_inst|Equal1~0 , uart_rx_inst|Equal1~0, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[5]~23 , uart_rx_inst|baud_cnt[5]~23, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[5] , uart_rx_inst|baud_cnt[5], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[2]~17 , uart_rx_inst|baud_cnt[2]~17, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[2] , uart_rx_inst|baud_cnt[2], uart_sd, 1
+instance = comp, \uart_rx_inst|Equal1~1 , uart_rx_inst|Equal1~1, uart_sd, 1
+instance = comp, \uart_rx_inst|Equal1~3 , uart_rx_inst|Equal1~3, uart_sd, 1
+instance = comp, \uart_rx_inst|work_en~0 , uart_rx_inst|work_en~0, uart_sd, 1
+instance = comp, \uart_rx_inst|work_en , uart_rx_inst|work_en, uart_sd, 1
+instance = comp, \uart_rx_inst|always5~0 , uart_rx_inst|always5~0, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[0] , uart_rx_inst|baud_cnt[0], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[1]~15 , uart_rx_inst|baud_cnt[1]~15, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[1] , uart_rx_inst|baud_cnt[1], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[3]~19 , uart_rx_inst|baud_cnt[3]~19, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[3] , uart_rx_inst|baud_cnt[3], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[6]~25 , uart_rx_inst|baud_cnt[6]~25, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[6] , uart_rx_inst|baud_cnt[6], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[7]~27 , uart_rx_inst|baud_cnt[7]~27, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[7] , uart_rx_inst|baud_cnt[7], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[8]~29 , uart_rx_inst|baud_cnt[8]~29, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[8] , uart_rx_inst|baud_cnt[8], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[9]~31 , uart_rx_inst|baud_cnt[9]~31, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[9] , uart_rx_inst|baud_cnt[9], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[11]~35 , uart_rx_inst|baud_cnt[11]~35, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[11] , uart_rx_inst|baud_cnt[11], uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[12]~37 , uart_rx_inst|baud_cnt[12]~37, uart_sd, 1
+instance = comp, \uart_rx_inst|baud_cnt[12] , uart_rx_inst|baud_cnt[12], uart_sd, 1
+instance = comp, \uart_rx_inst|Equal2~1 , uart_rx_inst|Equal2~1, uart_sd, 1
+instance = comp, \uart_rx_inst|Equal2~2 , uart_rx_inst|Equal2~2, uart_sd, 1
+instance = comp, \uart_rx_inst|bit_flag , uart_rx_inst|bit_flag, uart_sd, 1
+instance = comp, \uart_rx_inst|always4~1 , uart_rx_inst|always4~1, uart_sd, 1
+instance = comp, \uart_rx_inst|rx_flag , uart_rx_inst|rx_flag, uart_sd, 1
+instance = comp, \uart_rx_inst|po_flag , uart_rx_inst|po_flag, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|comb~1 , sd_ctrl_inst|comb~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|comb~0 , sd_ctrl_inst|comb~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|comb~2 , sd_ctrl_inst|comb~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector1~2 , sd_ctrl_inst|sd_write_inst|Selector1~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Selector1~3 , sd_ctrl_inst|sd_write_inst|Selector1~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 , sd_ctrl_inst|sd_write_inst|state.SEND_CMD24, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Mux0~0 , sd_ctrl_inst|sd_write_inst|Mux0~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~2 , sd_ctrl_inst|sd_write_inst|mosi~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~0 , sd_ctrl_inst|sd_write_inst|Equal3~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~3 , sd_ctrl_inst|sd_write_inst|mosi~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~4 , sd_ctrl_inst|sd_write_inst|mosi~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~5 , sd_ctrl_inst|sd_write_inst|mosi~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~8 , sd_ctrl_inst|sd_write_inst|mosi~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_write_inst|mosi , sd_ctrl_inst|sd_write_inst|mosi, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_mosi~0 , sd_ctrl_inst|sd_mosi~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_mosi~1 , sd_ctrl_inst|sd_mosi~1, uart_sd, 1
+instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[0]~13 , uart_tx_inst|baud_cnt[0]~13, uart_sd, 1
+instance = comp, \uart_tx_inst|Equal1~0 , uart_tx_inst|Equal1~0, uart_sd, 1
+instance = comp, \uart_tx_inst|Equal1~1 , uart_tx_inst|Equal1~1, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[4]~21 , uart_tx_inst|baud_cnt[4]~21, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[4] , uart_tx_inst|baud_cnt[4], uart_sd, 1
+instance = comp, \uart_tx_inst|Equal1~2 , uart_tx_inst|Equal1~2, uart_sd, 1
+instance = comp, \uart_tx_inst|Equal1~3 , uart_tx_inst|Equal1~3, uart_sd, 1
+instance = comp, \uart_tx_inst|always1~0 , uart_tx_inst|always1~0, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[0] , uart_tx_inst|baud_cnt[0], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[1]~15 , uart_tx_inst|baud_cnt[1]~15, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[1] , uart_tx_inst|baud_cnt[1], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[3]~19 , uart_tx_inst|baud_cnt[3]~19, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[3] , uart_tx_inst|baud_cnt[3], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[6]~25 , uart_tx_inst|baud_cnt[6]~25, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[6] , uart_tx_inst|baud_cnt[6], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[7]~27 , uart_tx_inst|baud_cnt[7]~27, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[7] , uart_tx_inst|baud_cnt[7], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[8]~29 , uart_tx_inst|baud_cnt[8]~29, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[8] , uart_tx_inst|baud_cnt[8], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[9]~31 , uart_tx_inst|baud_cnt[9]~31, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[9] , uart_tx_inst|baud_cnt[9], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[11]~35 , uart_tx_inst|baud_cnt[11]~35, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[11] , uart_tx_inst|baud_cnt[11], uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[12]~37 , uart_tx_inst|baud_cnt[12]~37, uart_sd, 1
+instance = comp, \uart_tx_inst|baud_cnt[12] , uart_tx_inst|baud_cnt[12], uart_sd, 1
+instance = comp, \uart_tx_inst|Equal2~0 , uart_tx_inst|Equal2~0, uart_sd, 1
+instance = comp, \uart_tx_inst|Equal2~1 , uart_tx_inst|Equal2~1, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_flag , uart_tx_inst|bit_flag, uart_sd, 1
+instance = comp, \uart_tx_inst|always3~0 , uart_tx_inst|always3~0, uart_sd, 1
+instance = comp, \uart_tx_inst|always0~1 , uart_tx_inst|always0~1, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[0]~5 , uart_tx_inst|bit_cnt[0]~5, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[0] , uart_tx_inst|bit_cnt[0], uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[1]~4 , uart_tx_inst|bit_cnt[1]~4, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[1] , uart_tx_inst|bit_cnt[1], uart_sd, 1
+instance = comp, \uart_tx_inst|Add1~0 , uart_tx_inst|Add1~0, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[3]~2 , uart_tx_inst|bit_cnt[3]~2, uart_sd, 1
+instance = comp, \uart_tx_inst|bit_cnt[3] , uart_tx_inst|bit_cnt[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[0]~16 , data_rw_ctrl_inst|cnt_wait[0]~16, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[3]~22 , data_rw_ctrl_inst|cnt_wait[3]~22, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[4]~24 , data_rw_ctrl_inst|cnt_wait[4]~24, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[4] , data_rw_ctrl_inst|cnt_wait[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal3~0 , data_rw_ctrl_inst|Equal3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|rd_busy_dly , data_rw_ctrl_inst|rd_busy_dly, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[0]~12 , data_rw_ctrl_inst|send_data_num[0]~12, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[0] , data_rw_ctrl_inst|send_data_num[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[1]~14 , data_rw_ctrl_inst|send_data_num[1]~14, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[1] , data_rw_ctrl_inst|send_data_num[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[2]~16 , data_rw_ctrl_inst|send_data_num[2]~16, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[2] , data_rw_ctrl_inst|send_data_num[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|always3~0 , data_rw_ctrl_inst|always3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[4]~20 , data_rw_ctrl_inst|send_data_num[4]~20, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[4] , data_rw_ctrl_inst|send_data_num[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[5]~22 , data_rw_ctrl_inst|send_data_num[5]~22, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[7] , data_rw_ctrl_inst|send_data_num[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_num[5] , data_rw_ctrl_inst|send_data_num[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|always3~1 , data_rw_ctrl_inst|always3~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|always3~3 , data_rw_ctrl_inst|always3~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_en~0 , data_rw_ctrl_inst|send_data_en~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|send_data_en , data_rw_ctrl_inst|send_data_en, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal3~1 , data_rw_ctrl_inst|Equal3~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[13]~26 , data_rw_ctrl_inst|cnt_wait[13]~26, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[0] , data_rw_ctrl_inst|cnt_wait[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[1]~18 , data_rw_ctrl_inst|cnt_wait[1]~18, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[1] , data_rw_ctrl_inst|cnt_wait[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[2]~20 , data_rw_ctrl_inst|cnt_wait[2]~20, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[2] , data_rw_ctrl_inst|cnt_wait[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[3] , data_rw_ctrl_inst|cnt_wait[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal2~3 , data_rw_ctrl_inst|Equal2~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[6]~29 , data_rw_ctrl_inst|cnt_wait[6]~29, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[7]~31 , data_rw_ctrl_inst|cnt_wait[7]~31, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[7] , data_rw_ctrl_inst|cnt_wait[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[8]~33 , data_rw_ctrl_inst|cnt_wait[8]~33, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[8] , data_rw_ctrl_inst|cnt_wait[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[9]~35 , data_rw_ctrl_inst|cnt_wait[9]~35, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[9] , data_rw_ctrl_inst|cnt_wait[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[10]~37 , data_rw_ctrl_inst|cnt_wait[10]~37, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[10] , data_rw_ctrl_inst|cnt_wait[10], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[11]~39 , data_rw_ctrl_inst|cnt_wait[11]~39, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[12]~41 , data_rw_ctrl_inst|cnt_wait[12]~41, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[12] , data_rw_ctrl_inst|cnt_wait[12], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[13]~43 , data_rw_ctrl_inst|cnt_wait[13]~43, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[14]~45 , data_rw_ctrl_inst|cnt_wait[14]~45, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[14] , data_rw_ctrl_inst|cnt_wait[14], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[15]~47 , data_rw_ctrl_inst|cnt_wait[15]~47, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[15] , data_rw_ctrl_inst|cnt_wait[15], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[6] , data_rw_ctrl_inst|cnt_wait[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal2~0 , data_rw_ctrl_inst|Equal2~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[13] , data_rw_ctrl_inst|cnt_wait[13], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|cnt_wait[11] , data_rw_ctrl_inst|cnt_wait[11], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal2~1 , data_rw_ctrl_inst|Equal2~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal2~2 , data_rw_ctrl_inst|Equal2~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|Equal2~4 , data_rw_ctrl_inst|Equal2~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|rd_fifo_rd_en , data_rw_ctrl_inst|rd_fifo_rd_en, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|LessThan2~0 , sd_ctrl_inst|sd_read_inst|LessThan2~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|LessThan2~1 , sd_ctrl_inst|sd_read_inst|LessThan2~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_en~0 , sd_ctrl_inst|sd_read_inst|rd_data_en~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_en , sd_ctrl_inst|sd_read_inst|rd_data_en, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 , sd_ctrl_inst|sd_read_inst|rd_data_reg~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] , sd_ctrl_inst|sd_read_inst|rd_data_reg[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~13 , sd_ctrl_inst|sd_read_inst|rd_data~13, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 , sd_ctrl_inst|sd_read_inst|rd_data[6]~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[0] , sd_ctrl_inst|sd_read_inst|rd_data[0], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 , sd_ctrl_inst|sd_read_inst|rd_data_reg~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] , sd_ctrl_inst|sd_read_inst|rd_data_reg[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 , sd_ctrl_inst|sd_read_inst|rd_data_reg~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] , sd_ctrl_inst|sd_read_inst|rd_data_reg[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 , sd_ctrl_inst|sd_read_inst|rd_data_reg~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] , sd_ctrl_inst|sd_read_inst|rd_data_reg[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 , sd_ctrl_inst|sd_read_inst|rd_data_reg~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] , sd_ctrl_inst|sd_read_inst|rd_data_reg[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 , sd_ctrl_inst|sd_read_inst|rd_data_reg~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] , sd_ctrl_inst|sd_read_inst|rd_data_reg[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 , sd_ctrl_inst|sd_read_inst|rd_data_reg~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] , sd_ctrl_inst|sd_read_inst|rd_data_reg[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 , sd_ctrl_inst|sd_read_inst|rd_data_reg~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] , sd_ctrl_inst|sd_read_inst|rd_data_reg[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 , sd_ctrl_inst|sd_read_inst|rd_data_reg~13, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] , sd_ctrl_inst|sd_read_inst|rd_data_reg[8], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~14 , sd_ctrl_inst|sd_read_inst|rd_data~14, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[8] , sd_ctrl_inst|sd_read_inst|rd_data[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8], uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0, uart_sd, 1
+instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~15 , sd_ctrl_inst|sd_read_inst|rd_data~15, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[1] , sd_ctrl_inst|sd_read_inst|rd_data[1], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~11 , sd_ctrl_inst|sd_read_inst|rd_data~11, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[2] , sd_ctrl_inst|sd_read_inst|rd_data[2], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~7 , sd_ctrl_inst|sd_read_inst|rd_data~7, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[3] , sd_ctrl_inst|sd_read_inst|rd_data[3], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~5 , sd_ctrl_inst|sd_read_inst|rd_data~5, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[4] , sd_ctrl_inst|sd_read_inst|rd_data[4], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~3 , sd_ctrl_inst|sd_read_inst|rd_data~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[5] , sd_ctrl_inst|sd_read_inst|rd_data[5], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~9 , sd_ctrl_inst|sd_read_inst|rd_data~9, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[6] , sd_ctrl_inst|sd_read_inst|rd_data[6], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~0 , sd_ctrl_inst|sd_read_inst|rd_data~0, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[7] , sd_ctrl_inst|sd_read_inst|rd_data[7], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 , sd_ctrl_inst|sd_read_inst|rd_data_reg~15, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] , sd_ctrl_inst|sd_read_inst|rd_data_reg[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~16 , sd_ctrl_inst|sd_read_inst|rd_data~16, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[9] , sd_ctrl_inst|sd_read_inst|rd_data[9], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~12 , sd_ctrl_inst|sd_read_inst|rd_data~12, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[10] , sd_ctrl_inst|sd_read_inst|rd_data[10], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~8 , sd_ctrl_inst|sd_read_inst|rd_data~8, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[11] , sd_ctrl_inst|sd_read_inst|rd_data[11], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~6 , sd_ctrl_inst|sd_read_inst|rd_data~6, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[12] , sd_ctrl_inst|sd_read_inst|rd_data[12], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 , sd_ctrl_inst|sd_read_inst|rd_data_reg~3, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] , sd_ctrl_inst|sd_read_inst|rd_data_reg[13], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~4 , sd_ctrl_inst|sd_read_inst|rd_data~4, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[13] , sd_ctrl_inst|sd_read_inst|rd_data[13], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~10 , sd_ctrl_inst|sd_read_inst|rd_data~10, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[14] , sd_ctrl_inst|sd_read_inst|rd_data[14], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 , sd_ctrl_inst|sd_read_inst|rd_data_reg~1, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] , sd_ctrl_inst|sd_read_inst|rd_data_reg[15], uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~2 , sd_ctrl_inst|sd_read_inst|rd_data~2, uart_sd, 1
+instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[15] , sd_ctrl_inst|sd_read_inst|rd_data[15], uart_sd, 1
+instance = comp, \uart_tx_inst|Mux0~0 , uart_tx_inst|Mux0~0, uart_sd, 1
+instance = comp, \uart_tx_inst|tx~0 , uart_tx_inst|tx~0, uart_sd, 1
+instance = comp, \uart_tx_inst|tx , uart_tx_inst|tx, uart_sd, 1
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo
new file mode 100644
index 0000000..b378534
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo
@@ -0,0 +1,19061 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE15F23C8 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE15F23C8,
+// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "uart_sd")
+  (DATE "06/02/2023 04:03:15")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_pll")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1)
+    (DELAY
+      (ABSOLUTE
+        (PORT areset (4506:4506:4506) (4506:4506:4506))
+        (PORT inclk[0] (2340:2340:2340) (2340:2340:2340))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (931:931:931) (923:923:923))
+        (PORT datab (808:808:808) (785:785:785))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (804:804:804) (804:804:804))
+        (PORT datab (1238:1238:1238) (1164:1164:1164))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (544:544:544) (574:574:574))
+        (PORT datab (334:334:334) (410:410:410))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1396:1396:1396) (1367:1367:1367))
+        (PORT d[1] (1359:1359:1359) (1335:1335:1335))
+        (PORT d[2] (1452:1452:1452) (1414:1414:1414))
+        (PORT d[3] (1585:1585:1585) (1553:1553:1553))
+        (PORT d[4] (1387:1387:1387) (1364:1364:1364))
+        (PORT d[5] (1594:1594:1594) (1561:1561:1561))
+        (PORT d[6] (1414:1414:1414) (1386:1386:1386))
+        (PORT d[7] (1413:1413:1413) (1374:1374:1374))
+        (PORT clk (2265:2265:2265) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1000:1000:1000) (1004:1004:1004))
+        (PORT d[1] (1057:1057:1057) (1051:1051:1051))
+        (PORT d[2] (1285:1285:1285) (1234:1234:1234))
+        (PORT d[3] (1146:1146:1146) (1091:1091:1091))
+        (PORT d[4] (998:998:998) (1003:1003:1003))
+        (PORT d[5] (1764:1764:1764) (1697:1697:1697))
+        (PORT d[6] (1395:1395:1395) (1356:1356:1356))
+        (PORT d[7] (1735:1735:1735) (1651:1651:1651))
+        (PORT d[8] (1021:1021:1021) (1025:1025:1025))
+        (PORT d[9] (923:923:923) (875:875:875))
+        (PORT clk (2261:2261:2261) (2297:2297:2297))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1263:1263:1263) (1151:1151:1151))
+        (PORT clk (2261:2261:2261) (2297:2297:2297))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2265:2265:2265) (2302:2302:2302))
+        (PORT d[0] (1970:1970:1970) (1865:1865:1865))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2266:2266:2266) (2303:2303:2303))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1346:1346:1346) (1254:1254:1254))
+        (PORT d[1] (1033:1033:1033) (1026:1026:1026))
+        (PORT d[2] (1785:1785:1785) (1710:1710:1710))
+        (PORT d[3] (1782:1782:1782) (1727:1727:1727))
+        (PORT d[4] (1630:1630:1630) (1616:1616:1616))
+        (PORT d[5] (1873:1873:1873) (1814:1814:1814))
+        (PORT d[6] (1365:1365:1365) (1328:1328:1328))
+        (PORT d[7] (1459:1459:1459) (1427:1427:1427))
+        (PORT d[8] (974:974:974) (920:920:920))
+        (PORT clk (2215:2215:2215) (2211:2211:2211))
+        (PORT stall (1591:1591:1591) (1712:1712:1712))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+      (HOLD stall (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2215:2215:2215) (2211:2211:2211))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2216:2216:2216) (2212:2212:2212))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2207:2207:2207) (2207:2207:2207))
+        (PORT ena (2140:2140:2140) (2024:2024:2024))
+        (IOPATH (posedge clk) q (392:392:392) (392:392:392))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (64:64:64))
+      (SETUP ena (posedge clk) (64:64:64))
+      (HOLD d (posedge clk) (211:211:211))
+      (HOLD ena (posedge clk) (211:211:211))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1219:1219:1219) (1143:1143:1143))
+        (PORT d[1] (1184:1184:1184) (1118:1118:1118))
+        (PORT d[2] (1203:1203:1203) (1138:1138:1138))
+        (PORT d[3] (1598:1598:1598) (1487:1487:1487))
+        (PORT d[4] (1213:1213:1213) (1146:1146:1146))
+        (PORT d[5] (1177:1177:1177) (1117:1117:1117))
+        (PORT d[6] (1221:1221:1221) (1147:1147:1147))
+        (PORT d[7] (1211:1211:1211) (1142:1142:1142))
+        (PORT d[9] (1185:1185:1185) (1123:1123:1123))
+        (PORT d[10] (1282:1282:1282) (1216:1216:1216))
+        (PORT d[11] (1267:1267:1267) (1194:1194:1194))
+        (PORT d[12] (1220:1220:1220) (1147:1147:1147))
+        (PORT d[13] (1532:1532:1532) (1431:1431:1431))
+        (PORT d[14] (1183:1183:1183) (1121:1121:1121))
+        (PORT d[15] (1589:1589:1589) (1459:1459:1459))
+        (PORT d[16] (1587:1587:1587) (1473:1473:1473))
+        (PORT clk (2277:2277:2277) (2307:2307:2307))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1343:1343:1343) (1305:1305:1305))
+        (PORT d[1] (1319:1319:1319) (1250:1250:1250))
+        (PORT d[2] (1673:1673:1673) (1575:1575:1575))
+        (PORT d[3] (1201:1201:1201) (1154:1154:1154))
+        (PORT d[4] (1004:1004:1004) (992:992:992))
+        (PORT d[5] (1807:1807:1807) (1681:1681:1681))
+        (PORT d[6] (1680:1680:1680) (1599:1599:1599))
+        (PORT d[7] (949:949:949) (949:949:949))
+        (PORT d[8] (1566:1566:1566) (1421:1421:1421))
+        (PORT clk (2273:2273:2273) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1282:1282:1282) (1174:1174:1174))
+        (PORT clk (2273:2273:2273) (2302:2302:2302))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2277:2277:2277) (2307:2307:2307))
+        (PORT d[0] (1989:1989:1989) (1888:1888:1888))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2278:2278:2278) (2308:2308:2308))
+        (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1309:1309:1309) (1203:1203:1203))
+        (PORT d[1] (1804:1804:1804) (1740:1740:1740))
+        (PORT d[2] (1461:1461:1461) (1445:1445:1445))
+        (PORT d[3] (1021:1021:1021) (1013:1013:1013))
+        (PORT d[4] (1060:1060:1060) (1047:1047:1047))
+        (PORT d[5] (1578:1578:1578) (1553:1553:1553))
+        (PORT d[6] (1006:1006:1006) (992:992:992))
+        (PORT d[7] (1333:1333:1333) (1307:1307:1307))
+        (PORT d[8] (1312:1312:1312) (1273:1273:1273))
+        (PORT d[9] (1627:1627:1627) (1511:1511:1511))
+        (PORT clk (2227:2227:2227) (2216:2216:2216))
+        (PORT stall (1248:1248:1248) (1359:1359:1359))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (254:254:254))
+      (HOLD stall (posedge clk) (254:254:254))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2227:2227:2227) (2216:2216:2216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_pulse_generator")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2228:2228:2228) (2217:2217:2217))
+        (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_ram_register")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2219:2219:2219) (2212:2212:2212))
+        (PORT ena (1788:1788:1788) (1681:1681:1681))
+        (IOPATH (posedge clk) q (392:392:392) (392:392:392))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (64:64:64))
+      (SETUP ena (posedge clk) (64:64:64))
+      (HOLD d (posedge clk) (211:211:211))
+      (HOLD ena (posedge clk) (211:211:211))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (567:567:567) (610:610:610))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (481:481:481))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (449:449:449))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (462:462:462))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (430:430:430))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (450:450:450))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (432:432:432))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (435:435:435))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (438:438:438))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (805:805:805) (798:798:798))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (628:628:628) (632:632:632))
+        (PORT datac (580:580:580) (595:595:595))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (432:432:432))
+        (PORT datab (565:565:565) (593:593:593))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (605:605:605))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (524:524:524) (558:558:558))
+        (PORT datad (474:474:474) (446:446:446))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (326:326:326))
+        (PORT datab (642:642:642) (657:657:657))
+        (PORT datac (1966:1966:1966) (1886:1886:1886))
+        (PORT datad (1111:1111:1111) (1012:1012:1012))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (463:463:463))
+        (PORT datab (359:359:359) (454:454:454))
+        (PORT datac (317:317:317) (411:411:411))
+        (PORT datad (321:321:321) (404:404:404))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (627:627:627))
+        (PORT datab (394:394:394) (508:508:508))
+        (PORT datac (924:924:924) (871:871:871))
+        (PORT datad (508:508:508) (485:485:485))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (953:953:953) (919:919:919))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (508:508:508) (494:494:494))
+        (PORT datad (355:355:355) (466:466:466))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (619:619:619) (585:585:585))
+        (PORT datab (383:383:383) (479:479:479))
+        (PORT datac (566:566:566) (543:543:543))
+        (PORT datad (356:356:356) (467:467:467))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (283:283:283) (315:315:315))
+        (PORT datab (385:385:385) (481:481:481))
+        (PORT datac (1679:1679:1679) (1549:1549:1549))
+        (PORT datad (928:928:928) (884:884:884))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (628:628:628))
+        (PORT datab (389:389:389) (503:503:503))
+        (PORT datac (906:906:906) (851:851:851))
+        (PORT datad (513:513:513) (492:492:492))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (925:925:925))
+        (PORT datab (384:384:384) (480:480:480))
+        (PORT datac (449:449:449) (425:425:425))
+        (PORT datad (943:943:943) (885:885:885))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (366:366:366) (458:458:458))
+        (PORT datac (343:343:343) (439:439:439))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (960:960:960) (926:926:926))
+        (PORT datab (384:384:384) (480:480:480))
+        (PORT datac (559:559:559) (534:534:534))
+        (PORT datad (354:354:354) (464:464:464))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (946:946:946) (905:905:905))
+        (PORT datab (398:398:398) (513:513:513))
+        (PORT datac (558:558:558) (533:533:533))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (370:370:370) (462:462:462))
+        (PORT datac (238:238:238) (265:265:265))
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (641:641:641) (656:656:656))
+        (PORT datac (573:573:573) (592:592:592))
+        (PORT datad (868:868:868) (822:822:822))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1097:1097:1097) (1105:1105:1105))
+        (PORT datac (975:975:975) (1007:1007:1007))
+        (PORT datad (1014:1014:1014) (1020:1020:1020))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (996:996:996) (1013:1013:1013))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (974:974:974) (1005:1005:1005))
+        (PORT datad (978:978:978) (973:973:973))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1026:1026:1026))
+        (PORT datab (1018:1018:1018) (1046:1046:1046))
+        (PORT datac (1038:1038:1038) (1061:1061:1061))
+        (PORT datad (1012:1012:1012) (1018:1018:1018))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (954:954:954) (967:967:967))
+        (PORT datad (898:898:898) (902:902:902))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1093:1093:1093) (1100:1100:1100))
+        (PORT datac (958:958:958) (977:977:977))
+        (PORT datad (1013:1013:1013) (1018:1018:1018))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1027:1027:1027))
+        (PORT datab (1017:1017:1017) (1045:1045:1045))
+        (PORT datac (953:953:953) (966:966:966))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1019:1019:1019) (1048:1048:1048))
+        (PORT datac (956:956:956) (975:975:975))
+        (PORT datad (1014:1014:1014) (1019:1019:1019))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1012:1012:1012))
+        (PORT datab (1097:1097:1097) (1104:1104:1104))
+        (PORT datac (974:974:974) (1006:1006:1006))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1003:1003:1003) (1026:1026:1026))
+        (PORT datab (1099:1099:1099) (1107:1107:1107))
+        (PORT datac (975:975:975) (1008:1008:1008))
+        (PORT datad (1015:1015:1015) (1021:1021:1021))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1011:1011:1011))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (955:955:955) (974:974:974))
+        (PORT datad (900:900:900) (898:898:898))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (906:906:906) (904:904:904))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1056:1056:1056) (1042:1042:1042))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (335:335:335) (423:423:423))
+        (PORT datad (341:341:341) (440:440:440))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (951:951:951) (877:877:877))
+        (PORT datab (392:392:392) (494:494:494))
+        (PORT datac (353:353:353) (473:473:473))
+        (PORT datad (867:867:867) (797:797:797))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (310:310:310))
+        (PORT datab (390:390:390) (492:492:492))
+        (PORT datac (851:851:851) (786:786:786))
+        (PORT datad (878:878:878) (811:811:811))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (862:862:862) (811:811:811))
+        (PORT datab (397:397:397) (515:515:515))
+        (PORT datac (809:809:809) (750:750:750))
+        (PORT datad (348:348:348) (449:449:449))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (398:398:398) (515:515:515))
+        (PORT datac (811:811:811) (754:754:754))
+        (PORT datad (349:349:349) (450:450:450))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (337:337:337) (424:424:424))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datad (531:531:531) (559:559:559))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (591:591:591) (628:628:628))
+        (PORT datab (360:360:360) (449:449:449))
+        (PORT datac (316:316:316) (413:413:413))
+        (PORT datad (263:263:263) (280:280:280))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (615:615:615) (619:619:619))
+        (PORT datac (564:564:564) (579:579:579))
+        (PORT datad (521:521:521) (540:540:540))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (1696:1696:1696) (1660:1660:1660))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (912:912:912) (907:907:907))
+        (PORT datab (1228:1228:1228) (1188:1188:1188))
+        (PORT datac (341:341:341) (430:430:430))
+        (PORT datad (254:254:254) (283:283:283))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datac (354:354:354) (438:438:438))
+        (PORT datad (274:274:274) (295:295:295))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (595:595:595) (631:631:631))
+        (PORT datad (254:254:254) (283:283:283))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (883:883:883) (842:842:842))
+        (PORT datac (810:810:810) (790:790:790))
+        (PORT datad (764:764:764) (700:700:700))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (810:810:810) (790:790:790))
+        (PORT datad (764:764:764) (700:700:700))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1269:1269:1269) (1235:1235:1235))
+        (PORT datad (1212:1212:1212) (1150:1150:1150))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (437:437:437))
+        (PORT datac (312:312:312) (400:400:400))
+        (PORT datad (323:323:323) (402:402:402))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (473:473:473))
+        (PORT datab (352:352:352) (442:442:442))
+        (PORT datac (336:336:336) (426:426:426))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (445:445:445))
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datac (845:845:845) (833:833:833))
+        (PORT datad (256:256:256) (282:282:282))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (903:903:903) (919:919:919))
+        (PORT datab (590:590:590) (574:574:574))
+        (PORT datac (1103:1103:1103) (1004:1004:1004))
+        (PORT datad (338:338:338) (419:419:419))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datad (300:300:300) (373:373:373))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (976:976:976) (910:910:910))
+        (PORT datac (788:788:788) (717:717:717))
+        (PORT datad (340:340:340) (424:424:424))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (446:446:446))
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datac (845:845:845) (833:833:833))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1181:1181:1181) (1102:1102:1102))
+        (PORT datab (362:362:362) (452:452:452))
+        (PORT datac (318:318:318) (416:416:416))
+        (PORT datad (482:482:482) (469:469:469))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (279:279:279) (304:304:304))
+        (PORT datac (494:494:494) (468:468:468))
+        (PORT datad (826:826:826) (758:758:758))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (285:285:285) (317:317:317))
+        (PORT datac (495:495:495) (475:475:475))
+        (PORT datad (972:972:972) (966:966:966))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (432:432:432))
+        (PORT datab (340:340:340) (419:419:419))
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (462:462:462))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (320:320:320) (407:407:407))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (276:276:276) (300:300:300))
+        (PORT datad (249:249:249) (271:271:271))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (515:515:515) (501:501:501))
+        (PORT datac (486:486:486) (463:463:463))
+        (PORT datad (330:330:330) (404:404:404))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (581:581:581) (603:603:603))
+        (PORT datab (397:397:397) (512:512:512))
+        (PORT datad (329:329:329) (420:420:420))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1341:1341:1341) (1329:1329:1329))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (933:933:933) (934:934:934))
+        (PORT datab (867:867:867) (869:869:869))
+        (PORT datad (903:903:903) (893:893:893))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (760:760:760) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (941:941:941))
+        (PORT datab (944:944:944) (930:930:930))
+        (PORT datad (293:293:293) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (959:959:959))
+        (PORT datab (888:888:888) (883:883:883))
+        (PORT datad (881:881:881) (876:876:876))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (973:973:973) (988:988:988))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1189:1189:1189) (1105:1105:1105))
+        (PORT datab (905:905:905) (896:896:896))
+        (PORT datad (296:296:296) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (492:492:492) (471:471:471))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (482:482:482) (450:450:450))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (934:934:934) (932:932:932))
+        (PORT datab (1342:1342:1342) (1281:1281:1281))
+        (PORT datad (310:310:310) (394:394:394))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1612:1612:1612) (1516:1516:1516))
+        (PORT datab (921:921:921) (910:910:910))
+        (PORT datad (549:549:549) (573:573:573))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (769:769:769) (844:844:844))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (772:772:772) (848:848:848))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1664:1664:1664))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1327:1327:1327) (1294:1294:1294))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (926:926:926) (912:912:912))
+        (PORT datab (617:617:617) (631:631:631))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (617:617:617) (626:626:626))
+        (PORT datab (827:827:827) (817:817:817))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (391:391:391) (507:507:507))
+        (PORT datac (336:336:336) (424:424:424))
+        (PORT datad (340:340:340) (439:439:439))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (295:295:295) (330:330:330))
+        (PORT datad (291:291:291) (325:325:325))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (936:936:936) (946:946:946))
+        (PORT datab (341:341:341) (421:421:421))
+        (PORT datac (305:305:305) (389:389:389))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1366:1366:1366) (1361:1361:1361))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (515:515:515) (501:501:501))
+        (PORT datac (487:487:487) (463:463:463))
+        (PORT datad (330:330:330) (404:404:404))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2013:2013:2013) (1835:1835:1835))
+        (PORT datac (330:330:330) (415:415:415))
+        (PORT datad (238:238:238) (256:256:256))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1740:1740:1740) (1706:1706:1706))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1825:1825:1825) (1791:1791:1791))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (794:794:794) (869:869:869))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (771:771:771) (846:846:846))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT ena (1107:1107:1107) (1090:1090:1090))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT asdata (771:771:771) (846:846:846))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT ena (1710:1710:1710) (1624:1624:1624))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datad (1118:1118:1118) (1013:1013:1013))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (768:768:768) (843:843:843))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (762:762:762) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1311:1311:1311) (1233:1233:1233))
+        (PORT datab (980:980:980) (943:943:943))
+        (PORT datac (362:362:362) (451:451:451))
+        (PORT datad (282:282:282) (306:306:306))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (303:303:303) (388:388:388))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (307:307:307) (391:391:391))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (942:942:942) (953:953:953))
+        (PORT datac (377:377:377) (502:502:502))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4197:4197:4197) (4406:4406:4406))
+        (PORT datad (917:917:917) (911:911:911))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (789:789:789) (859:859:859))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3759:3759:3759) (3988:3988:3988))
+        (PORT datab (354:354:354) (440:440:440))
+        (PORT datac (579:579:579) (595:595:595))
+        (PORT datad (922:922:922) (922:922:922))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (468:468:468))
+        (PORT datab (353:353:353) (441:441:441))
+        (PORT datac (531:531:531) (562:562:562))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (478:478:478))
+        (PORT datab (303:303:303) (340:340:340))
+        (PORT datac (337:337:337) (429:429:429))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT asdata (2143:2143:2143) (2068:2068:2068))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT asdata (1042:1042:1042) (1075:1075:1075))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1685:1685:1685) (1653:1653:1653))
+        (PORT datab (1310:1310:1310) (1222:1222:1222))
+        (PORT datac (307:307:307) (394:394:394))
+        (PORT datad (1199:1199:1199) (1130:1130:1130))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1672:1672:1672) (1637:1637:1637))
+        (PORT datab (1306:1306:1306) (1218:1218:1218))
+        (PORT datac (301:301:301) (386:386:386))
+        (PORT datad (1203:1203:1203) (1136:1136:1136))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1389:1389:1389) (1384:1384:1384))
+        (PORT datab (900:900:900) (861:861:861))
+        (PORT datac (1136:1136:1136) (1066:1066:1066))
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1275:1275:1275) (1196:1196:1196))
+        (PORT datab (1307:1307:1307) (1218:1218:1218))
+        (PORT datac (1621:1621:1621) (1577:1577:1577))
+        (PORT datad (307:307:307) (382:382:382))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (466:466:466))
+        (PORT datab (370:370:370) (466:466:466))
+        (PORT datac (311:311:311) (399:399:399))
+        (PORT datad (312:312:312) (388:388:388))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1367:1367:1367) (1362:1362:1362))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (645:645:645))
+        (PORT datab (856:856:856) (845:845:845))
+        (PORT datac (537:537:537) (560:560:560))
+        (PORT datad (527:527:527) (551:551:551))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1854:1854:1854))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1875:1875:1875) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (572:572:572) (599:599:599))
+        (PORT datab (341:341:341) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (449:449:449))
+        (PORT datab (349:349:349) (438:438:438))
+        (PORT datac (311:311:311) (401:401:401))
+        (PORT datad (311:311:311) (391:391:391))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (365:365:365) (442:442:442))
+        (PORT datad (324:324:324) (395:395:395))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_reg1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1854:1854:1854))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1875:1875:1875) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|start_nedge)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datac (1672:1672:1672) (1604:1604:1604))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (306:306:306) (392:392:392))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (301:301:301) (386:386:386))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3662:3662:3662) (3834:3834:3834))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (346:346:346) (436:436:436))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE rx\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (796:796:796) (842:842:842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (581:581:581))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (971:971:971) (966:966:966))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1242:1242:1242) (1210:1210:1210))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (326:326:326) (397:397:397))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (536:536:536) (568:568:568))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1468:1468:1468) (1342:1342:1342))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (325:325:325) (396:396:396))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (904:904:904) (893:893:893))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (306:306:306) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (376:376:376))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (377:377:377))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (908:908:908) (909:909:909))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (906:906:906) (907:907:907))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (378:378:378))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (884:884:884) (878:878:878))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (809:809:809) (780:780:780))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|rx_reg2\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_clk\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1609:1609:1609) (1559:1559:1559))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_cs_n\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1891:1891:1891) (1762:1762:1762))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE sd_mosi\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1825:1825:1825) (1696:1696:1696))
+        (IOPATH i o (3241:3241:3241) (3144:3144:3144))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE tx\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2904:2904:2904) (3042:3042:3042))
+        (IOPATH i o (3336:3336:3336) (3399:3399:3399))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_clk\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (806:806:806) (852:852:852))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2339:2339:2339) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (374:374:374) (460:460:460))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sys_rst_n\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (766:766:766) (812:812:812))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (3674:3674:3674) (3934:3934:3934))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (4634:4634:4634) (4434:4434:4434))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE rst_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3009:3009:3009) (3252:3252:3252))
+        (PORT datab (3770:3770:3770) (3925:3925:3925))
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE rst_n\~0clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2603:2603:2603) (2464:2464:2464))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE sd_miso\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (734:734:734) (781:781:781))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT asdata (4598:4598:4598) (4812:4812:4812))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4196:4196:4196) (4405:4405:4405))
+        (PORT datab (344:344:344) (427:427:427))
+        (PORT datad (528:528:528) (555:555:555))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (643:643:643))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (846:846:846) (813:813:813))
+        (PORT datad (553:553:553) (574:574:574))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (568:568:568) (605:605:605))
+        (PORT datab (891:891:891) (857:857:857))
+        (PORT datac (844:844:844) (810:810:810))
+        (PORT datad (552:552:552) (573:573:573))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (529:529:529))
+        (PORT datab (491:491:491) (476:476:476))
+        (PORT datad (254:254:254) (282:282:282))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1851:1851:1851))
+        (PORT sclr (1215:1215:1215) (1257:1257:1257))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (603:603:603))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (303:303:303) (387:387:387))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (595:595:595) (626:626:626))
+        (PORT datac (499:499:499) (480:480:480))
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (1676:1676:1676) (1638:1638:1638))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (998:998:998) (1014:1014:1014))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT ena (1644:1644:1644) (1548:1548:1548))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (432:432:432))
+        (PORT datab (342:342:342) (421:421:421))
+        (PORT datad (523:523:523) (549:549:549))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (823:823:823) (774:774:774))
+        (PORT datac (446:446:446) (418:418:418))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (433:433:433))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (385:385:385) (476:476:476))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (388:388:388) (482:482:482))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3848:3848:3848) (4133:4133:4133))
+        (PORT datab (949:949:949) (947:947:947))
+        (PORT datac (347:347:347) (443:443:443))
+        (PORT datad (349:349:349) (434:434:434))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (521:521:521))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (246:246:246) (271:271:271))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (430:430:430))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datac (310:310:310) (399:399:399))
+        (PORT datad (320:320:320) (411:411:411))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (286:286:286) (314:314:314))
+        (PORT datac (347:347:347) (443:443:443))
+        (PORT datad (349:349:349) (433:433:433))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (462:462:462))
+        (PORT datab (343:343:343) (422:422:422))
+        (PORT datac (345:345:345) (440:440:440))
+        (PORT datad (347:347:347) (431:431:431))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (474:474:474))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (380:380:380) (466:466:466))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (337:337:337) (427:427:427))
+        (PORT datad (338:338:338) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (1262:1262:1262) (1239:1239:1239))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (762:762:762) (832:832:832))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (370:370:370))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (759:759:759) (828:828:828))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (306:306:306) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT asdata (998:998:998) (1021:1021:1021))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1853:1853:1853))
+        (PORT ena (1944:1944:1944) (1786:1786:1786))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (894:894:894) (890:890:890))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (761:761:761) (830:830:830))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (762:762:762) (832:832:832))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (762:762:762) (831:831:831))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (763:763:763) (833:833:833))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT asdata (760:760:760) (829:829:829))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1845:1845:1845) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1865:1865:1865))
+        (PORT ena (1587:1587:1587) (1463:1463:1463))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (1246:1246:1246) (1218:1218:1218))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (314:314:314) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (508:508:508) (535:535:535))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (982:982:982) (1002:1002:1002))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (556:556:556) (590:590:590))
+        (PORT datad (506:506:506) (534:534:534))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (971:971:971) (986:986:986))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (302:302:302) (375:375:375))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1844:1844:1844) (1857:1857:1857))
+        (PORT asdata (770:770:770) (846:846:846))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (PORT ena (1335:1335:1335) (1275:1275:1275))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datad (304:304:304) (376:376:376))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (294:294:294) (333:333:333))
+        (PORT datad (256:256:256) (282:282:282))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (883:883:883) (802:802:802))
+        (PORT datac (320:320:320) (416:416:416))
+        (PORT datad (482:482:482) (469:469:469))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (447:447:447))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (600:600:600))
+        (PORT datab (341:341:341) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (284:284:284) (315:315:315))
+        (PORT datac (311:311:311) (402:402:402))
+        (PORT datad (248:248:248) (270:270:270))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (PORT sload (1066:1066:1066) (1150:1150:1150))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sload (posedge clk) (212:212:212))
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (433:433:433))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (357:357:357) (452:452:452))
+        (PORT datab (286:286:286) (317:317:317))
+        (PORT datad (249:249:249) (271:271:271))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1843:1843:1843) (1856:1856:1856))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1876:1876:1876) (1847:1847:1847))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (836:836:836) (785:785:785))
+        (PORT datad (788:788:788) (706:706:706))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (531:531:531) (520:520:520))
+        (PORT datac (306:306:306) (392:392:392))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (449:449:449))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (566:566:566) (609:609:609))
+        (PORT datab (342:342:342) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (328:328:328) (405:405:405))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (959:959:959) (947:947:947))
+        (PORT datac (864:864:864) (812:812:812))
+        (PORT datad (285:285:285) (313:313:313))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (PORT sclr (903:903:903) (966:966:966))
+        (PORT ena (1043:1043:1043) (1024:1024:1024))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1026:1026:1026))
+        (PORT datab (1099:1099:1099) (1107:1107:1107))
+        (PORT datac (975:975:975) (1007:1007:1007))
+        (PORT datad (1015:1015:1015) (1021:1021:1021))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (858:858:858) (805:805:805))
+        (PORT datad (279:279:279) (306:306:306))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (782:782:782) (733:733:733))
+        (PORT datab (381:381:381) (464:464:464))
+        (PORT datad (530:530:530) (526:526:526))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1182:1182:1182) (1104:1104:1104))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (320:320:320) (416:416:416))
+        (PORT datad (479:479:479) (466:466:466))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (784:784:784) (734:734:734))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (531:531:531) (528:528:528))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (785:785:785) (736:736:736))
+        (PORT datab (371:371:371) (455:455:455))
+        (PORT datad (532:532:532) (529:529:529))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (381:381:381) (475:475:475))
+        (PORT datab (594:594:594) (578:578:578))
+        (PORT datad (826:826:826) (758:758:758))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (462:462:462))
+        (PORT datab (591:591:591) (574:574:574))
+        (PORT datad (820:820:820) (752:752:752))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (462:462:462))
+        (PORT datab (359:359:359) (452:452:452))
+        (PORT datac (316:316:316) (410:410:410))
+        (PORT datad (321:321:321) (392:392:392))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (980:980:980) (914:914:914))
+        (PORT datac (793:793:793) (723:723:723))
+        (PORT datad (329:329:329) (406:406:406))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (522:522:522) (519:519:519))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (319:319:319) (413:413:413))
+        (PORT datad (824:824:824) (756:756:756))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (379:379:379) (472:472:472))
+        (PORT datab (370:370:370) (454:454:454))
+        (PORT datac (538:538:538) (572:572:572))
+        (PORT datad (338:338:338) (419:419:419))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (907:907:907) (857:857:857))
+        (PORT datab (324:324:324) (355:355:355))
+        (PORT datac (522:522:522) (494:494:494))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (441:441:441))
+        (PORT datab (531:531:531) (520:520:520))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (445:445:445))
+        (PORT datac (805:805:805) (798:798:798))
+        (PORT datad (338:338:338) (418:418:418))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (850:850:850) (818:818:818))
+        (PORT datab (830:830:830) (770:770:770))
+        (PORT datac (238:238:238) (264:264:264))
+        (PORT datad (1185:1185:1185) (1096:1096:1096))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (442:442:442))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (450:450:450))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (450:450:450))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (438:438:438))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (571:571:571) (599:599:599))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (318:318:318) (413:413:413))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (444:444:444))
+        (PORT datac (326:326:326) (411:411:411))
+        (PORT datad (309:309:309) (389:389:389))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (285:285:285) (316:316:316))
+        (PORT datac (495:495:495) (475:475:475))
+        (PORT datad (972:972:972) (967:967:967))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (531:531:531))
+        (PORT datab (1201:1201:1201) (1076:1076:1076))
+        (PORT datad (255:255:255) (283:283:283))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (298:298:298) (336:336:336))
+        (PORT datab (345:345:345) (428:428:428))
+        (PORT datac (504:504:504) (486:486:486))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (822:822:822) (784:784:784))
+        (PORT datab (854:854:854) (816:816:816))
+        (PORT datad (1184:1184:1184) (1095:1095:1095))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (627:627:627))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (338:338:338) (428:428:428))
+        (PORT datad (318:318:318) (405:405:405))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (433:433:433))
+        (PORT datab (565:565:565) (594:594:594))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (296:296:296) (341:341:341))
+        (PORT datab (530:530:530) (492:492:492))
+        (PORT datac (509:509:509) (480:480:480))
+        (PORT datad (574:574:574) (595:595:595))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (1663:1663:1663) (1589:1589:1589))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (470:470:470))
+        (PORT datac (314:314:314) (403:403:403))
+        (PORT datad (312:312:312) (389:389:389))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1369:1369:1369) (1364:1364:1364))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (292:292:292) (319:319:319))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (465:465:465))
+        (PORT datac (310:310:310) (398:398:398))
+        (PORT datad (311:311:311) (388:388:388))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (453:453:453))
+        (PORT datad (601:601:601) (651:651:651))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (704:704:704))
+        (PORT datac (301:301:301) (385:385:385))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (704:704:704))
+        (PORT datad (506:506:506) (537:537:537))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (643:643:643) (702:702:702))
+        (PORT datac (303:303:303) (386:386:386))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (437:437:437))
+        (PORT datab (550:550:550) (585:585:585))
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (607:607:607) (622:622:622))
+        (PORT datad (600:600:600) (650:650:650))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (642:642:642) (700:700:700))
+        (PORT datac (304:304:304) (389:389:389))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (642:642:642) (701:701:701))
+        (PORT datac (302:302:302) (386:386:386))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (302:302:302) (387:387:387))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (431:431:431))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datac (535:535:535) (553:553:553))
+        (PORT datad (534:534:534) (560:560:560))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (558:558:558) (531:531:531))
+        (PORT datab (287:287:287) (319:319:319))
+        (PORT datac (506:506:506) (485:485:485))
+        (PORT datad (490:490:490) (461:461:461))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (495:495:495) (475:475:475))
+        (PORT datab (889:889:889) (798:798:798))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (436:436:436))
+        (PORT datab (422:422:422) (545:545:545))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (544:544:544))
+        (PORT datac (304:304:304) (388:388:388))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (435:435:435))
+        (PORT datab (422:422:422) (545:545:545))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (545:545:545))
+        (PORT datac (304:304:304) (389:389:389))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (433:433:433))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datac (300:300:300) (383:383:383))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (557:557:557) (530:530:530))
+        (PORT datab (286:286:286) (318:318:318))
+        (PORT datac (505:505:505) (484:484:484))
+        (PORT datad (490:490:490) (461:461:461))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1366:1366:1366) (1360:1360:1360))
+        (PORT datab (323:323:323) (360:360:360))
+        (PORT datad (291:291:291) (319:319:319))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1369:1369:1369) (1364:1364:1364))
+        (PORT datab (322:322:322) (359:359:359))
+        (PORT datac (445:445:445) (427:427:427))
+        (PORT datad (333:333:333) (427:427:427))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (453:453:453))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (449:449:449))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1862:1862:1862))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1853:1853:1853))
+        (PORT sclr (1597:1597:1597) (1663:1663:1663))
+        (PORT ena (1276:1276:1276) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (299:299:299) (344:344:344))
+        (PORT datab (321:321:321) (358:358:358))
+        (PORT datac (518:518:518) (550:550:550))
+        (PORT datad (332:332:332) (426:426:426))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (538:538:538) (498:498:498))
+        (PORT datab (634:634:634) (643:643:643))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (514:514:514) (499:499:499))
+        (PORT datab (854:854:854) (816:816:816))
+        (PORT datad (516:516:516) (550:550:550))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (531:531:531) (560:560:560))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datad (531:531:531) (559:559:559))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (339:339:339) (422:422:422))
+        (PORT datac (303:303:303) (388:388:388))
+        (PORT datad (311:311:311) (395:395:395))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (313:313:313) (343:343:343))
+        (PORT datad (533:533:533) (562:562:562))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (575:575:575))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (433:433:433))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (566:566:566) (593:593:593))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (432:432:432))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (345:345:345) (428:428:428))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (PORT sclr (1036:1036:1036) (1021:1021:1021))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (301:301:301) (386:386:386))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (466:466:466))
+        (PORT datab (570:570:570) (598:598:598))
+        (PORT datac (309:309:309) (401:401:401))
+        (PORT datad (311:311:311) (395:395:395))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (315:315:315) (342:342:342))
+        (PORT datad (266:266:266) (283:283:283))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (467:467:467))
+        (PORT datab (343:343:343) (421:421:421))
+        (PORT datad (274:274:274) (298:298:298))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (768:768:768) (844:844:844))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (994:994:994) (1010:1010:1010))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (432:432:432))
+        (PORT datab (341:341:341) (420:420:420))
+        (PORT datad (320:320:320) (391:391:391))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1861:1861:1861))
+        (PORT asdata (772:772:772) (849:849:849))
+        (PORT clrn (1883:1883:1883) (1852:1852:1852))
+        (PORT ena (1602:1602:1602) (1501:1501:1501))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datab (344:344:344) (424:424:424))
+        (PORT datad (527:527:527) (554:554:554))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (893:893:893) (833:833:833))
+        (PORT datad (833:833:833) (773:773:773))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (326:326:326))
+        (PORT datab (1925:1925:1925) (1777:1777:1777))
+        (PORT datad (240:240:240) (259:259:259))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2353:2353:2353) (2234:2234:2234))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (480:480:480))
+        (PORT datad (332:332:332) (423:423:423))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1888:1888:1888) (1867:1867:1867))
+        (PORT sclr (2890:2890:2890) (3064:3064:3064))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (628:628:628))
+        (PORT datab (388:388:388) (502:502:502))
+        (PORT datac (342:342:342) (438:438:438))
+        (PORT datad (328:328:328) (418:418:418))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1946:1946:1946) (1865:1865:1865))
+        (PORT datad (1111:1111:1111) (1012:1012:1012))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (449:449:449))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1880:1880:1880))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1871:1871:1871))
+        (PORT sclr (2715:2715:2715) (2924:2924:2924))
+        (PORT ena (1279:1279:1279) (1214:1214:1214))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1152:1152:1152) (1063:1063:1063))
+        (PORT datab (622:622:622) (629:629:629))
+        (PORT datac (574:574:574) (593:593:593))
+        (PORT datad (536:536:536) (557:557:557))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (547:547:547) (509:509:509))
+        (PORT datab (641:641:641) (655:655:655))
+        (PORT datac (527:527:527) (561:561:561))
+        (PORT datad (265:265:265) (283:283:283))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1218:1218:1218) (1156:1156:1156))
+        (PORT datab (1653:1653:1653) (1531:1531:1531))
+        (PORT datad (466:466:466) (440:440:440))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4262:4262:4262) (4487:4487:4487))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (306:306:306) (392:392:392))
+        (PORT datad (381:381:381) (478:478:478))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (430:430:430))
+        (PORT datab (345:345:345) (426:426:426))
+        (PORT datac (299:299:299) (380:380:380))
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (437:437:437))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (364:364:364) (441:441:441))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (382:382:382) (479:479:479))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (304:304:304) (387:387:387))
+        (PORT datad (382:382:382) (478:478:478))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1842:1842:1842) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1845:1845:1845))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (575:575:575) (603:603:603))
+        (PORT datab (343:343:343) (423:423:423))
+        (PORT datac (300:300:300) (382:382:382))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datad (239:239:239) (257:257:257))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1288:1288:1288) (1231:1231:1231))
+        (PORT datab (1192:1192:1192) (1083:1083:1083))
+        (PORT datad (257:257:257) (287:287:287))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (451:451:451))
+        (PORT datad (535:535:535) (565:565:565))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (536:536:536) (566:566:566))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (450:450:450))
+        (PORT datab (345:345:345) (428:428:428))
+        (PORT datad (537:537:537) (568:568:568))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (310:310:310) (402:402:402))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1680:1680:1680) (1629:1629:1629))
+        (PORT datad (258:258:258) (287:287:287))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1678:1678:1678) (1628:1628:1628))
+        (PORT datab (298:298:298) (330:330:330))
+        (PORT datad (532:532:532) (561:561:561))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (820:820:820) (814:814:814))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datad (819:819:819) (814:814:814))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (848:848:848) (843:843:843))
+        (PORT datab (315:315:315) (345:345:345))
+        (PORT datad (314:314:314) (394:394:394))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1848:1848:1848) (1858:1858:1858))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1880:1880:1880) (1849:1849:1849))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (868:868:868))
+        (PORT datab (374:374:374) (456:456:456))
+        (PORT datac (792:792:792) (770:770:770))
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (459:459:459))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (319:319:319) (413:413:413))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (463:463:463))
+        (PORT datab (353:353:353) (442:442:442))
+        (PORT datac (311:311:311) (400:400:400))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (904:904:904) (878:878:878))
+        (PORT datab (585:585:585) (616:616:616))
+        (PORT datac (588:588:588) (606:606:606))
+        (PORT datad (489:489:489) (460:460:460))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (292:292:292) (332:332:332))
+        (PORT datab (584:584:584) (615:615:615))
+        (PORT datac (586:586:586) (604:604:604))
+        (PORT datad (493:493:493) (465:465:465))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (327:327:327))
+        (PORT datab (534:534:534) (498:498:498))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (266:266:266) (283:283:283))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (522:522:522))
+        (PORT datab (760:760:760) (709:709:709))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1857:1857:1857) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1889:1889:1889) (1864:1864:1864))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_cs_n\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1224:1224:1224) (1093:1093:1093))
+        (PORT datac (293:293:293) (370:370:370))
+        (PORT datad (822:822:822) (800:800:800))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (926:926:926) (876:876:876))
+        (PORT datad (868:868:868) (815:815:815))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1877:1877:1877))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1893:1893:1893) (1868:1868:1868))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (569:569:569) (605:605:605))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (319:319:319) (413:413:413))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (PORT sclr (1621:1621:1621) (1681:1681:1681))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (483:483:483))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datac (320:320:320) (414:414:414))
+        (PORT datad (312:312:312) (395:395:395))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (482:482:482))
+        (PORT datab (304:304:304) (328:328:328))
+        (PORT datac (239:239:239) (266:266:266))
+        (PORT datad (968:968:968) (962:962:962))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1841:1841:1841) (1853:1853:1853))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1874:1874:1874) (1844:1844:1844))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (239:239:239) (266:266:266))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (480:480:480))
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (430:430:430))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (377:377:377) (465:465:465))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (375:375:375) (485:485:485))
+        (PORT datab (278:278:278) (303:303:303))
+        (PORT datad (265:265:265) (301:301:301))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|bit_cnt\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (480:480:480))
+        (PORT datab (381:381:381) (470:470:470))
+        (PORT datac (239:239:239) (266:266:266))
+        (PORT datad (263:263:263) (298:298:298))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (435:435:435))
+        (PORT datab (341:341:341) (423:423:423))
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (600:600:600))
+        (PORT datab (341:341:341) (420:420:420))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (574:574:574) (606:606:606))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (377:377:377))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (629:629:629) (644:644:644))
+        (PORT datab (855:855:855) (844:844:844))
+        (PORT datac (536:536:536) (560:560:560))
+        (PORT datad (527:527:527) (551:551:551))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (557:557:557) (518:518:518))
+        (PORT datab (636:636:636) (650:650:650))
+        (PORT datac (501:501:501) (478:478:478))
+        (PORT datad (734:734:734) (661:661:661))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|work_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|work_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (280:280:280) (306:306:306))
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (422:422:422))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (436:436:436))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (351:351:351) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (352:352:352) (435:435:435))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (351:351:351) (440:440:440))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (449:449:449))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (PORT sclr (1131:1131:1131) (1151:1151:1151))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (451:451:451))
+        (PORT datab (351:351:351) (440:440:440))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (312:312:312) (392:392:392))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (811:811:811) (727:727:727))
+        (PORT datab (635:635:635) (648:648:648))
+        (PORT datac (506:506:506) (483:483:483))
+        (PORT datad (449:449:449) (422:422:422))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_rx_inst\|always4\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (306:306:306) (344:344:344))
+        (PORT datac (331:331:331) (437:437:437))
+        (PORT datad (527:527:527) (549:549:549))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|rx_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1864:1864:1864) (1881:1881:1881))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1896:1896:1896) (1872:1872:1872))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_rx_inst\|po_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1440:1440:1440) (1427:1427:1427))
+        (PORT clrn (1883:1883:1883) (1862:1862:1862))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1319:1319:1319) (1273:1273:1273))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1475:1475:1475) (1423:1423:1423))
+        (PORT datab (1359:1359:1359) (1341:1341:1341))
+        (PORT datac (864:864:864) (825:825:825))
+        (PORT datad (1466:1466:1466) (1446:1446:1446))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (238:238:238) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (324:324:324) (365:365:365))
+        (PORT datad (349:349:349) (433:433:433))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1475:1475:1475) (1423:1423:1423))
+        (PORT datab (1357:1357:1357) (1339:1339:1339))
+        (PORT datac (864:864:864) (825:825:825))
+        (PORT datad (1465:1465:1465) (1444:1444:1444))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (392:392:392) (485:485:485))
+        (PORT datab (591:591:591) (614:614:614))
+        (PORT datad (465:465:465) (440:440:440))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (463:463:463))
+        (PORT datab (387:387:387) (479:479:479))
+        (PORT datac (279:279:279) (316:316:316))
+        (PORT datad (348:348:348) (431:431:431))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (481:481:481))
+        (PORT datad (255:255:255) (279:279:279))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (477:477:477))
+        (PORT datac (346:346:346) (443:443:443))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (386:386:386) (485:485:485))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1326:1326:1326) (1309:1309:1309))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (322:322:322))
+        (PORT datad (534:534:534) (571:571:571))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (539:539:539) (558:558:558))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1319:1319:1319) (1260:1260:1260))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1271:1271:1271) (1218:1218:1218))
+        (PORT datab (984:984:984) (967:967:967))
+        (PORT datad (318:318:318) (396:396:396))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (569:569:569) (587:587:587))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1309:1309:1309) (1255:1255:1255))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (545:545:545) (568:568:568))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (307:307:307) (348:348:348))
+        (PORT datab (379:379:379) (465:465:465))
+        (PORT datad (548:548:548) (559:559:559))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (550:550:550) (573:573:573))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1365:1365:1365) (1346:1346:1346))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (792:792:792) (771:771:771))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (761:761:761) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT asdata (812:812:812) (900:900:900))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (978:978:978) (994:994:994))
+        (PORT datab (367:367:367) (447:447:447))
+        (PORT datad (973:973:973) (975:975:975))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT asdata (810:810:810) (898:898:898))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1023:1023:1023) (1040:1040:1040))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (861:861:861))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (507:507:507) (532:532:532))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (975:975:975) (990:990:990))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (597:597:597) (608:608:608))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1715:1715:1715) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (662:662:662) (670:670:670))
+        (PORT datab (1009:1009:1009) (992:992:992))
+        (PORT datad (301:301:301) (378:378:378))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (278:278:278) (310:310:310))
+        (PORT datab (859:859:859) (797:797:797))
+        (PORT datac (442:442:442) (422:422:422))
+        (PORT datad (809:809:809) (756:756:756))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (1457:1457:1457) (1407:1407:1407))
+        (PORT datac (1269:1269:1269) (1186:1186:1186))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (587:587:587) (625:625:625))
+        (PORT datab (388:388:388) (481:481:481))
+        (PORT datad (889:889:889) (847:847:847))
+        (IOPATH dataa combout (405:405:405) (407:407:407))
+        (IOPATH datab combout (410:410:410) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1464:1464:1464) (1423:1423:1423))
+        (PORT datab (388:388:388) (481:481:481))
+        (PORT datac (346:346:346) (425:425:425))
+        (PORT datad (1306:1306:1306) (1274:1274:1274))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (382:382:382) (480:480:480))
+        (PORT datad (246:246:246) (267:267:267))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1385:1385:1385) (1356:1356:1356))
+        (PORT datad (1284:1284:1284) (1241:1241:1241))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (461:461:461))
+        (PORT datab (385:385:385) (478:478:478))
+        (PORT datac (282:282:282) (320:320:320))
+        (PORT datad (348:348:348) (432:432:432))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (240:240:240) (259:259:259))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (481:481:481))
+        (PORT datab (387:387:387) (481:481:481))
+        (PORT datac (346:346:346) (443:443:443))
+        (PORT datad (578:578:578) (612:612:612))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1669:1669:1669) (1588:1588:1588))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (296:296:296) (375:375:375))
+        (PORT datad (1311:1311:1311) (1267:1267:1267))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (481:481:481))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1184:1184:1184) (1141:1141:1141))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (971:971:971) (997:997:997))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1446:1446:1446) (1416:1416:1416))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (803:803:803) (883:883:883))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (542:542:542) (562:562:562))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (973:973:973))
+        (PORT datab (936:936:936) (925:925:925))
+        (PORT datad (295:295:295) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (288:288:288) (326:326:326))
+        (PORT datab (334:334:334) (410:410:410))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (325:325:325))
+        (PORT datab (898:898:898) (822:822:822))
+        (PORT datad (246:246:246) (268:268:268))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (910:910:910) (883:883:883))
+        (PORT datab (892:892:892) (866:866:866))
+        (PORT datac (752:752:752) (678:678:678))
+        (PORT datad (506:506:506) (532:532:532))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (576:576:576) (620:620:620))
+        (PORT datab (377:377:377) (467:467:467))
+        (PORT datac (552:552:552) (579:579:579))
+        (PORT datad (263:263:263) (295:295:295))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (389:389:389) (486:486:486))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (620:620:620))
+        (PORT datab (387:387:387) (484:484:484))
+        (PORT datac (355:355:355) (439:439:439))
+        (PORT datad (528:528:528) (565:565:565))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (913:913:913) (886:886:886))
+        (PORT datab (380:380:380) (470:470:470))
+        (PORT datac (855:855:855) (834:834:834))
+        (PORT datad (337:337:337) (421:421:421))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (424:424:424))
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datac (297:297:297) (375:375:375))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1595:1595:1595) (1481:1481:1481))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (860:860:860) (862:862:862))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1377:1377:1377) (1332:1332:1332))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (PORT datab (368:368:368) (450:450:450))
+        (PORT datac (532:532:532) (516:516:516))
+        (PORT datad (859:859:859) (861:861:861))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (711:711:711) (642:642:642))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (381:381:381) (467:467:467))
+        (PORT datad (263:263:263) (295:295:295))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (620:620:620))
+        (PORT datab (378:378:378) (468:468:468))
+        (PORT datac (552:552:552) (579:579:579))
+        (PORT datad (264:264:264) (296:296:296))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (601:601:601) (636:636:636))
+        (PORT datab (387:387:387) (483:483:483))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (387:387:387) (483:483:483))
+        (PORT datac (351:351:351) (434:434:434))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (575:575:575) (615:615:615))
+        (PORT datad (245:245:245) (270:270:270))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1051:1051:1051) (1058:1058:1058))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1656:1656:1656) (1603:1603:1603))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (764:764:764) (833:833:833))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (759:759:759) (828:828:828))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (314:314:314) (402:402:402))
+        (PORT datad (324:324:324) (404:404:404))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (477:477:477))
+        (PORT datab (392:392:392) (486:486:486))
+        (PORT datad (254:254:254) (279:279:279))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1856:1856:1856) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1474:1474:1474) (1459:1459:1459))
+        (PORT ena (1575:1575:1575) (1483:1483:1483))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1286:1286:1286) (1243:1243:1243))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1838:1838:1838) (1855:1855:1855))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1681:1681:1681) (1604:1604:1604))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1330:1330:1330) (1283:1283:1283))
+        (PORT datac (356:356:356) (441:441:441))
+        (PORT datad (1211:1211:1211) (1150:1150:1150))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (434:434:434))
+        (PORT datab (341:341:341) (420:420:420))
+        (PORT datac (307:307:307) (394:394:394))
+        (PORT datad (319:319:319) (398:398:398))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1429:1429:1429) (1386:1386:1386))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1328:1328:1328) (1280:1280:1280))
+        (PORT datab (1249:1249:1249) (1190:1190:1190))
+        (PORT datac (353:353:353) (438:438:438))
+        (PORT datad (946:946:946) (938:938:938))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (330:330:330) (413:413:413))
+        (PORT datad (829:829:829) (787:787:787))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1457:1457:1457) (1419:1419:1419))
+        (PORT datac (332:332:332) (416:416:416))
+        (PORT datad (826:826:826) (784:784:784))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1848:1848:1848) (1802:1802:1802))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1456:1456:1456) (1418:1418:1418))
+        (PORT datab (1660:1660:1660) (1584:1584:1584))
+        (PORT datac (328:328:328) (411:411:411))
+        (PORT datad (827:827:827) (785:785:785))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (543:543:543) (569:569:569))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1321:1321:1321) (1319:1319:1319))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (798:798:798) (777:777:777))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT asdata (1055:1055:1055) (1064:1064:1064))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT asdata (1680:1680:1680) (1608:1608:1608))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (846:846:846) (809:809:809))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (762:762:762) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (PORT datab (550:550:550) (578:578:578))
+        (PORT datac (327:327:327) (411:411:411))
+        (PORT datad (1572:1572:1572) (1421:1421:1421))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (900:900:900) (854:854:854))
+        (PORT datad (734:734:734) (669:669:669))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT asdata (1772:1772:1772) (1735:1735:1735))
+        (PORT ena (1747:1747:1747) (1669:1669:1669))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (297:297:297) (335:335:335))
+        (PORT datac (339:339:339) (428:428:428))
+        (PORT datad (553:553:553) (586:586:586))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (595:595:595) (566:566:566))
+        (PORT datab (370:370:370) (454:454:454))
+        (PORT datad (861:861:861) (863:863:863))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1871:1871:1871))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (833:833:833) (808:808:808))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1585:1585:1585) (1456:1456:1456))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1179:1179:1179) (1120:1120:1120))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1869:1869:1869))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT asdata (1284:1284:1284) (1237:1237:1237))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (858:858:858) (826:826:826))
+        (PORT datab (354:354:354) (441:441:441))
+        (PORT datac (358:358:358) (443:443:443))
+        (PORT datad (272:272:272) (292:292:292))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1868:1868:1868))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (859:859:859) (826:826:826))
+        (PORT datab (1206:1206:1206) (1153:1153:1153))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (902:902:902) (904:904:904))
+        (PORT datab (602:602:602) (609:609:609))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (554:554:554) (593:593:593))
+        (PORT datab (955:955:955) (929:929:929))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (612:612:612) (620:620:620))
+        (PORT datab (883:883:883) (885:885:885))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (336:336:336) (419:419:419))
+        (PORT datab (532:532:532) (559:559:559))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (421:421:421))
+        (PORT datad (528:528:528) (549:549:549))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (488:488:488) (478:478:478))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (239:239:239) (257:257:257))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (1983:1983:1983) (1881:1881:1881))
+        (PORT datac (237:237:237) (263:263:263))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|comb\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (314:314:314))
+        (PORT datab (279:279:279) (305:305:305))
+        (PORT datac (235:235:235) (261:261:261))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2015:2015:2015) (1838:1838:1838))
+        (PORT datab (370:370:370) (452:452:452))
+        (PORT datac (1631:1631:1631) (1576:1576:1576))
+        (PORT datad (826:826:826) (791:791:791))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (894:894:894) (834:834:834))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (836:836:836) (776:776:776))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1849:1849:1849) (1859:1859:1859))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1881:1881:1881) (1850:1850:1850))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (450:450:450))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (455:455:455))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (446:446:446))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (464:464:464))
+        (PORT datab (359:359:359) (455:455:455))
+        (PORT datac (318:318:318) (412:412:412))
+        (PORT datad (321:321:321) (404:404:404))
+        (IOPATH dataa combout (453:453:453) (472:472:472))
+        (IOPATH datab combout (455:455:455) (473:473:473))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (448:448:448))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (PORT sclr (2551:2551:2551) (2696:2696:2696))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (319:319:319) (415:415:415))
+        (PORT datad (320:320:320) (407:407:407))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (357:357:357) (452:452:452))
+        (PORT datac (317:317:317) (411:411:411))
+        (PORT datad (318:318:318) (401:401:401))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (360:360:360) (449:449:449))
+        (PORT datac (319:319:319) (415:415:415))
+        (PORT datad (248:248:248) (271:271:271))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (490:490:490) (475:475:475))
+        (PORT datac (1968:1968:1968) (1887:1887:1887))
+        (PORT datad (783:783:783) (726:726:726))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (918:918:918) (904:904:904))
+        (PORT datab (2008:2008:2008) (1923:1923:1923))
+        (PORT datac (1946:1946:1946) (1865:1865:1865))
+        (PORT datad (539:539:539) (560:560:560))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (PORT datab (2010:2010:2010) (1925:1925:1925))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1879:1879:1879))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1870:1870:1870))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (885:885:885) (868:868:868))
+        (PORT datab (941:941:941) (925:925:925))
+        (PORT datac (1707:1707:1707) (1633:1633:1633))
+        (PORT datad (334:334:334) (414:414:414))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_mosi\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (849:849:849) (846:846:846))
+        (PORT datac (895:895:895) (881:881:881))
+        (PORT datad (236:236:236) (254:254:254))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (2339:2339:2339) (2308:2308:2308))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (913:913:913) (928:928:928))
+        (PORT datab (341:341:341) (420:420:420))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (434:434:434))
+        (PORT datab (343:343:343) (425:425:425))
+        (PORT datac (300:300:300) (384:384:384))
+        (PORT datad (301:301:301) (376:376:376))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (888:888:888) (888:888:888))
+        (PORT datab (865:865:865) (770:770:770))
+        (PORT datac (903:903:903) (887:887:887))
+        (PORT datad (931:931:931) (902:902:902))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (442:442:442))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (453:453:453))
+        (PORT datab (352:352:352) (442:442:442))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (313:313:313) (394:394:394))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal1\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (959:959:959) (944:944:944))
+        (PORT datac (911:911:911) (901:901:901))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (932:932:932) (925:925:925))
+        (PORT datab (289:289:289) (318:318:318))
+        (PORT datac (813:813:813) (755:755:755))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (348:348:348) (433:433:433))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (350:350:350) (440:440:440))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (449:449:449))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|baud_cnt\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1497:1497:1497) (1499:1499:1499))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (453:453:453))
+        (PORT datab (352:352:352) (441:441:441))
+        (PORT datac (312:312:312) (402:402:402))
+        (PORT datad (313:313:313) (393:393:393))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (960:960:960) (945:945:945))
+        (PORT datab (965:965:965) (941:941:941))
+        (PORT datac (1124:1124:1124) (990:990:990))
+        (PORT datad (248:248:248) (275:275:275))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_flag)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1193:1193:1193) (1146:1146:1146))
+        (PORT datad (1187:1187:1187) (1123:1123:1123))
+        (IOPATH dataa combout (421:421:421) (428:428:428))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|always0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (327:327:327))
+        (PORT datab (1249:1249:1249) (1173:1173:1173))
+        (PORT datac (347:347:347) (466:466:466))
+        (PORT datad (310:310:310) (393:393:393))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1193:1193:1193) (1147:1147:1147))
+        (PORT datab (1252:1252:1252) (1177:1177:1177))
+        (PORT datad (291:291:291) (326:326:326))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (377:377:377))
+        (PORT datab (391:391:391) (507:507:507))
+        (PORT datad (256:256:256) (289:289:289))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (602:602:602))
+        (PORT datab (353:353:353) (439:439:439))
+        (PORT datac (350:350:350) (470:470:470))
+        (PORT datad (346:346:346) (446:446:446))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (377:377:377))
+        (PORT datab (297:297:297) (332:332:332))
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH datab combout (455:455:455) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|bit_cnt\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (434:434:434))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (445:445:445))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (632:632:632) (648:648:648))
+        (PORT datac (854:854:854) (833:833:833))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_busy_dly)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT asdata (1677:1677:1677) (1619:1619:1619))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (418:418:418))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (421:421:421))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (420:420:420))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (304:304:304) (381:381:381))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (431:431:431))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1850:1850:1850) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1882:1882:1882) (1855:1855:1855))
+        (PORT sclr (1580:1580:1580) (1648:1648:1648))
+        (PORT ena (1638:1638:1638) (1553:1553:1553))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (436:436:436))
+        (PORT datab (343:343:343) (426:426:426))
+        (PORT datac (302:302:302) (386:386:386))
+        (PORT datad (303:303:303) (380:380:380))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|always3\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (494:494:494) (472:472:472))
+        (PORT datab (277:277:277) (302:302:302))
+        (PORT datac (236:236:236) (262:262:262))
+        (PORT datad (839:839:839) (785:785:785))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1317:1317:1317) (1271:1271:1271))
+        (PORT datab (337:337:337) (414:414:414))
+        (PORT datad (1043:1043:1043) (938:938:938))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|send_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (628:628:628) (642:642:642))
+        (PORT datab (578:578:578) (602:602:602))
+        (PORT datac (527:527:527) (561:561:561))
+        (PORT datad (559:559:559) (579:579:579))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (289:289:289) (324:324:324))
+        (PORT datab (279:279:279) (305:305:305))
+        (PORT datac (320:320:320) (398:398:398))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (434:434:434))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (624:624:624) (638:638:638))
+        (PORT datab (575:575:575) (599:599:599))
+        (PORT datac (524:524:524) (557:557:557))
+        (PORT datad (556:556:556) (575:575:575))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (446:446:446))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (360:360:360) (437:437:437))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (446:446:446))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (573:573:573) (600:600:600))
+        (PORT datab (559:559:559) (585:585:585))
+        (PORT datac (533:533:533) (549:549:549))
+        (PORT datad (552:552:552) (570:570:570))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1864:1864:1864))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1855:1855:1855))
+        (PORT sclr (1121:1121:1121) (1143:1143:1143))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (836:836:836) (819:819:819))
+        (PORT datab (617:617:617) (622:622:622))
+        (PORT datac (787:787:787) (765:765:765))
+        (PORT datad (522:522:522) (541:541:541))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1524:1524:1524) (1455:1455:1455))
+        (PORT datab (558:558:558) (583:583:583))
+        (PORT datac (237:237:237) (264:264:264))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (392:392:392) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|Equal2\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (632:632:632) (648:648:648))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (854:854:854) (833:833:833))
+        (PORT datad (245:245:245) (269:269:269))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (410:410:410) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (311:311:311))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (379:379:379) (466:466:466))
+        (PORT datac (348:348:348) (447:447:447))
+        (PORT datad (254:254:254) (278:278:278))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (377:377:377) (467:467:467))
+        (PORT datad (245:245:245) (266:266:266))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (881:881:881) (867:867:867))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (886:886:886))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (916:916:916) (915:915:915))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1140:1140:1140) (1130:1130:1130))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1322:1322:1322) (1307:1307:1307))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (760:760:760) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (1407:1407:1407) (1398:1398:1398))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (865:865:865) (853:853:853))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1265:1265:1265) (1225:1225:1225))
+        (PORT datab (361:361:361) (438:438:438))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (591:591:591) (628:628:628))
+        (PORT datab (359:359:359) (453:453:453))
+        (PORT datac (339:339:339) (429:429:429))
+        (PORT datad (318:318:318) (405:405:405))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (298:298:298) (343:343:343))
+        (PORT datab (472:472:472) (455:455:455))
+        (PORT datac (511:511:511) (483:483:483))
+        (PORT datad (573:573:573) (594:594:594))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1367:1367:1367) (1362:1362:1362))
+        (PORT datab (368:368:368) (464:464:464))
+        (PORT datac (484:484:484) (459:459:459))
+        (PORT datad (275:275:275) (297:297:297))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1863:1863:1863))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1854:1854:1854))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1441:1441:1441) (1423:1423:1423))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (762:762:762) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (857:857:857))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1676:1676:1676) (1565:1565:1565))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT asdata (789:789:789) (859:859:859))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (549:549:549) (576:576:576))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (626:626:626))
+        (PORT datab (631:631:631) (635:635:635))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (931:931:931) (925:925:925))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (1884:1884:1884) (1779:1779:1779))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT asdata (1410:1410:1410) (1388:1388:1388))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (462:462:462))
+        (PORT datab (377:377:377) (465:465:465))
+        (PORT datac (500:500:500) (480:480:480))
+        (PORT datad (338:338:338) (415:415:415))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1232:1232:1232))
+        (PORT datab (983:983:983) (947:947:947))
+        (PORT datad (282:282:282) (305:305:305))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (598:598:598) (609:609:609))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1134:1134:1134) (1128:1128:1128))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (842:842:842) (825:825:825))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (939:939:939) (923:923:923))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (937:937:937))
+        (PORT datab (549:549:549) (585:585:585))
+        (PORT datad (294:294:294) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (810:810:810) (811:811:811))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (786:786:786) (856:856:856))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (323:323:323) (394:394:394))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (334:334:334) (408:408:408))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (321:321:321) (391:391:391))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (298:298:298) (368:368:368))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (555:555:555) (594:594:594))
+        (PORT datab (887:887:887) (893:893:893))
+        (PORT datad (294:294:294) (364:364:364))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (310:310:310))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (236:236:236) (263:263:263))
+        (PORT datad (834:834:834) (764:764:764))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (286:286:286) (318:318:318))
+        (PORT datac (1848:1848:1848) (1742:1742:1742))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (886:886:886))
+        (PORT datab (379:379:379) (470:470:470))
+        (PORT datad (781:781:781) (719:719:719))
+        (IOPATH dataa combout (405:405:405) (407:407:407))
+        (IOPATH datab combout (410:410:410) (412:412:412))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (948:948:948) (954:954:954))
+        (PORT datab (565:565:565) (600:600:600))
+        (PORT datac (300:300:300) (330:330:330))
+        (PORT datad (909:909:909) (908:908:908))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (945:945:945) (945:945:945))
+        (PORT datab (856:856:856) (861:861:861))
+        (PORT datad (792:792:792) (723:723:723))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (856:856:856) (862:862:862))
+        (PORT datad (792:792:792) (723:723:723))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (854:854:854) (826:826:826))
+        (PORT datab (956:956:956) (958:958:958))
+        (PORT datac (828:828:828) (828:828:828))
+        (PORT datad (459:459:459) (433:433:433))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (990:990:990) (971:971:971))
+        (PORT datad (252:252:252) (276:276:276))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (922:922:922) (927:927:927))
+        (PORT datab (363:363:363) (456:456:456))
+        (PORT datac (324:324:324) (420:420:420))
+        (PORT datad (933:933:933) (927:927:927))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (993:993:993) (974:974:974))
+        (PORT datac (322:322:322) (418:418:418))
+        (PORT datad (256:256:256) (281:281:281))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (454:454:454))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (424:424:424))
+        (PORT datac (515:515:515) (545:545:545))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (944:944:944) (944:944:944))
+        (PORT datab (380:380:380) (470:470:470))
+        (PORT datac (324:324:324) (403:403:403))
+        (PORT datad (817:817:817) (819:819:819))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (297:297:297) (375:375:375))
+        (PORT datad (863:863:863) (858:858:858))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1893:1893:1893) (1790:1790:1790))
+        (PORT datab (288:288:288) (320:320:320))
+        (PORT datac (523:523:523) (561:561:561))
+        (PORT datad (248:248:248) (270:270:270))
+        (IOPATH dataa combout (448:448:448) (472:472:472))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (949:949:949) (954:954:954))
+        (PORT datab (973:973:973) (961:961:961))
+        (PORT datad (238:238:238) (257:257:257))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1861:1861:1861) (1874:1874:1874))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (461:461:461))
+        (PORT datab (852:852:852) (856:856:856))
+        (PORT datac (791:791:791) (707:707:707))
+        (PORT datad (874:874:874) (886:886:886))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (459:459:459))
+        (PORT datab (991:991:991) (971:971:971))
+        (PORT datad (253:253:253) (277:277:277))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (361:361:361) (454:454:454))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (982:982:982) (1003:1003:1003))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (787:787:787) (856:856:856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1238:1238:1238) (1206:1206:1206))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (760:760:760) (829:829:829))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (305:305:305) (382:382:382))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (802:802:802) (780:780:780))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (299:299:299) (369:369:369))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (831:831:831) (825:825:825))
+        (PORT datab (613:613:613) (617:617:617))
+        (PORT datad (791:791:791) (760:760:760))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (1332:1332:1332) (1310:1310:1310))
+        (PORT ena (1347:1347:1347) (1288:1288:1288))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (319:319:319) (410:410:410))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (831:831:831) (807:807:807))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1873:1873:1873))
+        (PORT asdata (787:787:787) (873:873:873))
+        (PORT ena (1285:1285:1285) (1213:1213:1213))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (831:831:831) (800:800:800))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT asdata (761:761:761) (830:830:830))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (296:296:296) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1874:1874:1874) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (431:431:431))
+        (PORT datab (575:575:575) (591:591:591))
+        (PORT datad (294:294:294) (363:363:363))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (462:462:462))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (537:537:537) (566:566:566))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (964:964:964) (958:958:958))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT asdata (763:763:763) (832:832:832))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (874:874:874) (885:885:885))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT asdata (1597:1597:1597) (1523:1523:1523))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1860:1860:1860) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (912:912:912) (883:883:883))
+        (PORT datab (1184:1184:1184) (1107:1107:1107))
+        (PORT datad (295:295:295) (365:365:365))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (312:312:312))
+        (PORT datab (276:276:276) (301:301:301))
+        (PORT datac (448:448:448) (424:424:424))
+        (PORT datad (770:770:770) (705:705:705))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1118:1118:1118) (1020:1020:1020))
+        (PORT datab (1834:1834:1834) (1684:1684:1684))
+        (PORT datac (243:243:243) (274:274:274))
+        (PORT datad (247:247:247) (269:269:269))
+        (IOPATH dataa combout (432:432:432) (446:446:446))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1419:1419:1419) (1410:1410:1410))
+        (PORT datab (991:991:991) (977:977:977))
+        (PORT datac (1194:1194:1194) (1158:1158:1158))
+        (PORT datad (827:827:827) (769:769:769))
+        (IOPATH dataa combout (405:405:405) (398:398:398))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (240:240:240) (258:258:258))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (833:833:833))
+        (PORT datad (329:329:329) (402:402:402))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1309:1309:1309) (1230:1230:1230))
+        (PORT datab (982:982:982) (946:946:946))
+        (PORT datac (359:359:359) (447:447:447))
+        (PORT datad (282:282:282) (305:305:305))
+        (IOPATH dataa combout (392:392:392) (407:407:407))
+        (IOPATH datab combout (393:393:393) (412:412:412))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (390:390:390) (492:492:492))
+        (PORT datad (255:255:255) (280:280:280))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (395:395:395) (498:498:498))
+        (PORT datab (381:381:381) (468:468:468))
+        (PORT datad (252:252:252) (277:277:277))
+        (IOPATH dataa combout (421:421:421) (418:418:418))
+        (IOPATH datab combout (407:407:407) (408:408:408))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (380:380:380) (471:471:471))
+        (PORT datad (246:246:246) (268:268:268))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (448:448:448))
+        (PORT datad (320:320:320) (391:391:391))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (391:391:391) (494:494:494))
+        (PORT datab (379:379:379) (469:469:469))
+        (PORT datac (363:363:363) (451:451:451))
+        (PORT datad (339:339:339) (423:423:423))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (462:462:462))
+        (PORT datab (980:980:980) (943:943:943))
+        (PORT datac (340:340:340) (433:433:433))
+        (PORT datad (1242:1242:1242) (1176:1176:1176))
+        (IOPATH dataa combout (461:461:461) (486:486:486))
+        (IOPATH datab combout (473:473:473) (489:489:489))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (413:413:413))
+        (PORT datac (296:296:296) (374:374:374))
+        (PORT datad (498:498:498) (525:525:525))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (340:340:340) (417:417:417))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1293:1293:1293) (1242:1242:1242))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (566:566:566) (533:533:533))
+        (PORT datab (382:382:382) (471:471:471))
+        (PORT datad (338:338:338) (415:415:415))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1888:1888:1888))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1859:1859:1859) (1872:1872:1872))
+        (PORT asdata (1840:1840:1840) (1817:1817:1817))
+        (PORT ena (1387:1387:1387) (1333:1333:1333))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (379:379:379) (469:469:469))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT asdata (761:761:761) (831:831:831))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1290:1290:1290) (1255:1255:1255))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (1280:1280:1280) (1245:1245:1245))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT asdata (972:972:972) (990:990:990))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (297:297:297) (367:367:367))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1873:1873:1873) (1889:1889:1889))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (904:904:904) (869:869:869))
+        (PORT datab (934:934:934) (890:890:890))
+        (PORT datad (293:293:293) (362:362:362))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1832:1832:1832) (1682:1682:1682))
+        (PORT datac (247:247:247) (278:278:278))
+        (PORT datad (245:245:245) (267:267:267))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4197:4197:4197) (4406:4406:4406))
+        (PORT datab (1234:1234:1234) (1141:1141:1141))
+        (PORT datac (1266:1266:1266) (1240:1240:1240))
+        (PORT datad (882:882:882) (857:857:857))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1338:1338:1338) (1323:1323:1323))
+        (PORT datad (928:928:928) (924:924:924))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1364:1364:1364) (1359:1359:1359))
+        (PORT datab (364:364:364) (459:459:459))
+        (PORT datac (484:484:484) (458:458:458))
+        (PORT datad (275:275:275) (297:297:297))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (437:437:437) (436:436:436))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1313:1313:1313) (1290:1290:1290))
+        (PORT datab (926:926:926) (902:902:902))
+        (PORT datac (1179:1179:1179) (1102:1102:1102))
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1311:1311:1311) (1288:1288:1288))
+        (PORT datab (925:925:925) (900:900:900))
+        (PORT datac (1182:1182:1182) (1106:1106:1106))
+        (PORT datad (322:322:322) (392:392:392))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1286:1286:1286))
+        (PORT datab (924:924:924) (899:899:899))
+        (PORT datac (1184:1184:1184) (1108:1108:1108))
+        (PORT datad (323:323:323) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1310:1310:1310) (1286:1286:1286))
+        (PORT datab (924:924:924) (899:899:899))
+        (PORT datac (1183:1183:1183) (1108:1108:1108))
+        (PORT datad (322:322:322) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1309:1309:1309) (1285:1285:1285))
+        (PORT datab (923:923:923) (898:898:898))
+        (PORT datac (1185:1185:1185) (1109:1109:1109))
+        (PORT datad (323:323:323) (393:393:393))
+        (IOPATH dataa combout (404:404:404) (398:398:398))
+        (IOPATH datab combout (435:435:435) (424:424:424))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1851:1851:1851) (1860:1860:1860))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1883:1883:1883) (1851:1851:1851))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1274:1274:1274) (1194:1194:1194))
+        (PORT datab (1308:1308:1308) (1219:1219:1219))
+        (PORT datac (1626:1626:1626) (1583:1583:1583))
+        (PORT datad (911:911:911) (907:907:907))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1274:1274:1274) (1194:1194:1194))
+        (PORT datab (1307:1307:1307) (1219:1219:1219))
+        (PORT datac (1625:1625:1625) (1582:1582:1582))
+        (PORT datad (304:304:304) (377:377:377))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1676:1676:1676) (1642:1642:1642))
+        (PORT datab (1308:1308:1308) (1219:1219:1219))
+        (PORT datac (304:304:304) (389:389:389))
+        (PORT datad (1202:1202:1202) (1134:1134:1134))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1635:1635:1635) (1594:1594:1594))
+        (PORT datad (306:306:306) (380:380:380))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (331:331:331) (409:409:409))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1858:1858:1858) (1872:1872:1872))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1588:1588:1588) (1477:1477:1477))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (320:320:320) (390:390:390))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1875:1875:1875) (1890:1890:1890))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT ena (1676:1676:1676) (1565:1565:1565))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (303:303:303) (379:379:379))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (986:986:986) (971:971:971))
+        (PORT datac (1344:1344:1344) (1330:1330:1330))
+        (IOPATH datab combout (455:455:455) (436:436:436))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1339:1339:1339) (1324:1324:1324))
+        (PORT datad (887:887:887) (885:885:885))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1352:1352:1352) (1339:1339:1339))
+        (PORT datad (931:931:931) (921:921:921))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1350:1350:1350) (1337:1337:1337))
+        (PORT datad (944:944:944) (934:934:934))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1627:1627:1627) (1584:1584:1584))
+        (PORT datad (911:911:911) (908:908:908))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1633:1633:1633) (1592:1592:1592))
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (435:435:435))
+        (PORT datac (1624:1624:1624) (1581:1581:1581))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1272:1272:1272) (1191:1191:1191))
+        (PORT datab (1309:1309:1309) (1221:1221:1221))
+        (PORT datac (1632:1632:1632) (1590:1590:1590))
+        (PORT datad (305:305:305) (379:379:379))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1622:1622:1622) (1578:1578:1578))
+        (PORT datad (307:307:307) (381:381:381))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (438:438:438))
+        (PORT datac (1632:1632:1632) (1591:1591:1591))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (440:440:440))
+        (PORT datac (1634:1634:1634) (1593:1593:1593))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1940:1940:1940) (1799:1799:1799))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (921:921:921) (907:907:907))
+        (PORT datac (1349:1349:1349) (1336:1336:1336))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (924:924:924) (911:911:911))
+        (PORT datab (1178:1178:1178) (1103:1103:1103))
+        (PORT datac (1342:1342:1342) (1328:1328:1328))
+        (PORT datad (860:860:860) (819:819:819))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1348:1348:1348) (1334:1334:1334))
+        (PORT datad (305:305:305) (378:378:378))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (440:440:440))
+        (PORT datac (1351:1351:1351) (1338:1338:1338))
+        (IOPATH dataa combout (453:453:453) (446:446:446))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (438:438:438))
+        (PORT datab (1177:1177:1177) (1103:1103:1103))
+        (PORT datac (1343:1343:1343) (1329:1329:1329))
+        (PORT datad (860:860:860) (819:819:819))
+        (IOPATH dataa combout (453:453:453) (413:413:413))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1341:1341:1341) (1326:1326:1326))
+        (PORT datad (296:296:296) (366:366:366))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1852:1852:1852) (1865:1865:1865))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1884:1884:1884) (1856:1856:1856))
+        (PORT ena (1620:1620:1620) (1534:1534:1534))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD ena (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|Mux0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (290:290:290) (328:328:328))
+        (PORT datab (353:353:353) (440:440:440))
+        (PORT datac (351:351:351) (471:471:471))
+        (PORT datad (842:842:842) (786:786:786))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE uart_tx_inst\|tx\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (313:313:313))
+        (PORT datab (1251:1251:1251) (1176:1176:1176))
+        (PORT datad (239:239:239) (258:258:258))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE uart_tx_inst\|tx)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1863:1863:1863) (1876:1876:1876))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT clrn (1895:1895:1895) (1867:1867:1867))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+)
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/clk_gen.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/clk_gen.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/clk_gen.qip
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..bc30615
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt
@@ -0,0 +1,66 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=1
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=1
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=1
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=1
+CLK1_PHASE_SHIFT=6667
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_USED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_USED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+SELF_RESET_ON_LOSS_LOCK=OFF
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone IV E"
+CBX_AUTO_BLACKBOX=ALL
+areset
+inclk
+inclk
+clk
+clk
+locked
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf
new file mode 100644
index 0000000..f5b3989
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
+# Date created = 16:24:33  September 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "16:24:33  September 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "uart_sd"
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf
new file mode 100644
index 0000000..f0d56ba
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf
@@ -0,0 +1,85 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
+# Date created = 16:24:33  September 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		uart_sd_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY uart_sd
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:24:33  SEPTEMBER 05, 2019"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_F8 -to sd_clk
+set_location_assignment PIN_E7 -to sd_cs_n
+set_location_assignment PIN_F7 -to sd_mosi
+set_location_assignment PIN_E9 -to sd_miso
+
+set_location_assignment PIN_T22 -to sys_clk
+set_location_assignment PIN_U20 -to sys_rst_n
+set_location_assignment PIN_V1 -to rx
+set_location_assignment PIN_U1 -to tx
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp/stp1.stp
+set_global_assignment -name VERILOG_FILE ../rtl/data_rw_ctrl.v
+set_global_assignment -name VERILOG_FILE ../rtl/uart_tx.v
+set_global_assignment -name VERILOG_FILE ../rtl/uart_sd.v
+set_global_assignment -name VERILOG_FILE ../rtl/uart_rx.v
+set_global_assignment -name VERILOG_FILE ../rtl/sd_write.v
+set_global_assignment -name VERILOG_FILE ../rtl/sd_read.v
+set_global_assignment -name VERILOG_FILE ../rtl/sd_init.v
+set_global_assignment -name VERILOG_FILE ../rtl/sd_ctrl.v
+set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip
+set_global_assignment -name QIP_FILE ip_core/fifo_wr_data/fifo_wr_data.qip
+set_global_assignment -name QIP_FILE ip_core/fifo_rd_data/fifo_rd_data.qip
+
+set_global_assignment -name SLD_FILE "E:/GitLib/Altera/EP4CE10/base_code/21_uart_sd/quartus_prj/stp/stp1_auto_stripped.stp"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws
new file mode 100644
index 0000000..105501c
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf
new file mode 100644
index 0000000..f091ef2
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf
@@ -0,0 +1,805 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 03:53:43  June 02, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v
new file mode 100644
index 0000000..1bb9f5e
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v
@@ -0,0 +1,191 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : data_rw
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : 读写数据控制模块
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  data_rw_ctrl
+(
+    input   wire            sys_clk     ,   //输入工作时钟,频率50MHz
+    input   wire            sys_rst_n   ,   //输入复位信号,低电平有效
+    input   wire            init_end    ,   //SD卡初始化完成信号
+    
+    input   wire            rx_flag     ,   //写fifo写入数据标志信号
+    input   wire    [7:0]   rx_data     ,   //写fifo写入数据
+    input   wire            wr_req      ,   //sd卡数据写请求
+    input   wire            wr_busy     ,   //sd卡写数据忙信号
+
+    output  wire            wr_en       ,   //sd卡数据写使能信号
+    output  wire    [31:0]  wr_addr     ,   //sd卡写数据扇区地址
+    output  wire    [15:0]  wr_data     ,   //sd卡写数据
+
+    input   wire            rd_data_en  ,   //sd卡读出数据标志信号
+    input   wire    [15:0]  rd_data     ,   //sd卡读出数据
+    input   wire            rd_busy     ,   //sd卡读数据忙信号
+    output  reg             rd_en       ,   //sd卡数据读使能信号
+    output  wire    [31:0]  rd_addr     ,   //sd卡读数据扇区地址
+    output  reg             tx_flag     ,   //读fifo读出数据标志信号
+    output  wire    [7:0]   tx_data         //读fifo读出数据
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   DATA_NUM    =   12'd256     ;   //读写数据个数
+parameter   SECTOR_ADDR =   32'd1000    ;   //读写数据扇区地址
+parameter   CNT_WAIT_MAX=   16'd60000   ;   //读fifo输出数据时间间隔计数最大值
+
+//wire  define
+wire    [11:0]  wr_fifo_data_num    ;   //写fifo内数据个数
+wire            wr_busy_fall        ;   //sd卡写数据忙信号下降沿
+wire            rd_busy_fall        ;   //sd卡读数据忙信号下降沿
+//wire            rd_fifo_rd_en       ;   //读fifo读使能信号
+
+//reg   define
+reg             wr_busy_dly         ;   //sd卡写数据忙信号打一拍
+reg             rd_busy_dly         ;   //sd卡读数据忙信号打一拍
+reg             send_data_en        ;   //串口发送数据使能信号
+reg     [15:0]  cnt_wait            ;   //读fifo输出数据时间间隔计数
+reg     [11:0]  send_data_num       ;   //串口发送数据字节数计数
+reg             rd_fifo_rd_en       ;
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//wr_en:sd卡数据写使能信号
+assign  wr_en = ((wr_fifo_data_num == (DATA_NUM)) && (init_end == 1'b1))
+                ? 1'b1 : 1'b0;
+
+//wr_addr:sd卡写数据扇区地址
+assign  wr_addr = SECTOR_ADDR;
+
+//wr_busy_dly:sd卡写数据忙信号打一拍
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        wr_busy_dly <=  1'b0;
+    else
+        wr_busy_dly <=  wr_busy;
+
+//wr_busy_fall:sd卡写数据忙信号下降沿
+assign  wr_busy_fall = ((wr_busy == 1'b0) && (wr_busy_dly == 1'b1))
+                        ? 1'b1 : 1'b0;
+
+//rd_en:sd卡数据读使能信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rd_en   <=  1'b0;
+    else    if(wr_busy_fall == 1'b1)
+        rd_en   <=  1'b1;
+    else
+        rd_en   <=  1'b0;
+
+//rd_addr:sd卡读数据扇区地址
+assign  rd_addr = SECTOR_ADDR;
+
+//rd_busy_dly:sd卡读数据忙信号打一拍
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rd_busy_dly <=  1'b0;
+    else
+        rd_busy_dly <=  rd_busy;
+
+//rd_busy_fall:sd卡读数据忙信号下降沿
+assign  rd_busy_fall = ((rd_busy == 1'b0) && (rd_busy_dly == 1'b1))
+                        ? 1'b1 : 1'b0;
+
+//send_data_en:串口发送数据使能信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        send_data_en    <=  1'b0;
+    else    if((send_data_num == (DATA_NUM * 2) - 1'b1)
+                && (cnt_wait == CNT_WAIT_MAX - 1'b1))
+        send_data_en    <=  1'b0;
+    else    if(rd_busy_fall == 1'b1)
+        send_data_en    <=  1'b1;
+    else
+        send_data_en    <=  send_data_en;
+
+//cnt_wait:读fifo输出数据时间间隔计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_wait    <=  16'd0;
+    else    if(send_data_en == 1'b1)
+        if(cnt_wait == CNT_WAIT_MAX)
+            cnt_wait    <=  16'd0;
+        else
+            cnt_wait    <=  cnt_wait + 1'b1;
+    else
+        cnt_wait    <=  16'd0;
+
+//send_data_num:串口发送数据字节数计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        send_data_num   <=  12'd0;
+    else    if(send_data_en == 1'b1)
+        if(cnt_wait == CNT_WAIT_MAX)
+            send_data_num   <=  send_data_num + 1'b1;
+        else
+            send_data_num   <=  send_data_num;
+    else
+        send_data_num   <=  12'd0;
+
+//rd_fifo_rd_en:读fifo读使能信号
+//assign  rd_fifo_rd_en = (cnt_wait == CNT_WAIT_MAX) ? 1'b1 : 1'b0;
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rd_fifo_rd_en   <=  1'b0;
+    else    if(cnt_wait == (CNT_WAIT_MAX - 1'b1))
+        rd_fifo_rd_en   <=  1'b1;
+    else
+        rd_fifo_rd_en   <=  1'b0;
+
+//tx_flag:读fifo读出数据标志信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        tx_flag <=  1'b0;
+    else
+        tx_flag <=  rd_fifo_rd_en;
+
+//********************************************************************//
+//************************** Instantiation ***************************//
+//********************************************************************//
+//------------- fifo_wr_data_inst -------------
+fifo_wr_data   fifo_wr_data_inst
+(
+    .wrclk      (sys_clk            ),  //数据写时钟
+    .wrreq      (rx_flag            ),  //数据写使能
+    .data       (rx_data            ),  //写入数据
+
+    .rdclk      (sys_clk            ),  //数据读时钟
+    .rdreq      (wr_req             ),  //数据读使能
+    .q          (wr_data            ),  //读出数据
+    .rdusedw    (wr_fifo_data_num   )   //fifo内剩余数据个数
+);
+
+//------------- fifo_rd_data_inst -------------
+fifo_rd_data    fifo_rd_data_inst
+(
+    .wrclk      (sys_clk        ),  //数据写时钟
+    .wrreq      (rd_data_en     ),  //数据写使能
+    .data       (rd_data        ),  //写入数据
+
+    .rdclk      (sys_clk        ),  //数据读时钟
+    .rdreq      (rd_fifo_rd_en  ),  //数据读使能
+    .q          (tx_data        )   //读出数据
+);
+
+endmodule
+\ No newline at end of file
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v
new file mode 100644
index 0000000..5f58911
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v
@@ -0,0 +1,136 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : sd_ctrl
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : SD卡控制顶层模块
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  sd_ctrl
+(
+    input   wire            sys_clk         ,   //输入工作时钟,频率50MHz
+    input   wire            sys_clk_shift   ,   //输入工作时钟,频率50MHz,相位偏移90度
+    input   wire            sys_rst_n       ,   //输入复位信号,低电平有效
+    //SD卡接口
+    input   wire            sd_miso         ,   //主输入从输出信号
+    output  wire            sd_clk          ,   //SD卡时钟信号
+    output  reg             sd_cs_n         ,   //片选信号
+    output  reg             sd_mosi         ,   //主输出从输入信号
+    //写SD卡接口
+    input   wire            wr_en           ,   //数据写使能信号
+    input   wire    [31:0]  wr_addr         ,   //写数据扇区地址
+    input   wire    [15:0]  wr_data         ,   //写数据
+    output  wire            wr_busy         ,   //写操作忙信号
+    output  wire            wr_req          ,   //写数据请求信号
+    //读SD卡接口
+    input   wire            rd_en           ,   //数据读使能信号
+    input   wire    [31:0]  rd_addr         ,   //读数据扇区地址
+    output  wire            rd_busy         ,   //读操作忙信号
+    output  wire            rd_data_en      ,   //读数据标志信号
+    output  wire    [15:0]  rd_data         ,   //读数据
+
+    output  wire            init_end            //SD卡初始化完成信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//wire define
+wire            init_cs_n   ;   //初始化阶段片选信号
+wire            init_mosi   ;   //初始化阶段主输出从输入信号
+wire            wr_cs_n     ;   //写数据阶段片选信号
+wire            wr_mosi     ;   //写数据阶段主输出从输入信号
+wire            rd_cs_n     ;   //读数据阶段片选信号
+wire            rd_mosi     ;   //读数据阶段主输出从输入信号
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//sd_clk:SD卡时钟信号
+assign  sd_clk = sys_clk_shift;
+
+//SD卡接口信号选择
+always@(*)
+    if(init_end == 1'b0)
+        begin
+            sd_cs_n <=  init_cs_n;
+            sd_mosi <=  init_mosi;
+        end
+    else    if(wr_busy == 1'b1)
+        begin
+            sd_cs_n <=  wr_cs_n;
+            sd_mosi <=  wr_mosi;
+        end
+    else    if(rd_busy == 1'b1)
+        begin
+            sd_cs_n <= rd_cs_n;
+            sd_mosi <= rd_mosi;
+        end
+    else
+        begin
+            sd_cs_n <=  1'b1;
+            sd_mosi <=  1'b1;
+        end
+
+//********************************************************************//
+//************************** Instantiation ***************************//
+//********************************************************************//
+//------------- sd_init_inst -------------
+sd_init sd_init_inst
+(
+    .sys_clk        (sys_clk        ),  //输入工作时钟,频率50MHz
+    .sys_clk_shift  (sys_clk_shift  ),  //输入工作时钟,频率50MHz,相位偏移90度
+    .sys_rst_n      (sys_rst_n      ),  //输入复位信号,低电平有效
+    .miso           (sd_miso        ),  //主输入从输出信号
+
+    .cs_n           (init_cs_n      ),  //输出片选信号
+    .mosi           (init_mosi      ),  //主输出从输入信号
+    .init_end       (init_end       )   //初始化完成信号
+);
+
+//------------- sd_write_inst -------------
+sd_write    sd_write_inst
+(
+    .sys_clk        (sys_clk            ),  //输入工作时钟,频率50MHz
+    .sys_clk_shift  (sys_clk_shift      ),  //输入工作时钟,频率50MHz,相位偏移90度
+    .sys_rst_n      (sys_rst_n          ),  //输入复位信号,低电平有效
+    .miso           (sd_miso            ),  //主输入从输出信号
+    .wr_en          (wr_en && init_end  ),  //数据写使能信号
+    .wr_addr        (wr_addr            ),  //写数据扇区地址
+    .wr_data        (wr_data            ),  //写数据
+
+    .cs_n           (wr_cs_n            ),  //输出片选信号
+    .mosi           (wr_mosi            ),  //主输出从输入信号
+    .wr_busy        (wr_busy            ),  //写操作忙信号
+    .wr_req         (wr_req             )   //写数据请求信号
+);
+
+//------------- sd_read_inst -------------
+sd_read sd_read_inst
+(
+    .sys_clk        (sys_clk            ),  //输入工作时钟,频率50MHz
+    .sys_clk_shift  (sys_clk_shift      ),  //输入工作时钟,频率50MHz,相位偏移90度
+    .sys_rst_n      (sys_rst_n          ),  //输入复位信号,低电平有效
+    .miso           (sd_miso            ),  //主输入从输出信号
+    .rd_en          (rd_en & init_end   ),  //数据读使能信号
+    .rd_addr        (rd_addr            ),  //读数据扇区地址
+
+    .rd_busy        (rd_busy            ),  //读操作忙信号
+    .rd_data_en     (rd_data_en         ),  //读数据标志信号
+    .rd_data        (rd_data            ),  //读数据
+    .cs_n           (rd_cs_n            ),  //片选信号
+    .mosi           (rd_mosi            )   //主输出从输入信号
+);
+
+endmodule
+\ No newline at end of file
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v
new file mode 100644
index 0000000..3092489
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v
@@ -0,0 +1,271 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : sd_init
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : SD卡初始化
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  sd_init
+(
+    input   wire    sys_clk         ,   //输入工作时钟,频率50MHz
+    input   wire    sys_clk_shift   ,   //输入工作时钟,频率50MHz,相位偏移90度
+    input   wire    sys_rst_n       ,   //输入复位信号,低电平有效
+    input   wire    miso            ,   //主输入从输出信号
+
+    output  reg     cs_n            ,   //输出片选信号
+    output  reg     mosi            ,   //主输出从输入信号
+    output  reg     init_end            //初始化完成信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   CMD0    =   {8'h40,8'h00,8'h00,8'h00,8'h00,8'h95},  //复位指令
+            CMD8    =   {8'h48,8'h00,8'h00,8'h01,8'haa,8'h87},  //查询电压指令
+            CMD55   =   {8'h77,8'h00,8'h00,8'h00,8'h00,8'hff},  //应用指令告知指令
+            ACMD41  =   {8'h69,8'h40,8'h00,8'h00,8'h00,8'hff};  //应用指令
+parameter   CNT_WAIT_MAX    =   9'd511; //上电后同步过程等待时钟计数最大值
+parameter   IDLE        =   4'b0000,    //初始状态
+            SEND_CMD0   =   4'b0001,    //CMD0发送状态
+            CMD0_ACK    =   4'b0011,    //CMD0响应状态
+            SEND_CMD8   =   4'b0010,    //CMD8发送状态
+            CMD8_ACK    =   4'b0110,    //CMD8响应状态
+            SEND_CMD55  =   4'b0111,    //CMD55发送状态
+            CMD55_ACK   =   4'b0101,    //CMD55响应状态
+            SEND_ACMD41 =   4'b0100,    //ACMD41发送状态
+            ACMD41_ACK  =   4'b1100,    //ACMD41响应状态
+            INIT_END    =   4'b1101;    //初始化完成状态
+
+//reg   define
+reg     [8:0]   cnt_wait        ;   //上电同步时钟计数器
+reg     [3:0]   state           ;   //状态机状态
+reg     [7:0]   cnt_cmd_bit     ;   //指令比特计数器
+reg             miso_dly        ;   //主输入从输出信号打一拍
+reg             ack_en          ;   //响应使能信号
+reg     [39:0]  ack_data        ;   //响应数据
+reg     [7:0]   cnt_ack_bit     ;   //响应数据字节计数
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//cnt_wait:上电同步时钟计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_wait    <=  9'd0;
+    else    if(cnt_wait >= CNT_WAIT_MAX)
+        cnt_wait    <=  CNT_WAIT_MAX;
+    else
+        cnt_wait    <=  cnt_wait + 1'b1;
+
+//state:状态机状态跳转
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        state   <=  IDLE;
+    else
+        case(state)
+            IDLE:
+                if(cnt_wait == CNT_WAIT_MAX)
+                    state   <=  SEND_CMD0;
+                else
+                    state   <=  state;
+            SEND_CMD0:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD0_ACK;
+                else
+                    state   <=  state;
+            CMD0_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h01)
+                        state   <=  SEND_CMD8;
+                    else
+                        state   <=  SEND_CMD0;
+                else
+                    state   <=  state;
+            SEND_CMD8:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD8_ACK;
+                else
+                    state   <=  state;
+            CMD8_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[11:8] == 4'b0001)
+                        state   <=  SEND_CMD55;
+                    else
+                        state   <=  SEND_CMD8;
+                else
+                    state   <=  state;
+            SEND_CMD55:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD55_ACK;
+                else
+                    state   <=  state;
+            CMD55_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h01)
+                        state   <=  SEND_ACMD41;
+                    else
+                        state   <=  SEND_CMD55;
+                else
+                    state   <=  state;
+            SEND_ACMD41:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  ACMD41_ACK;
+                else
+                    state   <=  state;
+            ACMD41_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h00)
+                        state   <=  INIT_END;
+                    else
+                        state   <=  SEND_CMD55;
+                else
+                    state   <=  state;
+            INIT_END:
+                state   <=  state;
+            default:
+                state   <=  IDLE;
+        endcase
+
+//cs_n,mosi,init_end,cnt_cmd_bit
+//片选信号,主输出从输入信号,初始化结束信号,指令比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            cs_n            <=  1'b1;
+            mosi            <=  1'b1;
+            init_end        <=  1'b0;
+            cnt_cmd_bit     <=  8'd0;
+        end
+    else
+        case(state)
+            IDLE:
+                begin
+                    cs_n            <=  1'b1;
+                    mosi            <=  1'b1;
+                    init_end        <=  1'b0;
+                    cnt_cmd_bit     <=  8'd0;
+                end
+            SEND_CMD0:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD0[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD0_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_CMD8:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD8[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD8_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_CMD55:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD55[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD55_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_ACMD41:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  ACMD41[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            ACMD41_ACK:
+                if(cnt_ack_bit < 8'd47)
+                    cs_n    <=  1'b0;
+                else
+                    cs_n    <=  1'b1;
+            INIT_END:
+                begin
+                    cs_n        <=  1'b1;
+                    mosi        <=  1'b1;
+                    init_end    <=  1'b1;
+                end
+            default:
+                begin
+                    cs_n    <=  1'b1;
+                    mosi    <=  1'b1;
+                end
+        endcase
+
+//miso_dly:主输入从输出信号打一拍
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        miso_dly    <=  1'b0;
+    else
+        miso_dly    <=  miso;
+
+//ack_en:响应使能信号
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        ack_en  <=  1'b0;
+    else    if(cnt_ack_bit == 8'd47)
+        ack_en  <=  1'b0;
+    else    if((miso == 1'b0) && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0))
+        ack_en  <=  1'b1;
+    else
+        ack_en  <=  ack_en;
+
+//ack_data:响应数据
+//cnt_ack_bit:响应数据字节计数
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            ack_data    <=  8'b0;
+            cnt_ack_bit <=  8'd0;
+        end
+    else    if(ack_en == 1'b1)
+        begin
+            cnt_ack_bit     <=  cnt_ack_bit + 8'd1;
+            if(cnt_ack_bit < 8'd40)
+                ack_data    <=  {ack_data[38:0],miso_dly};
+            else
+                ack_data    <=  ack_data;
+        end
+    else
+        cnt_ack_bit <=  8'd0;
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak
new file mode 100644
index 0000000..50c320c
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak
@@ -0,0 +1,271 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : sd_init
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : SD卡初始化
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  sd_init
+(
+    input   wire    sys_clk         ,   //输入工作时钟,频率50MHz
+    input   wire    sys_clk_shift   ,   //输入工作时钟,频率50MHz,相位偏移90度
+    input   wire    sys_rst_n       ,   //输入复位信号,低电平有效
+    input   wire    miso            ,   //主输入从输出信号
+
+    output  reg     cs_n            ,   //输出片选信号
+    output  reg     mosi            ,   //主输出从输入信号
+    output  reg     init_end            //初始化完成信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   CMD0    =   {8'h40,8'h00,8'h00,8'h00,8'h00,8'h95},  //复位指令
+            CMD8    =   {8'h48,8'h00,8'h00,8'h01,8'haa,8'h87},  //查询电压指令
+            CMD55   =   {8'h77,8'h00,8'h00,8'h00,8'h00,8'hff},  //应用指令告知指令
+            ACMD41  =   {8'h69,8'h40,8'h00,8'h00,8'h00,8'hff};  //应用指令
+parameter   CNT_WAIT_MAX    =   8'd100; //上电后同步过程等待时钟计数最大值
+parameter   IDLE        =   4'b0000,    //初始状态
+            SEND_CMD0   =   4'b0001,    //CMD0发送状态
+            CMD0_ACK    =   4'b0011,    //CMD0响应状态
+            SEND_CMD8   =   4'b0010,    //CMD8发送状态
+            CMD8_ACK    =   4'b0110,    //CMD8响应状态
+            SEND_CMD55  =   4'b0111,    //CMD55发送状态
+            CMD55_ACK   =   4'b0101,    //CMD55响应状态
+            SEND_ACMD41 =   4'b0100,    //ACMD41发送状态
+            ACMD41_ACK  =   4'b1100,    //ACMD41响应状态
+            INIT_END    =   4'b1101;    //初始化完成状态
+
+//reg   define
+reg     [7:0]   cnt_wait        ;   //上电同步时钟计数器
+reg     [3:0]   state           ;   //状态机状态
+reg     [7:0]   cnt_cmd_bit     ;   //指令比特计数器
+reg             miso_dly        ;   //主输入从输出信号打一拍
+reg             ack_en          ;   //响应使能信号
+reg     [39:0]  ack_data        ;   //响应数据
+reg     [7:0]   cnt_ack_bit     ;   //响应数据字节计数
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//cnt_wait:上电同步时钟计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_wait    <=  8'd0;
+    else    if(cnt_wait >= CNT_WAIT_MAX)
+        cnt_wait    <=  CNT_WAIT_MAX;
+    else
+        cnt_wait    <=  cnt_wait + 1'b1;
+
+//state:状态机状态跳转
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        state   <=  IDLE;
+    else
+        case(state)
+            IDLE:
+                if(cnt_wait == CNT_WAIT_MAX)
+                    state   <=  SEND_CMD0;
+                else
+                    state   <=  state;
+            SEND_CMD0:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD0_ACK;
+                else
+                    state   <=  state;
+            CMD0_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h01)
+                        state   <=  SEND_CMD8;
+                    else
+                        state   <=  SEND_CMD0;
+                else
+                    state   <=  state;
+            SEND_CMD8:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD8_ACK;
+                else
+                    state   <=  state;
+            CMD8_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[11:8] == 4'b0001)
+                        state   <=  SEND_CMD55;
+                    else
+                        state   <=  SEND_CMD8;
+                else
+                    state   <=  state;
+            SEND_CMD55:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  CMD55_ACK;
+                else
+                    state   <=  state;
+            CMD55_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h01)
+                        state   <=  SEND_ACMD41;
+                    else
+                        state   <=  SEND_CMD55;
+                else
+                    state   <=  state;
+            SEND_ACMD41:
+                if(cnt_cmd_bit == 8'd48)
+                    state   <=  ACMD41_ACK;
+                else
+                    state   <=  state;
+            ACMD41_ACK:
+                if(cnt_ack_bit == 8'd48)
+                    if(ack_data[39:32] == 8'h00)
+                        state   <=  INIT_END;
+                    else
+                        state   <=  SEND_CMD55;
+                else
+                    state   <=  state;
+            INIT_END:
+                state   <=  state;
+            default:
+                state   <=  IDLE;
+        endcase
+
+//cs_n,mosi,init_end,cnt_cmd_bit
+//片选信号,主输出从输入信号,初始化结束信号,指令比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            cs_n            <=  1'b1;
+            mosi            <=  1'b1;
+            init_end        <=  1'b0;
+            cnt_cmd_bit     <=  8'd0;
+        end
+    else
+        case(state)
+            IDLE:
+                begin
+                    cs_n            <=  1'b1;
+                    mosi            <=  1'b1;
+                    init_end        <=  1'b0;
+                    cnt_cmd_bit     <=  8'd0;
+                end
+            SEND_CMD0:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD0[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD0_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_CMD8:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD8[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD8_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_CMD55:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  CMD55[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            CMD55_ACK:
+                if(cnt_ack_bit == 8'd47)
+                    cs_n    <=  1'b1;
+                else
+                    cs_n    <=  1'b0;
+            SEND_ACMD41:
+                if(cnt_cmd_bit == 8'd48)
+                    cnt_cmd_bit     <=  8'd0;
+                else
+                    begin
+                        cs_n            <=  1'b0;
+                        mosi            <=  ACMD41[8'd47 - cnt_cmd_bit];
+                        init_end        <=  1'b0;
+                        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+                    end
+            ACMD41_ACK:
+                if(cnt_ack_bit < 8'd47)
+                    cs_n    <=  1'b0;
+                else
+                    cs_n    <=  1'b1;
+            INIT_END:
+                begin
+                    cs_n        <=  1'b1;
+                    mosi        <=  1'b1;
+                    init_end    <=  1'b1;
+                end
+            default:
+                begin
+                    cs_n    <=  1'b1;
+                    mosi    <=  1'b1;
+                end
+        endcase
+
+//miso_dly:主输入从输出信号打一拍
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        miso_dly    <=  1'b0;
+    else
+        miso_dly    <=  miso;
+
+//ack_en:响应使能信号
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        ack_en  <=  1'b0;
+    else    if(cnt_ack_bit == 8'd47)
+        ack_en  <=  1'b0;
+    else    if((miso == 1'b0) && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0))
+        ack_en  <=  1'b1;
+    else
+        ack_en  <=  ack_en;
+
+//ack_data:响应数据
+//cnt_ack_bit:响应数据字节计数
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            ack_data    <=  8'b0;
+            cnt_ack_bit <=  8'd0;
+        end
+    else    if(ack_en == 1'b1)
+        begin
+            cnt_ack_bit     <=  cnt_ack_bit + 8'd1;
+            if(cnt_ack_bit < 8'd40)
+                ack_data    <=  {ack_data[38:0],miso_dly};
+            else
+                ack_data    <=  ack_data;
+        end
+    else
+        cnt_ack_bit <=  8'd0;
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v
new file mode 100644
index 0000000..f7fc271
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v
@@ -0,0 +1,268 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : sd_read
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : SD卡数据读操作
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  sd_read
+(
+    input   wire            sys_clk         ,   //输入工作时钟,频率50MHz
+    input   wire            sys_clk_shift   ,   //输入工作时钟,频率50MHz,相位偏移90度
+    input   wire            sys_rst_n       ,   //输入复位信号,低电平有效
+    input   wire            miso            ,   //主输入从输出信号
+    input   wire            rd_en           ,   //数据读使能信号
+    input   wire    [31:0]  rd_addr         ,   //读数据扇区地址
+
+    output  wire            rd_busy         ,   //读操作忙信号
+    output  reg             rd_data_en      ,   //读数据标志信号
+    output  reg     [15:0]  rd_data         ,   //读数据
+    output  reg             cs_n            ,   //片选信号
+    output  reg             mosi                //主输出从输入信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   IDLE        =   3'b000  ,   //初始状态
+            SEND_CMD17  =   3'b001  ,   //读命令CMD17发送状态
+            CMD17_ACK   =   3'b011  ,   //CMD17响应状态
+            RD_DATA     =   3'b010  ,   //读数据状态
+            RD_END      =   3'b110  ;   //读结束状态
+parameter   DATA_NUM    =   12'd256 ;   //待读取数据字节数
+
+//wire  define
+wire    [47:0]  cmd_rd      ;   //数据读指令
+
+//reg   define
+reg     [2:0]   state       ;   //状态机状态
+reg     [7:0]   cnt_cmd_bit ;   //指令比特计数器
+reg             ack_en      ;   //响应使能信号
+reg     [7:0]   ack_data    ;   //响应数据
+reg     [7:0]   cnt_ack_bit ;   //响应数据字节计数
+reg     [11:0]  cnt_data_num;   //读出数据个数计数
+reg     [3:0]   cnt_data_bit;   //读数据比特计数器
+reg     [2:0]   cnt_end     ;   //结束状态时钟计数
+reg             miso_dly    ;   //主输入从输出信号打一拍
+reg     [15:0]  rd_data_reg ;   //读出数据寄存
+reg     [15:0]  byte_head   ;   //读数据字节头
+reg             byte_head_en;   //读数据字节头使能
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//rd_busy:读操作忙信号
+assign  rd_busy = (state != IDLE) ? 1'b1 : 1'b0;
+
+//cmd_rd:数据读指令
+assign  cmd_rd = {8'h51,rd_addr,8'hff};
+
+//miso_dly:主输入从输出信号打一拍
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        miso_dly    <=  1'b0;
+    else
+        miso_dly    <=  miso;
+
+//ack_en:响应使能信号
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        ack_en  <=  1'b0;
+    else    if(cnt_ack_bit == 8'd15)
+        ack_en  <=  1'b0;
+    else    if((state == CMD17_ACK) && (miso == 1'b0)
+                && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0))
+        ack_en  <=  1'b1;
+    else
+        ack_en  <=  ack_en;
+
+//ack_data:响应数据
+//cnt_ack_bit:响应数据字节计数
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            ack_data    <=  8'b0;
+            cnt_ack_bit <=  8'd0;
+        end
+    else    if(ack_en == 1'b1)
+        begin
+            cnt_ack_bit     <=  cnt_ack_bit + 8'd1;
+            if(cnt_ack_bit < 8'd8)
+                ack_data    <=  {ack_data[6:0],miso_dly};
+            else
+                ack_data    <=  ack_data;
+        end
+    else
+        cnt_ack_bit <=  8'd0;
+
+//state:状态机状态跳转
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        state   <=  IDLE;
+    else
+        case(state)
+            IDLE:
+                if(rd_en == 1'b1)
+                    state   <=  SEND_CMD17;
+                else
+                    state   <=  state;
+            SEND_CMD17:
+                if(cnt_cmd_bit == 8'd47)
+                    state   <=  CMD17_ACK;
+                else
+                    state   <=  state;
+            CMD17_ACK:
+                if(cnt_ack_bit == 8'd15)
+                    if(ack_data == 8'h00)
+                        state   <=  RD_DATA;
+                    else
+                        state   <=  SEND_CMD17;
+                else
+                    state   <=  state;
+            RD_DATA:
+                if((cnt_data_num == (DATA_NUM + 1'b1))
+                    && (cnt_data_bit == 4'd15))
+                    state   <=  RD_END;
+                else
+                    state   <=  state;
+            RD_END:
+                if(cnt_end == 3'd7)
+                    state   <=  IDLE;
+                else
+                    state   <=  state;
+            default:state   <=  IDLE;
+        endcase
+
+//cs_n:输出片选信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cs_n    <=  1'b1;
+    else    if(cnt_end == 3'd7)
+        cs_n    <=  1'b1;
+    else    if(rd_en == 1'b1)
+        cs_n    <=  1'b0;
+    else
+        cs_n    <=  cs_n;
+
+//cnt_cmd_bit:指令比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_cmd_bit     <=  8'd0;
+    else    if(state == SEND_CMD17)
+        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+    else
+        cnt_cmd_bit     <=  8'd0;
+
+//mosi:主输出从输入信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        mosi    <=  1'b1;
+    else    if(state == SEND_CMD17)
+        mosi    <=  cmd_rd[8'd47 - cnt_cmd_bit];
+    else
+        mosi    <=  1'b1;
+
+//byte_head:读数据字节头
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        byte_head   <=  16'b0;
+    else    if(byte_head_en == 1'b0)
+        byte_head   <=  16'b0;
+    else    if(byte_head_en == 1'b1)
+        byte_head   <=  {byte_head[14:0],miso};
+    else
+        byte_head   <=  byte_head;
+
+//byte_head_en:读数据字节头使能
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        byte_head_en    <=  1'b0;
+    else    if(byte_head == 16'hfffe)
+        byte_head_en    <=  1'b0;
+    else    if((state == RD_DATA) && (cnt_data_num == 12'd0)
+                && (cnt_data_bit == 4'd0))
+        byte_head_en    <=  1'b1;
+    else
+        byte_head_en    <=  byte_head_en;
+
+//cnt_data_bit:读数据比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_data_bit    <=  4'd0;
+    else    if((state == RD_DATA) && (cnt_data_num >= 12'd1))
+        cnt_data_bit    <=  cnt_data_bit + 4'd1;
+    else
+        cnt_data_bit    <=  4'd0;
+
+//cnt_data_num:读出数据个数计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_data_num    <=  12'd0;
+    else    if(state == RD_DATA)
+        if((cnt_data_bit == 4'd15) || (byte_head == 16'hfffe))
+            cnt_data_num    <=  cnt_data_num + 12'd1;
+        else
+            cnt_data_num    <=  cnt_data_num;
+    else
+        cnt_data_num    <=  12'd0;
+
+//rd_data_reg:读出数据寄存
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rd_data_reg <=  16'd0;
+    else    if((state == RD_DATA) && (cnt_data_num >= 12'd1)
+                && (cnt_data_num <= DATA_NUM))
+        rd_data_reg <=  {rd_data_reg[14:0],miso};
+    else
+        rd_data_reg <=  16'd0;
+
+//rd_data_en:读数据标志信号
+//rd_data:读数据
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            rd_data_en  <=  1'b0;
+            rd_data     <=  16'd0;
+        end
+    else    if(state == RD_DATA)
+        begin
+            if((cnt_data_bit == 4'd15) && (cnt_data_num <= DATA_NUM))
+                begin
+                    rd_data_en  <=  1'b1;
+                    rd_data     <=  rd_data_reg;
+                end
+            else
+                begin
+                    rd_data_en  <=  1'b0;
+                    rd_data     <=  rd_data;
+                end
+        end
+    else
+        begin
+            rd_data_en  <=  1'b0;
+            rd_data     <=  16'd0;
+        end
+
+//cnt_end:结束状态时钟计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_end <=  3'd0;
+    else    if(state == RD_END)
+        cnt_end <=  cnt_end + 3'd1;
+    else
+        cnt_end <=  3'd0;
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v
new file mode 100644
index 0000000..1b23bf1
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v
@@ -0,0 +1,234 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : sd_write
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : SD卡数据写操作
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  sd_write
+(
+    input   wire            sys_clk         ,   //输入工作时钟,频率50MHz
+    input   wire            sys_clk_shift   ,   //输入工作时钟,频率50MHz,相位偏移90度
+    input   wire            sys_rst_n       ,   //输入复位信号,低电平有效
+    input   wire            miso            ,   //主输入从输出信号
+    input   wire            wr_en           ,   //数据写使能信号
+    input   wire    [31:0]  wr_addr         ,   //写数据扇区地址
+    input   wire    [15:0]  wr_data         ,   //写数据
+
+    output  reg             cs_n            ,   //输出片选信号
+    output  reg             mosi            ,   //主输出从输入信号
+    output  wire            wr_busy         ,   //写操作忙信号
+    output  wire            wr_req              //写数据请求信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   IDLE        =   3'b000  ,   //初始状态
+            SEND_CMD24  =   3'b001  ,   //写命令CMD24发送状态
+            CMD24_ACK   =   3'b011  ,   //CMD24响应状态
+            WR_DATA     =   3'b010  ,   //写数据状态
+            WR_BUSY     =   3'b110  ,   //SD卡写忙状态
+            WR_END      =   3'b111  ;   //写结束状态
+parameter   DATA_NUM    =   12'd256 ;   //待写入数据字节数
+parameter   BYTE_HEAD   =   16'hfffe;   //写数据字节头
+
+//wire  define
+wire    [47:0]  cmd_wr      ;   //数据写指令
+
+//reg   define
+reg     [2:0]   state       ;   //状态机状态
+reg     [7:0]   cnt_cmd_bit ;   //指令比特计数器
+reg             ack_en      ;   //响应使能信号
+reg     [7:0]   ack_data    ;   //响应数据
+reg     [7:0]   cnt_ack_bit ;   //响应数据字节计数
+reg     [11:0]  cnt_data_num;   //写入数据个数计数
+reg     [3:0]   cnt_data_bit;   //写数据比特计数器
+reg     [7:0]   busy_data   ;   //忙状态数据
+reg     [2:0]   cnt_end     ;   //结束状态时钟计数
+reg             miso_dly    ;   //主输入从输出信号打一拍
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//wr_busy:写操作忙信号
+assign  wr_busy = (state != IDLE) ? 1'b1 : 1'b0;
+
+//wr_req:写数据请求信号
+assign  wr_req = ((cnt_data_num <= DATA_NUM - 1'b1) && (cnt_data_bit == 4'd15))
+                ? 1'b1 : 1'b0;
+
+//cmd_wr:数据写指令
+assign  cmd_wr = {8'h58,wr_addr,8'hff};
+
+//miso_dly:主输入从输出信号打一拍
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        miso_dly    <=  1'b0;
+    else
+        miso_dly    <=  miso;
+
+//ack_en:响应使能信号
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        ack_en  <=  1'b0;
+    else    if(cnt_ack_bit == 8'd15)
+        ack_en  <=  1'b0;
+    else    if((state == CMD24_ACK) && (miso == 1'b0)
+                && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0))
+        ack_en  <=  1'b1;
+    else
+        ack_en  <=  ack_en;
+
+//ack_data:响应数据
+//cnt_ack_bit:响应数据字节计数
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        begin
+            ack_data    <=  8'b0;
+            cnt_ack_bit <=  8'd0;
+        end
+    else    if(ack_en == 1'b1)
+        begin
+            cnt_ack_bit     <=  cnt_ack_bit + 8'd1;
+            if(cnt_ack_bit < 8'd8)
+                ack_data    <=  {ack_data[6:0],miso_dly};
+            else
+                ack_data    <=  ack_data;
+        end
+    else
+        cnt_ack_bit <=  8'd0;
+
+//busy_data:忙状态数据
+always@(posedge sys_clk_shift or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        busy_data   <=  8'd0;
+    else    if(state == WR_BUSY)
+        busy_data   <=  {busy_data[6:0],miso};
+    else
+        busy_data   <=  8'd0;
+
+//state:状态机状态跳转
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        state   <=  IDLE;
+    else
+        case(state)
+            IDLE:
+                if(wr_en == 1'b1)
+                    state   <=  SEND_CMD24;
+                else
+                    state   <=  state;
+            SEND_CMD24:
+                if(cnt_cmd_bit == 8'd47)
+                    state   <=  CMD24_ACK;
+                else
+                    state   <=  state;
+            CMD24_ACK:
+                if(cnt_ack_bit == 8'd15)
+                    if(ack_data == 8'h00)
+                        state   <=  WR_DATA;
+                    else
+                        state   <=  SEND_CMD24;
+                else
+                    state   <=  state;
+            WR_DATA:
+                if((cnt_data_num == (DATA_NUM + 1'b1))
+                    && (cnt_data_bit == 4'd15))
+                    state   <=  WR_BUSY;
+                else
+                    state   <=  state;
+            WR_BUSY:
+                if(busy_data == 8'hff)
+                    state   <=  WR_END;
+                else
+                    state   <=  state;
+            WR_END:
+                if(cnt_end == 3'd7)
+                    state   <=  IDLE;
+                else
+                    state   <=  state;
+            default:state   <=  IDLE;
+        endcase
+
+//cs_n:输出片选信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cs_n    <=  1'b1;
+    else    if(cnt_end == 3'd7)
+        cs_n    <=  1'b1;
+    else    if(wr_en == 1'b1)
+        cs_n    <=  1'b0;
+    else
+        cs_n    <=  cs_n;
+
+//cnt_cmd_bit:指令比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_cmd_bit     <=  8'd0;
+    else    if(state == SEND_CMD24)
+        cnt_cmd_bit     <=  cnt_cmd_bit + 8'd1;
+    else
+        cnt_cmd_bit     <=  8'd0;
+
+//mosi:主输出从输入信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        mosi    <=  1'b1;
+    else    if(state == SEND_CMD24)
+        mosi    <=  cmd_wr[8'd47 - cnt_cmd_bit];
+    else    if(state == WR_DATA)
+        if(cnt_data_num == 12'd0)
+            mosi    <=  BYTE_HEAD[15 - cnt_data_bit];
+        else    if((cnt_data_num >= 12'd1) && (cnt_data_num <= DATA_NUM))
+            mosi    <=  wr_data[15 - cnt_data_bit];
+        else
+            mosi    <=  1'b1;
+    else
+        mosi    <=  1'b1;
+
+//cnt_data_bit:写数据比特计数器
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_data_bit    <=  4'd0;
+    else    if(state == WR_DATA)
+        cnt_data_bit    <=  cnt_data_bit + 4'd1;
+    else
+        cnt_data_bit    <=  4'd0;
+
+//cnt_data_num:写入数据个数计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_data_num    <=  12'd0;
+    else    if(state == WR_DATA)
+        if(cnt_data_bit == 4'd15)
+            cnt_data_num    <=  cnt_data_num + 12'd1;
+        else
+            cnt_data_num    <=  cnt_data_num;
+    else
+        cnt_data_num    <=  12'd0;
+
+//cnt_end:结束状态时钟计数
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        cnt_end <=  3'd0;
+    else    if(state == WR_END)
+        cnt_end <=  cnt_end + 3'd1;
+    else
+        cnt_end <=  3'd0;
+
+endmodule
+
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v
new file mode 100644
index 0000000..ad85158
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v
@@ -0,0 +1,154 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/06/12
+// Module Name   : uart_rx
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   :
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  uart_rx
+#(
+    parameter   UART_BPS    =   'd9600,         //串口波特率
+    parameter   CLK_FREQ    =   'd50_000_000    //时钟频率
+)
+(
+    input   wire            sys_clk     ,   //系统时钟50MHz
+    input   wire            sys_rst_n   ,   //全局复位
+    input   wire            rx          ,   //串口接收数据
+
+    output  reg     [7:0]   po_data     ,   //串转并后的8bit数据
+    output  reg             po_flag         //串转并后的数据有效标志信号
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//localparam    define
+localparam  BAUD_CNT_MAX    =   CLK_FREQ/UART_BPS   ;
+
+//reg   define
+reg         rx_reg1     ;
+reg         rx_reg2     ;
+reg         rx_reg3     ;
+reg         start_nedge ;
+reg         work_en     ;
+reg [12:0]  baud_cnt    ;
+reg         bit_flag    ;
+reg [3:0]   bit_cnt     ;
+reg [7:0]   rx_data     ;
+reg         rx_flag     ;
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//插入两级寄存器进行数据同步，用来消除亚稳态
+//rx_reg1:第一级寄存器，寄存器空闲状态复位为1
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rx_reg1 <= 1'b1;
+    else
+        rx_reg1 <= rx;
+
+//rx_reg2:第二级寄存器，寄存器空闲状态复位为1
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rx_reg2 <= 1'b1;
+    else
+        rx_reg2 <= rx_reg1;
+
+//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rx_reg3 <= 1'b1;
+    else
+        rx_reg3 <= rx_reg2;
+
+//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        start_nedge <= 1'b0;
+    else    if((~rx_reg2) && (rx_reg3))
+        start_nedge <= 1'b1;
+    else
+        start_nedge <= 1'b0;
+
+//work_en:接收数据工作使能信号
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        work_en <= 1'b0;
+    else    if(start_nedge == 1'b1)
+        work_en <= 1'b1;
+    else    if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
+        work_en <= 1'b0;
+
+//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        baud_cnt <= 13'b0;
+    else    if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0))
+        baud_cnt <= 13'b0;
+    else    if(work_en == 1'b1)
+        baud_cnt <= baud_cnt + 1'b1;
+
+//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定，
+//此时拉高一个标志信号表示数据可以被取走
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        bit_flag <= 1'b0;
+    else    if(baud_cnt == BAUD_CNT_MAX/2 - 1)
+        bit_flag <= 1'b1;
+    else
+        bit_flag <= 1'b0;
+
+//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位）
+//都接收完成后计数器清零
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        bit_cnt <= 4'b0;
+    else    if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
+        bit_cnt <= 4'b0;
+     else    if(bit_flag ==1'b1)
+         bit_cnt <= bit_cnt + 1'b1;
+
+//rx_data:输入数据进行移位
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rx_data <= 8'b0;
+    else    if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1))
+        rx_data <= {rx_reg3, rx_data[7:1]};
+
+//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        rx_flag <= 1'b0;
+    else    if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
+        rx_flag <= 1'b1;
+    else
+        rx_flag <= 1'b0;
+
+//po_data:输出完整的8位有效数据
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        po_data <= 8'b0;
+    else    if(rx_flag == 1'b1)
+        po_data <= rx_data;
+
+//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步）
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        po_flag <= 1'b0;
+    else
+        po_flag <= rx_flag;
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v
new file mode 100644
index 0000000..d85f92d
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v
@@ -0,0 +1,162 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+//Create Date    : 2019/09/03
+// Module Name   : uart_sd
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : 串口读写SD卡顶层模块
+//
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  uart_sd
+(
+    input   wire            sys_clk     ,   //输入工作时钟,频率50MHz
+    input   wire            sys_rst_n   ,   //输入复位信号,低电平有效
+    input   wire            rx          ,   //串口发送数据
+    input   wire            sd_miso     ,   //主输入从输出信号
+
+    output  wire            sd_clk      ,   //SD卡时钟信号
+    output  wire            sd_cs_n     ,   //片选信号
+    output  wire            sd_mosi     ,   //主输出从输入信号
+    output  wire            tx              //串口接收数据
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//parameter define
+parameter   UART_BPS    =   14'd9600        ,   //比特率
+            CLK_FREQ    =   26'd50_000_000  ;   //时钟频率
+
+//wire  define
+wire            rx_flag         ;   //写fifo写入数据标志信号
+wire    [7:0]   rx_data         ;   //写fifo写入数据
+wire            wr_req          ;   //sd卡数据写请求
+wire            wr_busy         ;   //sd卡写数据忙信号
+wire            wr_en           ;   //sd卡数据写使能信号
+wire    [31:0]  wr_addr         ;   //sd卡写数据扇区地址
+wire    [15:0]  wr_data         ;   //sd卡写数据
+wire            rd_data_en      ;   //sd卡读出数据标志信号
+wire    [15:0]  rd_data         ;   //sd卡读出数据
+wire            rd_busy         ;   //sd卡读数据忙信号
+wire            rd_en           ;   //sd卡数据读使能信号
+wire    [31:0]  rd_addr         ;   //sd卡读数据扇区地址
+wire            tx_flag         ;   //读fifo读出数据标志信号
+wire    [7:0]   tx_data         ;   //读fifo读出数据
+wire            clk_50m         ;   //生成50MHz时钟
+wire            clk_50m_shift   ;   //生成50MHz时钟,相位偏移180度
+wire            locked          ;   //时钟锁定信号
+wire            rst_n           ;   //复位信号
+wire            init_end        ;   //SD卡初始化完成信号
+
+//rst_n:复位信号,低有效
+assign  rst_n = sys_rst_n && locked;
+
+//********************************************************************//
+//************************** Instantiation ***************************//
+//********************************************************************//
+//------------- clk_gen_inst -------------
+clk_gen clk_gen_inst
+(
+    .areset     (~sys_rst_n     ),  //复位信号,高有效
+    .inclk0     (sys_clk        ),  //输入系统时钟,50MHz
+
+    .c0         (clk_50m        ),  //生成50MHz时钟
+    .c1         (clk_50m_shift  ),  //生成50MHz时钟,相位偏移180度
+    .locked     (locked         )   //时钟锁定信号
+    );
+
+//------------- uart_rx_inst -------------
+uart_rx
+#(
+    .UART_BPS    (UART_BPS  ),   //串口波特率
+    .CLK_FREQ    (CLK_FREQ  )    //时钟频率
+)
+uart_rx_inst
+(
+    .sys_clk     (clk_50m   ),   //系统时钟50Mhz
+    .sys_rst_n   (rst_n     ),   //全局复位
+    .rx          (rx        ),   //串口接收数据
+
+    .po_data     (rx_data   ),   //串转并后的数据
+    .po_flag     (rx_flag   )    //串转并后的数据有效标志信号
+);
+
+//------------- data_rw_ctrl_inst -------------
+data_rw_ctrl    data_rw_ctrl_inst
+(
+    .sys_clk     (clk_50m   ),  //输入工作时钟,频率50MHz
+    .sys_rst_n   (rst_n     ),  //输入复位信号,低电平有效
+    .init_end    (init_end  ),  //SD卡初始化完成信号
+
+    .rx_flag     (rx_flag   ),  //写fifo写入数据标志信号
+    .rx_data     (rx_data   ),  //写fifo写入数据
+    .wr_req      (wr_req    ),  //sd卡数据写请求
+    .wr_busy     (wr_busy   ),  //sd卡写数据忙信号
+
+    .wr_en       (wr_en     ),  //sd卡数据写使能信号
+    .wr_addr     (wr_addr   ),  //sd卡写数据扇区地址
+    .wr_data     (wr_data   ),  //sd卡写数据
+
+    .rd_data_en  (rd_data_en),  //sd卡读出数据标志信号
+    .rd_data     (rd_data   ),  //sd卡读出数据
+    .rd_busy     (rd_busy   ),  //sd卡读数据忙信号
+    .rd_en       (rd_en     ),  //sd卡数据读使能信号
+    .rd_addr     (rd_addr   ),  //sd卡读数据扇区地址
+    .tx_flag     (tx_flag   ),  //读fifo读出数据标志信号
+    .tx_data     (tx_data   )   //读fifo读出数据
+);
+
+//------------- sd_ctrl_inst -------------
+sd_ctrl sd_ctrl_inst
+(
+    .sys_clk         (clk_50m       ),  //输入工作时钟,频率50MHz
+    .sys_clk_shift   (clk_50m_shift ),  //输入工作时钟,频率50MHz,相位偏移180度
+    .sys_rst_n       (rst_n         ),  //输入复位信号,低电平有效
+
+    .sd_miso         (sd_miso       ),  //主输入从输出信号
+    .sd_clk          (sd_clk        ),  //SD卡时钟信号
+    .sd_cs_n         (sd_cs_n       ),  //片选信号
+    .sd_mosi         (sd_mosi       ),  //主输出从输入信号
+
+    .wr_en           (wr_en         ),  //数据写使能信号
+    .wr_addr         (wr_addr       ),  //写数据扇区地址
+    .wr_data         (wr_data       ),  //写数据
+    .wr_busy         (wr_busy       ),  //写操作忙信号
+    .wr_req          (wr_req        ),  //写数据请求信号
+
+    .rd_en           (rd_en         ),  //数据读使能信号
+    .rd_addr         (rd_addr       ),  //读数据扇区地址
+    .rd_busy         (rd_busy       ),  //读操作忙信号
+    .rd_data_en      (rd_data_en    ),  //读数据标志信号
+    .rd_data         (rd_data       ),  //读数据
+
+    .init_end        (init_end      )   //SD卡初始化完成信号
+);
+
+//------------- uart_tx_inst -------------
+uart_tx
+#(
+    .UART_BPS    (UART_BPS  ),   //串口波特率
+    .CLK_FREQ    (CLK_FREQ  )    //时钟频率
+)
+uart_tx_inst
+(
+    .sys_clk     (clk_50m   ),   //系统时钟50Mhz
+    .sys_rst_n   (rst_n     ),   //全局复位
+    .pi_data     (tx_data   ),   //并行数据
+    .pi_flag     (tx_flag   ),   //并行数据有效标志信号
+
+    .tx          (tx        )    //串口发送数据
+);
+
+endmodule
+\ No newline at end of file
diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v
new file mode 100644
index 0000000..a1e1f2e
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v
@@ -0,0 +1,104 @@
+`timescale  1ns/1ns
+////////////////////////////////////////////////////////////////////////
+// Author        : EmbedFire
+// Create Date   : 2019/06/12
+// Module Name   : uart_tx
+// Project Name  : uart_sd
+// Target Devices: Altera EP4CE10F17C8N
+// Tool Versions : Quartus 13.0
+// Description   : 
+// 
+// Revision      : V1.0
+// Additional Comments:
+// 
+// 实验平台: 野火_征途Pro_FPGA开发板
+// 公司    : http://www.embedfire.com
+// 论坛    : http://www.firebbs.cn
+// 淘宝    : https://fire-stm32.taobao.com
+////////////////////////////////////////////////////////////////////////
+
+module  uart_tx
+#(
+    parameter   UART_BPS    =   'd9600,         //串口波特率
+    parameter   CLK_FREQ    =   'd50_000_000    //时钟频率
+)
+(
+     input   wire            sys_clk     ,   //系统时钟50MHz
+     input   wire            sys_rst_n   ,   //全局复位
+     input   wire    [7:0]   pi_data     ,   //模块输入的8bit数据
+     input   wire            pi_flag     ,   //并行数据有效标志信号
+ 
+     output  reg             tx              //串转并后的1bit数据
+);
+
+//********************************************************************//
+//****************** Parameter and Internal Signal *******************//
+//********************************************************************//
+//localparam    define
+localparam  BAUD_CNT_MAX    =   CLK_FREQ/UART_BPS   ;
+
+//reg   define
+reg [12:0]  baud_cnt;
+reg         bit_flag;
+reg [3:0]   bit_cnt ;
+reg         work_en ;
+
+//********************************************************************//
+//***************************** Main Code ****************************//
+//********************************************************************//
+//work_en:接收数据工作使能信号
+always@(posedge sys_clk or negedge sys_rst_n)
+        if(sys_rst_n == 1'b0)
+            work_en <= 1'b0;
+        else    if(pi_flag == 1'b1)
+            work_en <= 1'b1;
+        else    if((bit_flag == 1'b1) && (bit_cnt == 4'd9))
+            work_en <= 1'b0;
+
+//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1
+always@(posedge sys_clk or negedge sys_rst_n)
+        if(sys_rst_n == 1'b0)
+            baud_cnt <= 13'b0;
+        else    if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0))
+            baud_cnt <= 13'b0;
+        else    if(work_en == 1'b1)
+            baud_cnt <= baud_cnt + 1'b1;
+
+//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平
+always@(posedge sys_clk or negedge sys_rst_n)
+        if(sys_rst_n == 1'b0)
+            bit_flag <= 1'b0;
+        else    if(baud_cnt == 13'd1)
+            bit_flag <= 1'b1;
+        else
+            bit_flag <= 1'b0;
+
+//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        bit_cnt <= 4'b0;
+    else    if((bit_flag == 1'b1) && (bit_cnt == 4'd9))
+        bit_cnt <= 4'b0;
+    else    if((bit_flag == 1'b1) && (work_en == 1'b1))
+        bit_cnt <= bit_cnt + 1'b1;
+
+//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出
+always@(posedge sys_clk or negedge sys_rst_n)
+        if(sys_rst_n == 1'b0)
+            tx <= 1'b1; //空闲状态时为高电平
+        else    if(bit_flag == 1'b1)
+            case(bit_cnt)
+                0       : tx <= 1'b0;
+                1       : tx <= pi_data[0];
+                2       : tx <= pi_data[1];
+                3       : tx <= pi_data[2];
+                4       : tx <= pi_data[3];
+                5       : tx <= pi_data[4];
+                6       : tx <= pi_data[5];
+                7       : tx <= pi_data[6];
+                8       : tx <= pi_data[7];
+                9       : tx <= 1'b1;
+                default : tx <= 1'b1;
+            endcase
+
+endmodule
diff --git a/smh-ac415-fpga/examples/06_uart_sd/实验现象.txt b/smh-ac415-fpga/examples/06_uart_sd/实验现象.txt
new file mode 100644
index 0000000..b3c452d
--- /dev/null
+++ b/smh-ac415-fpga/examples/06_uart_sd/实验现象.txt
@@ -0,0 +1,6 @@
+现象：先把tf卡插入开发板（尽量用sandisk等大牌厂家），把usb插入电脑，预先安装ch340串口驱动，打开某个串口软件，波特率选择9600，接收发送均选择hex，发送框输入下文中512个字节数据，接收框会返回这512字节数据，此中会把这512字节先存入tf卡，在从tf卡读出。此例程参考野火fpga例程修改而来。具体可参考野火教程。
+
+测试：可以测试tf卡，串口是否正常。
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+00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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