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-rw-r--r--fpga/hp_lcd_driver/ebaz4205.xdc9
-rw-r--r--fpga/hp_lcd_driver/kbd_uarts.vhdl221
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl35
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl12
-rw-r--r--fpga/hp_lcd_driver/zynq7_wrapper.vhdl153
5 files changed, 385 insertions, 45 deletions
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
index 39ea882..c2ee09d 100644
--- a/fpga/hp_lcd_driver/ebaz4205.xdc
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -117,6 +117,15 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
#set_property PULLTYPE PULLUP [get_ports {sys_rst_n}]
#
+set_property PACKAGE_PIN M19 [get_ports {u0_tx}]; #data3-5
+set_property IOSTANDARD LVCMOS33 [get_ports {u0_tx}]
+set_property PACKAGE_PIN P18 [get_ports {u0_rx}]; #data3-7
+set_property IOSTANDARD LVCMOS33 [get_ports {u0_rx}]
+set_property PACKAGE_PIN N17 [get_ports {u1_tx}]; #data3-9
+set_property IOSTANDARD LVCMOS33 [get_ports {u1_tx}]
+set_property PACKAGE_PIN P20 [get_ports {u1_rx}]; #data3-11
+set_property IOSTANDARD LVCMOS33 [get_ports {u1_rx}]
+
set_property PACKAGE_PIN M20 [get_ports {scope_ch1}]; #data2-19
set_property IOSTANDARD LVCMOS33 [get_ports {scope_ch1}]
diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl
index 64bc3a3..57c0f8b 100644
--- a/fpga/hp_lcd_driver/kbd_uarts.vhdl
+++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl
@@ -53,13 +53,226 @@ entity kbd_uarts is
);
end kbd_uarts;
architecture Behavioural of kbd_uarts is
+
+ signal uc_axi_awid : std_logic_vector ( 23 downto 0 );
+ signal uc_axi_awaddr : std_logic_vector ( 63 downto 0 );
+ signal uc_axi_awlen : std_logic_vector ( 15 downto 0 );
+ signal uc_axi_awsize : std_logic_vector ( 5 downto 0 );
+ signal uc_axi_awburst : std_logic_vector ( 3 downto 0 );
+ signal uc_axi_awlock : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_awcache : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_awprot : std_logic_vector ( 5 downto 0 );
+ signal uc_axi_awregion : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_awqos : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_awvalid : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_awready : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_wdata : std_logic_vector ( 63 downto 0 );
+ signal uc_axi_wstrb : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_wlast : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_wvalid : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_wready : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_bid : std_logic_vector ( 23 downto 0 );
+ signal uc_axi_bresp : std_logic_vector ( 3 downto 0 );
+ signal uc_axi_bvalid : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_bready : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_arid : std_logic_vector ( 23 downto 0 );
+ signal uc_axi_araddr : std_logic_vector ( 63 downto 0 );
+ signal uc_axi_arlen : std_logic_vector ( 15 downto 0 );
+ signal uc_axi_arsize : std_logic_vector ( 5 downto 0 );
+ signal uc_axi_arburst : std_logic_vector ( 3 downto 0 );
+ signal uc_axi_arlock : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_arcache : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_arprot : std_logic_vector ( 5 downto 0 );
+ signal uc_axi_arregion : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_arqos : std_logic_vector ( 7 downto 0 );
+ signal uc_axi_arvalid : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_arready : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_rid : std_logic_vector ( 23 downto 0 );
+ signal uc_axi_rdata : std_logic_vector ( 63 downto 0 );
+ signal uc_axi_rresp : std_logic_vector ( 3 downto 0 );
+ signal uc_axi_rlast : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_rvalid : std_logic_vector ( 1 downto 0 );
+ signal uc_axi_rready : std_logic_vector ( 1 downto 0 );
+
begin
- u0_int <= '0';
- u0_tx <='1';
- u1_int <= '0';
- u1_tx <='1';
+axi_crossbar_0_i: entity work.axi_crossbar_0
+ Port map (
+ aclk => s_axi_aclk,
+ aresetn => s_axi_aresetn,
+ s_axi_awid => s_axi_awid,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_awlen => s_axi_awlen,
+ s_axi_awsize => s_axi_awsize,
+ s_axi_awburst => s_axi_awburst,
+ s_axi_awlock => s_axi_awlock,
+ s_axi_awcache => s_axi_awcache,
+ s_axi_awprot => s_axi_awprot,
+ s_axi_awqos => s_axi_awqos,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wlast => s_axi_wlast,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bid => s_axi_bid,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_arid => s_axi_arid,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_arlen => s_axi_arlen,
+ s_axi_arsize => s_axi_arsize,
+ s_axi_arburst => s_axi_arburst,
+ s_axi_arlock => s_axi_arlock,
+ s_axi_arcache => s_axi_arcache,
+ s_axi_arprot => s_axi_arprot,
+ s_axi_arqos => s_axi_arqos,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rid => s_axi_rid,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rlast => s_axi_rlast,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+
+ m_axi_awid => uc_axi_awid,
+ m_axi_awaddr => uc_axi_awaddr,
+ m_axi_awlen => uc_axi_awlen,
+ m_axi_awsize => uc_axi_awsize,
+ m_axi_awburst => uc_axi_awburst,
+ m_axi_awlock => uc_axi_awlock,
+ m_axi_awcache => uc_axi_awcache,
+ m_axi_awprot => uc_axi_awprot,
+ m_axi_awregion => uc_axi_awregion,
+ m_axi_awqos => uc_axi_awqos,
+ m_axi_awvalid => uc_axi_awvalid,
+ m_axi_awready => uc_axi_awready,
+ m_axi_wdata => uc_axi_wdata,
+ m_axi_wstrb => uc_axi_wstrb,
+ m_axi_wlast => uc_axi_wlast,
+ m_axi_wvalid => uc_axi_wvalid,
+ m_axi_wready => uc_axi_wready,
+ m_axi_bid => uc_axi_bid,
+ m_axi_bresp => uc_axi_bresp,
+ m_axi_bvalid => uc_axi_bvalid,
+ m_axi_bready => uc_axi_bready,
+ m_axi_arid => uc_axi_arid,
+-- m_axi_araddr => uc_axi_araddr,
+ m_axi_arlen => uc_axi_arlen,
+ m_axi_arsize => uc_axi_arsize,
+ m_axi_arburst => uc_axi_arburst,
+ m_axi_arlock => uc_axi_arlock,
+ m_axi_arcache => uc_axi_arcache,
+ m_axi_arprot => uc_axi_arprot,
+ m_axi_arregion => uc_axi_arregion,
+ m_axi_arqos => uc_axi_arqos,
+ m_axi_arvalid => uc_axi_arvalid,
+ m_axi_arready => uc_axi_arready,
+ m_axi_rid => uc_axi_rid,
+ m_axi_rdata => uc_axi_rdata,
+ m_axi_rresp => uc_axi_rresp,
+ m_axi_rlast => uc_axi_rlast,
+ m_axi_rvalid => uc_axi_rvalid,
+ m_axi_rready => uc_axi_rready
+ );
+
+uc_axi_araddr <= ( others => '0');
+
+axi_uart16550_0_i0: entity work.axi_uart16550_0
+port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+
+
+
+ s_axi_awaddr => uc_axi_awaddr(12 downto 0),
+ s_axi_awvalid => uc_axi_awvalid(0),
+ s_axi_awready => uc_axi_awready(0),
+ s_axi_wdata => uc_axi_wdata(31 downto 0),
+ s_axi_wstrb => uc_axi_wstrb (3 downto 0),
+ s_axi_wvalid => uc_axi_wvalid(0),
+ s_axi_wready => uc_axi_wready(0),
+ s_axi_bresp => uc_axi_bresp(1 downto 0),
+ s_axi_bvalid =>uc_axi_bvalid(0),
+ s_axi_bready =>uc_axi_bready(0),
+ s_axi_araddr => uc_axi_araddr(12 downto 0),
+ s_axi_arvalid => uc_axi_arvalid(0),
+ s_axi_arready => uc_axi_arready(0),
+ s_axi_rdata => uc_axi_rdata(31 downto 0),
+ s_axi_rresp => uc_axi_rresp(1 downto 0),
+ s_axi_rvalid => uc_axi_rvalid(0),
+ s_axi_rready => uc_axi_rready(0),
+
+
+ ip2intc_irpt => u0_int,
+ freeze => '0',
+
+ sin => u0_rx,
+ sout => u0_tx
+
+-- baudoutn : out STD_LOGIC;
+-- ctsn : in STD_LOGIC;
+-- dcdn : in STD_LOGIC;
+-- ddis : out STD_LOGIC;
+-- dsrn : in STD_LOGIC;
+-- dtrn : out STD_LOGIC;
+-- out1n : out STD_LOGIC;
+-- out2n : out STD_LOGIC;
+-- rin : in STD_LOGIC;
+-- rtsn : out STD_LOGIC;
+-- rxrdyn : out STD_LOGIC;
+-- txrdyn : out STD_LOGIC;
+);
+
+axi_uart16550_0_i1: entity work.axi_uart16550_0
+port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+
+
+
+ s_axi_awaddr => uc_axi_awaddr(44 downto 32),
+ s_axi_awvalid => uc_axi_awvalid(1),
+ s_axi_awready => uc_axi_awready(1),
+ s_axi_wdata => uc_axi_wdata(63 downto 32),
+ s_axi_wstrb => uc_axi_wstrb (7 downto 4),
+ s_axi_wvalid => uc_axi_wvalid(1),
+ s_axi_wready => uc_axi_wready(1),
+ s_axi_bresp => uc_axi_bresp(3 downto 2),
+ s_axi_bvalid =>uc_axi_bvalid(1),
+ s_axi_bready =>uc_axi_bready(1),
+ s_axi_araddr => uc_axi_araddr(44 downto 32),
+ s_axi_arvalid => uc_axi_arvalid(1),
+ s_axi_arready => uc_axi_arready(1),
+ s_axi_rdata => uc_axi_rdata(63 downto 32),
+ s_axi_rresp => uc_axi_rresp(3 downto 2),
+ s_axi_rvalid => uc_axi_rvalid(1),
+ s_axi_rready => uc_axi_rready(1),
+
+
+ ip2intc_irpt => u1_int,
+ freeze => '0',
+
+ sin => u1_rx,
+ sout => u1_tx
+
+-- baudoutn : out STD_LOGIC;
+-- ctsn : in STD_LOGIC;
+-- dcdn : in STD_LOGIC;
+-- ddis : out STD_LOGIC;
+-- dsrn : in STD_LOGIC;
+-- dtrn : out STD_LOGIC;
+-- out1n : out STD_LOGIC;
+-- out2n : out STD_LOGIC;
+-- rin : in STD_LOGIC;
+-- rtsn : out STD_LOGIC;
+-- rxrdyn : out STD_LOGIC;
+-- txrdyn : out STD_LOGIC;
+);
end Behavioural;
diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
index d297c7a..74025a8 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
@@ -10,38 +10,9 @@ set_property -dict [list \
CONFIG.NUM_MI {2} \
CONFIG.ID_WIDTH {12} \
CONFIG.S00_THREAD_ID_WIDTH {12} \
- CONFIG.S01_THREAD_ID_WIDTH {12} \
- CONFIG.S02_THREAD_ID_WIDTH {12} \
- CONFIG.S03_THREAD_ID_WIDTH {12} \
- CONFIG.S04_THREAD_ID_WIDTH {12} \
- CONFIG.S05_THREAD_ID_WIDTH {12} \
- CONFIG.S06_THREAD_ID_WIDTH {12} \
- CONFIG.S07_THREAD_ID_WIDTH {12} \
- CONFIG.S08_THREAD_ID_WIDTH {12} \
- CONFIG.S09_THREAD_ID_WIDTH {12} \
- CONFIG.S10_THREAD_ID_WIDTH {12} \
- CONFIG.S11_THREAD_ID_WIDTH {12} \
- CONFIG.S12_THREAD_ID_WIDTH {12} \
- CONFIG.S13_THREAD_ID_WIDTH {12} \
- CONFIG.S14_THREAD_ID_WIDTH {12} \
- CONFIG.S15_THREAD_ID_WIDTH {12} \
- CONFIG.S01_BASE_ID {0x00001000} \
- CONFIG.S02_BASE_ID {0x00002000} \
- CONFIG.S03_BASE_ID {0x00003000} \
- CONFIG.S04_BASE_ID {0x00004000} \
- CONFIG.S05_BASE_ID {0x00005000} \
- CONFIG.S06_BASE_ID {0x00006000} \
- CONFIG.S07_BASE_ID {0x00007000} \
- CONFIG.S08_BASE_ID {0x00008000} \
- CONFIG.S09_BASE_ID {0x00009000} \
- CONFIG.S10_BASE_ID {0x0000a000} \
- CONFIG.S11_BASE_ID {0x0000b000} \
- CONFIG.S12_BASE_ID {0x0000c000} \
- CONFIG.S13_BASE_ID {0x0000d000} \
- CONFIG.S14_BASE_ID {0x0000e000} \
- CONFIG.S15_BASE_ID {0x0000f000} \
- CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \
- CONFIG.M01_A00_BASE_ADDR {0x0000000000001000} \
+ CONFIG.S00_BASE_ID {0x80000000} \
+ CONFIG.M00_A00_BASE_ADDR {0x80000000} \
+ CONFIG.M01_A00_BASE_ADDR {0x80001000} \
] [get_ips axi_crossbar_0]
generate_target all [get_ips]
diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
index 92cf5d4..823fd0c 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
@@ -11,11 +11,18 @@ set_property -dict [list \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_USE_M_AXI_GP0 {1} \
CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
CONFIG.PCW_M_AXI_GP0_FREQMHZ {100} \
CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+ CONFIG.PCW_USE_M_AXI_GP1 {1} \
+ CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+ CONFIG.PCW_M_AXI_GP1_FREQMHZ {100} \
+ CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+ CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+ CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
CONFIG.PCW_USE_HIGH_OCM {1} \
CONFIG.PCW_EN_CLK0_PORT {1} \
@@ -27,6 +34,8 @@ set_property -dict [list \
CONFIG.PCW_EN_RST3_PORT {1} \
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
@@ -41,7 +50,8 @@ set_property -dict [list \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps}] [get_ips processing_system7_0]
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} \
+ ] [get_ips processing_system7_0]
generate_target all [get_ips]
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 6e90760..1639572 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -91,6 +91,11 @@ entity zynq7_wrapper is
hdmi_b_n : out std_logic;
hdmi_vcc : out std_logic;
+ u0_tx: out std_logic;
+ u0_rx: in std_logic;
+ u1_tx: out std_logic;
+ u1_rx: in std_logic;
+
scope_ch1: out std_logic
);
@@ -107,8 +112,8 @@ architecture arch of zynq7_wrapper is
signal emio_o : std_logic_vector(63 downto 0);
signal emio_t : std_logic_vector(63 downto 0);
- signal gp0_aclk : std_logic;
- signal gp0_nrst : std_logic;
+ signal gp01_aclk : std_logic;
+ signal gp01_nrst : std_logic;
signal gp0_arvalid : std_logic;
signal gp0_awvalid : std_logic;
@@ -148,7 +153,48 @@ architecture arch of zynq7_wrapper is
signal gp0_bresp : std_logic_vector ( 1 downto 0 );
signal gp0_rresp : std_logic_vector ( 1 downto 0 );
signal gp0_rdata : std_logic_vector ( 31 downto 0 );
-
+
+
+signal gp1_arvalid : std_logic;
+ signal gp1_awvalid : std_logic;
+ signal gp1_bready : std_logic;
+ signal gp1_rready : std_logic;
+ signal gp1_wlast : std_logic;
+ signal gp1_wvalid : std_logic;
+ signal gp1_arid : std_logic_vector ( 11 downto 0 );
+ signal gp1_awid : std_logic_vector ( 11 downto 0 );
+ signal gp1_wid : std_logic_vector ( 11 downto 0 );
+ signal gp1_arburst : std_logic_vector ( 1 downto 0 );
+ signal gp1_arlock : std_logic_vector ( 1 downto 0 );
+ signal gp1_arsize : std_logic_vector ( 2 downto 0 );
+ signal gp1_awburst : std_logic_vector ( 1 downto 0 );
+ signal gp1_awlock : std_logic_vector ( 1 downto 0 );
+ signal gp1_awsize : std_logic_vector ( 2 downto 0 );
+ signal gp1_arprot : std_logic_vector ( 2 downto 0 );
+ signal gp1_awprot : std_logic_vector ( 2 downto 0 );
+ signal gp1_araddr : std_logic_vector ( 31 downto 0 );
+ signal gp1_awaddr : std_logic_vector ( 31 downto 0 );
+ signal gp1_wdata : std_logic_vector ( 31 downto 0 );
+ signal gp1_arcache : std_logic_vector ( 3 downto 0 );
+ signal gp1_arlen : std_logic_vector ( 3 downto 0 );
+ signal gp1_arqos : std_logic_vector ( 3 downto 0 );
+ signal gp1_awcache : std_logic_vector ( 3 downto 0 );
+ signal gp1_awlen : std_logic_vector ( 3 downto 0 );
+ signal gp1_awqos : std_logic_vector ( 3 downto 0 );
+ signal gp1_wstrb : std_logic_vector ( 3 downto 0 );
+ signal gp1_arready : std_logic;
+ signal gp1_awready : std_logic;
+ signal gp1_bvalid : std_logic;
+ signal gp1_rlast : std_logic;
+ signal gp1_rvalid : std_logic;
+ signal gp1_wready : std_logic;
+ signal gp1_bid : std_logic_vector ( 11 downto 0 );
+ signal gp1_rid : std_logic_vector ( 11 downto 0 );
+ signal gp1_bresp : std_logic_vector ( 1 downto 0 );
+ signal gp1_rresp : std_logic_vector ( 1 downto 0 );
+ signal gp1_rdata : std_logic_vector ( 31 downto 0 );
+
+
signal hp0_aclk : std_logic;
signal hp0_nrst : std_logic;
signal hp0_arvalid : std_logic;
@@ -259,10 +305,10 @@ begin
DDR_DRSTB => ddr_reset_n_io,
DDR_WEB => ddr_we_n_io,
FCLK_CLK0 => eth0_clk_o,
- FCLK_CLK1 => gp0_aclk,
+ FCLK_CLK1 => gp01_aclk,
FCLK_CLK2 => hp0_aclk,
FCLK_CLK3 => clk_50m_ps,
- FCLK_RESET1_N => gp0_nrst,
+ FCLK_RESET1_N => gp01_nrst,
FCLK_RESET2_N => hp0_nrst,
FCLK_RESET3_N => sys_rst_n,
@@ -320,7 +366,7 @@ begin
M_AXI_GP0_AWLEN => gp0_awlen ,
M_AXI_GP0_AWQOS => gp0_awqos ,
M_AXI_GP0_WSTRB => gp0_wstrb ,
- M_AXI_GP0_ACLK => gp0_aclk ,
+ M_AXI_GP0_ACLK => gp01_aclk ,
M_AXI_GP0_ARREADY => gp0_arready ,
M_AXI_GP0_AWREADY => gp0_awready ,
M_AXI_GP0_BVALID => gp0_bvalid ,
@@ -333,6 +379,47 @@ begin
M_AXI_GP0_RRESP => gp0_rresp ,
M_AXI_GP0_RDATA => gp0_rdata ,
+
+ M_AXI_GP1_ARVALID => gp1_arvalid ,
+ M_AXI_GP1_AWVALID => gp1_awvalid ,
+ M_AXI_GP1_BREADY => gp1_bready ,
+ M_AXI_GP1_RREADY => gp1_rready ,
+ M_AXI_GP1_WLAST => gp1_wlast ,
+ M_AXI_GP1_WVALID => gp1_wvalid ,
+ M_AXI_GP1_ARID => gp1_arid ,
+ M_AXI_GP1_AWID => gp1_awid ,
+ M_AXI_GP1_WID => gp1_wid ,
+ M_AXI_GP1_ARBURST => gp1_arburst ,
+ M_AXI_GP1_ARLOCK => gp1_arlock ,
+ M_AXI_GP1_ARSIZE => gp1_arsize ,
+ M_AXI_GP1_AWBURST => gp1_awburst ,
+ M_AXI_GP1_AWLOCK => gp1_awlock ,
+ M_AXI_GP1_AWSIZE => gp1_awsize ,
+ M_AXI_GP1_ARPROT => gp1_arprot ,
+ M_AXI_GP1_AWPROT => gp1_awprot ,
+ M_AXI_GP1_ARADDR => gp1_araddr ,
+ M_AXI_GP1_AWADDR => gp1_awaddr ,
+ M_AXI_GP1_WDATA => gp1_wdata ,
+ M_AXI_GP1_ARCACHE => gp1_arcache ,
+ M_AXI_GP1_ARLEN => gp1_arlen ,
+ M_AXI_GP1_ARQOS => gp1_arqos ,
+ M_AXI_GP1_AWCACHE => gp1_awcache ,
+ M_AXI_GP1_AWLEN => gp1_awlen ,
+ M_AXI_GP1_AWQOS => gp1_awqos ,
+ M_AXI_GP1_WSTRB => gp1_wstrb ,
+ M_AXI_GP1_ACLK => gp01_aclk ,
+ M_AXI_GP1_ARREADY => gp1_arready ,
+ M_AXI_GP1_AWREADY => gp1_awready ,
+ M_AXI_GP1_BVALID => gp1_bvalid ,
+ M_AXI_GP1_RLAST => gp1_rlast ,
+ M_AXI_GP1_RVALID => gp1_rvalid ,
+ M_AXI_GP1_WREADY => gp1_wready ,
+ M_AXI_GP1_BID => gp1_bid ,
+ M_AXI_GP1_RID => gp1_rid ,
+ M_AXI_GP1_BRESP => gp1_bresp ,
+ M_AXI_GP1_RRESP => gp1_rresp ,
+ M_AXI_GP1_RDATA => gp1_rdata ,
+
S_AXI_HP0_ACLK => hp0_aclk,
S_AXI_HP0_ARADDR => hp0_araddr,
S_AXI_HP0_ARBURST => "01",
@@ -419,8 +506,8 @@ begin
addr_width => addr_width
)
port map (
- s_axi_aclk => gp0_aclk,
- s_axi_aresetn => gp0_nrst,
+ s_axi_aclk => gp01_aclk,
+ s_axi_aresetn => gp01_nrst,
s_axi_awid => gp0_awid ,
s_axi_awaddr => gp0_awaddr,
@@ -466,6 +553,56 @@ begin
);
+ kbd_uarts_i: entity work.kbd_uarts
+ port map (
+ s_axi_aclk => gp01_aclk,
+ s_axi_aresetn => gp01_nrst,
+
+ s_axi_awid => gp1_awid ,
+ s_axi_awaddr => gp1_awaddr,
+ s_axi_awlen => gp1_awlen ,
+ s_axi_awsize => gp1_awsize ,
+ s_axi_awburst => gp1_awburst ,
+ s_axi_awlock => gp1_awlock ,
+ s_axi_awcache => gp1_awcache ,
+ s_axi_awprot => gp1_awprot ,
+ s_axi_awvalid => gp1_awvalid ,
+ s_axi_awready => gp1_awready ,
+ s_axi_wdata => gp1_wdata ,
+ s_axi_wstrb => gp1_wstrb ,
+ s_axi_wlast => gp1_wlast ,
+ s_axi_wvalid => gp1_wvalid ,
+ s_axi_wready => gp1_wready ,
+ s_axi_bid => gp1_bid ,
+ s_axi_bresp => gp1_bresp ,
+ s_axi_bvalid => gp1_bvalid ,
+ s_axi_bready => gp1_bready ,
+ s_axi_arid => gp1_arid ,
+ s_axi_araddr => gp1_araddr,
+ s_axi_arlen => gp1_arlen,
+ s_axi_arsize => gp1_arsize ,
+ s_axi_arburst => gp1_arburst ,
+ s_axi_arlock => gp1_arlock ,
+ s_axi_arcache => gp1_arcache ,
+ s_axi_arprot => gp1_arprot ,
+ s_axi_arvalid => gp1_arvalid ,
+ s_axi_arready => gp1_arready ,
+ s_axi_rid => gp1_rid ,
+ s_axi_rdata => gp1_rdata ,
+ s_axi_rresp => gp1_rresp ,
+ s_axi_rlast => gp1_rlast ,
+ s_axi_rvalid => gp1_rvalid ,
+ s_axi_rready => gp1_rready ,
+
+u0_tx => u0_tx,
+u0_rx => u0_rx,
+
+u1_tx => u1_tx,
+u1_rx => u1_rx
+);
+
+
+
hp0_araddr <= (others => '0');
hp0_arvalid <= '0';
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-17 20:11:45 +0000