diff options
Diffstat (limited to 'fpga/hp_lcd_driver')
| -rw-r--r-- | fpga/hp_lcd_driver/.gitignore | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/Makefile | 11 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/ep4ce15f23c8.mk | 132 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/ep4ce15f23c8_loader.mk | 24 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/flash_loader.loader_qsft | 25 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/flash_loader.vhdl | 102 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/quartus.mk | 135 |
7 files changed, 299 insertions, 132 deletions
diff --git a/fpga/hp_lcd_driver/.gitignore b/fpga/hp_lcd_driver/.gitignore index a7f48f7..d7fb5c6 100644 --- a/fpga/hp_lcd_driver/.gitignore +++ b/fpga/hp_lcd_driver/.gitignore @@ -1,3 +1,5 @@ build_spartan6/ build_smh-ac415/ build_smh-ac415b/ +build_loader/ +NOT/ diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile index f9ce72b..4e2be26 100644 --- a/fpga/hp_lcd_driver/Makefile +++ b/fpga/hp_lcd_driver/Makefile @@ -1,4 +1,4 @@ -TARGETS= smh-ac415b #spartan6 #ep4ce6 smh-ac415 +TARGETS= smh-ac415b #spartan6 #ep4ce6 smh-ac415 #fish:smh-ac415 default: ${TARGETS:%=build_%/hp_lcd_driver.svf} @@ -6,9 +6,18 @@ default: ${TARGETS:%=build_%/hp_lcd_driver.svf} smh-ac415: build_smh-ac415/hp_lcd_driver.svf spartan6: build_spartan6/hp_lcd_driver.svf + build_%/hp_lcd_driver.svf: dummy ${MAKE} -f ${@:build_%/hp_lcd_driver.svf=%}.mk +build_smh-ac415/hp_lcd_driver.svf: build_flash_loader/output_files/flash_loader.sof + +build_flash_loader/output_files/flash_loader.sof: dummy + ${MAKE} -f ep4ce15f23c8_loader.mk + + + + clean: for i in ${TARGETS}; do ${MAKE} -f $$i.mk $@; done diff --git a/fpga/hp_lcd_driver/ep4ce15f23c8.mk b/fpga/hp_lcd_driver/ep4ce15f23c8.mk index 390dc5b..7597aad 100644 --- a/fpga/hp_lcd_driver/ep4ce15f23c8.mk +++ b/fpga/hp_lcd_driver/ep4ce15f23c8.mk @@ -17,137 +17,7 @@ ASM_ARGS = STA_ARGS = CPF_ARGS = -c -q 1MHZ -g 3.3 -n p -GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd} -QIP=${GEN_VSRCS:%.vhd=%.qip} -BASE=${BUILD}/${DESIGN_NAME} -QSF=${BASE}.qsf -QPF=${BASE}.qpf -MAP=${BUILD}/${OF}/$(PROJECT).map.rpt -FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt -ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt -ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt -SOF=${BUILD}/${OF}/${PROJECT}.sof -COF=${BUILD}/${OF}/${PROJECT}.cof -JIC=${BUILD}/${OF}/${PROJECT}.jic -CDF=${BUILD}/${OF}/${PROJECT}.cdf -SVF=${BUILD}/${PROJECT}.svf -PSVF=${BUILD}/${PROJECT}-p.svf -default:${SVF} ${PSVF} - echo ${PSVF} - - -${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl - cat $< > ${BUILD}/${<:%.vhdl=%.vhd} - (cd ${BUILD} && ../scripts/run_in_x run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD})) - - -${QSF}: ${PRJ} ${DESIGN_NAME}.${BOARD}_qsft - mkdir -p ${BUILD} - rm -f $@ - echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@ - echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@ - echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@ - echo 'set_global_assignment -name DEVICE ${PART}' >> $@ - cat ${DESIGN_NAME}.${BOARD}_qsft >> $@ - for file in ${GEN_VSRCS} ${VSRCS}; do \ - echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \ - done - - - -${QPF}: - mkdir -p ${BUILD} - rm -f $@ - echo 'PROJECT_REVISION = "${TOP}"' > $@ - - -map: ${MAP} -${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS} ${QIP} - (cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT}) - -fit: ${FIT} -${FIT}:${MAP} - (cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT)) - -asm: ${ASM} -sof: ${ASM} -${SOF} ${ASM}:${FIT} - (cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT)) - -sta: ${STA} -${STA}:${FIT} - (cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT)) - - -svf:${SVF} -${SVF}:${SOF} - (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) -${JIC}:${SOF} - (cd ${BUILD} && run_quartus quartus_cpf -c -s ${PART} -d ${CPART} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) - - -${CDF}:${JIC} - echo 'JedecChain;' > $@ - echo ' FileRevision(JESD32A);' >> $@ - echo ' DefaultMfr(6E);' >> $@ - echo '' >> $@ - echo ' P ActionCode(Ign)' >> $@ - echo ' Device PartName(EP4CE15F23) Path("/root/projects/hp_instrument_lcds/fpga/hp_lcd_driver/fl2/output_files/") File("flash_loader.sof") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 1) SFLPath("$(call abspath,${JIC})"));' >> $@ - echo '' >> $@ - echo 'ChainEnd;' >> $@ - echo '' >> $@ - echo 'AlteraBegin;' >> $@ - echo ' ChainType(JTAG);' >> $@ - echo 'AlteraEnd;' >> $@ - -${PSVF}:${CDF} - (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) - - - -tidy: - git diff --exit-code -s ${VSRCS} - for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done - - - -# -# -##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg -# -#FIT_ARGS = -#ASM_ARGS = -# -#SVF=${PROJECT}.svf -# -# -# -#default: ${SVF} -# -#${SVF}: ${BUILD}/${PROJECT}.svf -# cat $< > $@ || /bin/rm -f $@ -# -#program: ${SVF} -# ${OPENOCD} -c "init; svf $<; exit" -# -#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt ${BUILD}/${PROJECT}.svf -# -clean: - rm -rf db ${BUILD} *.orig *.bak incremental_db db - -# -# -# -# -# -# - -#tidy: -# for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done -# -# - -.PRECIOUS: +include quartus.mk diff --git a/fpga/hp_lcd_driver/ep4ce15f23c8_loader.mk b/fpga/hp_lcd_driver/ep4ce15f23c8_loader.mk new file mode 100644 index 0000000..1ad68f0 --- /dev/null +++ b/fpga/hp_lcd_driver/ep4ce15f23c8_loader.mk @@ -0,0 +1,24 @@ +include relpath.mk + +FAMILY=Cyclone IV E +PART=EP4CE15F23C8 +CPART=EPCS16 +TOP=flash_loader +BOARD=loader +BUILD=build_${BOARD} +OF=output_files + +PROJECT = flash_loader +VSRCS = +IPS= flash_loader.vhdl + +DESIGN_NAME=${TOP} + +MAP_ARGS = --smart +FIT_ARGS = +ASM_ARGS = +STA_ARGS = +CPF_ARGS = -c -q 1MHZ -g 3.3 -n p + +include quartus.mk + diff --git a/fpga/hp_lcd_driver/flash_loader.loader_qsft b/fpga/hp_lcd_driver/flash_loader.loader_qsft new file mode 100644 index 0000000..0e45e44 --- /dev/null +++ b/fpga/hp_lcd_driver/flash_loader.loader_qsft @@ -0,0 +1,25 @@ +#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +#set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00 APRIL 20, 2025" +#set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" + +set_parameter -name target "cyclone4" + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + + + + diff --git a/fpga/hp_lcd_driver/flash_loader.vhdl b/fpga/hp_lcd_driver/flash_loader.vhdl new file mode 100644 index 0000000..41eb1df --- /dev/null +++ b/fpga/hp_lcd_driver/flash_loader.vhdl @@ -0,0 +1,102 @@ +-- megafunction wizard: %Serial Flash Loader% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altserial_flash_loader + +-- ============================================================ +-- File Name: flash_loader.vhd +-- Megafunction Name(s): +-- altserial_flash_loader +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY flash_loader IS + PORT + ( + noe_in : IN STD_LOGIC + ); +END flash_loader; + + +ARCHITECTURE SYN OF flash_loader IS + + + + + COMPONENT altserial_flash_loader + GENERIC ( + enable_quad_spi_support : NATURAL; + enable_shared_access : STRING; + enhanced_mode : NATURAL; + intended_device_family : STRING; + lpm_type : STRING + ); + PORT ( + noe : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + + altserial_flash_loader_component : altserial_flash_loader + GENERIC MAP ( + enable_quad_spi_support => 0, + enable_shared_access => "OFF", + enhanced_mode => 1, + intended_device_family => "Cyclone IV E", + lpm_type => "altserial_flash_loader" + ) + PORT MAP ( + noe => noe_in + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0" +-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF" +-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in" +-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/fpga/hp_lcd_driver/quartus.mk b/fpga/hp_lcd_driver/quartus.mk new file mode 100644 index 0000000..9d1cd0c --- /dev/null +++ b/fpga/hp_lcd_driver/quartus.mk @@ -0,0 +1,135 @@ +GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd} +QIP=${GEN_VSRCS:%.vhd=%.qip} + +BASE=${BUILD}/${DESIGN_NAME} +QSF=${BASE}.qsf +QPF=${BASE}.qpf +MAP=${BUILD}/${OF}/$(PROJECT).map.rpt +FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt +ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt +ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt +SOF=${BUILD}/${OF}/${PROJECT}.sof +COF=${BUILD}/${OF}/${PROJECT}.cof +JIC=${BUILD}/${OF}/${PROJECT}.jic +CDF=${BUILD}/${OF}/${PROJECT}.cdf +SVF=${BUILD}/${PROJECT}.svf +PSVF=${BUILD}/${PROJECT}-p.svf + +default:${SVF} ${PSVF} + echo ${PSVF} + + +${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl + cat $< > ${BUILD}/${<:%.vhdl=%.vhd} + (cd ${BUILD} && ../scripts/run_in_x run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD})) + + +${QSF}: ${PRJ} ${DESIGN_NAME}.${BOARD}_qsft + mkdir -p ${BUILD} + rm -f $@ + echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@ + echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@ + echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@ + echo 'set_global_assignment -name DEVICE ${PART}' >> $@ + cat ${DESIGN_NAME}.${BOARD}_qsft >> $@ + for file in ${GEN_VSRCS} ${VSRCS}; do \ + echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \ + done + + + +${QPF}: + mkdir -p ${BUILD} + rm -f $@ + echo 'PROJECT_REVISION = "${TOP}"' > $@ + + +map: ${MAP} +${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS} ${QIP} + (cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT}) + +fit: ${FIT} +${FIT}:${MAP} + (cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT)) + +asm: ${ASM} +sof: ${ASM} +${SOF} ${ASM}:${FIT} + (cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT)) + +sta: ${STA} +${STA}:${FIT} + (cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT)) + + +svf:${SVF} +${SVF}:${SOF} + (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) + +${JIC}:${SOF} + (cd ${BUILD} && run_quartus quartus_cpf -c -s ${PART} -d ${CPART} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) + + +${CDF}:${JIC} + echo 'JedecChain;' > $@ + echo ' FileRevision(JESD32A);' >> $@ + echo ' DefaultMfr(6E);' >> $@ + echo '' >> $@ + echo ' P ActionCode(Ign)' >> $@ + echo ' Device PartName(EP4CE15F23) Path("$(call abspath,build_loader/output_files)/") File("flash_loader.sof") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 1) SFLPath("$(call abspath,${JIC})"));' >> $@ + echo '' >> $@ + echo 'ChainEnd;' >> $@ + echo '' >> $@ + echo 'AlteraBegin;' >> $@ + echo ' ChainType(JTAG);' >> $@ + echo 'AlteraEnd;' >> $@ + +${PSVF}:${CDF} + (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) + + + +tidy: + git diff --exit-code -s ${VSRCS} + for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done + + + +# +# +##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg +# +#FIT_ARGS = +#ASM_ARGS = +# +#SVF=${PROJECT}.svf +# +# +# +#default: ${SVF} +# +#${SVF}: ${BUILD}/${PROJECT}.svf +# cat $< > $@ || /bin/rm -f $@ +# +#program: ${SVF} +# ${OPENOCD} -c "init; svf $<; exit" +# +#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt ${BUILD}/${PROJECT}.svf +# +clean: + rm -rf db ${BUILD} *.orig *.bak incremental_db db + +# +# +# +# +# +# + +#tidy: +# for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done +# +# + +.PRECIOUS: + |